CN1146075A - 用于电子封装的超薄贵金属涂层 - Google Patents
用于电子封装的超薄贵金属涂层 Download PDFInfo
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- CN1146075A CN1146075A CN96108768A CN96108768A CN1146075A CN 1146075 A CN1146075 A CN 1146075A CN 96108768 A CN96108768 A CN 96108768A CN 96108768 A CN96108768 A CN 96108768A CN 1146075 A CN1146075 A CN 1146075A
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Abstract
提供一种位于镍表面上的贵金属超薄组合物层。该组合物的厚度可在2.5-11微英寸之间变化,从镍开始依次包括:0.5-3.5微英寸的钯或金的触击电镀层;0.5-5微英寸厚的钯—镍合金层,其中,镍的重量占合金总重量的10-90%;0.5-5微英寸厚的钯层和0-1微英寸厚的金层。金层用于期望达到较钯的焊料浸湿速度更高的焊料浸湿速度的场合。适用的超薄涂层可通过双卷盘金属淀积工艺,作多层的淀积来最有效地获得。
Description
本发明涉及一种特别适用于集成电路元件封装的可焊接的超薄贵金属保护涂层。
具有密封于保护外壳中的一个集成电路(IC)单元和一个引线框架的集成电路(IC)元件,广泛应用于多种产品之中,包括消耗性电子仪器、家用设备、计算机、汽车、电信装置、机器人技术和军用设备。IC单元包括:集成电路芯片,具有一或多个IC芯片的混合集成电路组件,以及其他的制作于塑料或陶瓷支座上的电子元件。
一种将IC单元与IC元件外部电路互连的方法是采用一个引线框架的形式。引线框架由高导电性能的材料如铜或铜合金制成,或把一个金属坯压印或刻蚀成几个引线(或指状引线)来确定一个中心区域以安装IC单元。引线框架通常包括一个安装片和几个从此安装片相邻位置伸出的分离的引线条。在那些没有这种安装片的场合,则是这样地来作引线,即把引线端与IC单元的周边交叠或使引线端与IC单元相接或离开一段距离。
有几种连接工艺可用于连接一个封装中的引线框架与IC元件。这些工艺包括金属丝接合、焊接、小片连接和密封。最常用的是金属丝接合和焊接。所有情况下,连接都需要引线框架表面具备特殊的质量。最常见的是要求此种表面一定是无氧化物的,并易于同其他元件,例如同金或铝引线,填充有环氧树脂或焊料的银相互作用。为了能以可重复的方式获得这种连接,引线框架表面的光洁度起着重要作用。
引线框架坯料一般是在引线框架的表面镀了一层镍。镍镀层用来作为一个阻挡层,阻止引线框架表面上铜向内部扩散和铜反应物如铜氧化物和铜硫化物的形成。可惜,厚度小于400微英寸(10.2微米)的镍层含有孔隙,通过这些孔隙会发生铜向引线框架表面的迁移和扩散。但是厚度超过400微英寸的镍层又会在引线最终弯曲时引起裂痕。
为了消除或者至少是减小铜向不到400微英寸厚的镍层扩散的效应,所做的一种尝试是在镍层的顶部淀积一薄层钯或钯/镍合金(参见1987年12月23日公布的欧洲专利申请号为0250146的专利文献)。然而,铜的腐蚀物,包括氧化物、硫化物和铜的其他反应产物会不断地出现在引线框架上,污染引线框架的表面并降低了它的与金属丝接合和焊接的能力。克服这些缺点的进一步尝试是在铜基底上镀上若干层:从铜基底开始,依序包括一个5微英寸(127纳米)厚的镍的触击电镀(strike)层,一个3微英寸(76纳米)厚的钯/镍合金层,一个镍层和一个钯层。镍的触击电镀层和钯/镍合金层用作阻挡层,阻止铜离子移到引线框架的表面以便允许使用较薄(小于400微英寸)的镍层(参见1989年10月4日公布的欧洲专利申请号为0335608的专利文献)。但是,这种层的组合也无法作出一种产品,可以抵抗密封元件制作过程中需要的工艺步骤所带来的各种效应。
引线表面的镍和镍生成物如氧化镍的存在,与铜和铜生成物的存在相比,从可焊性这一点而言对于引线表面具有更大的利害关系。这种表面上少至5%甚至更少的镍原子就会对此表面的可焊性产生不利影响。镍和镍生成物,由于各种工艺步骤中效应的存在,包括高温和氧化状态,会扩散到前述的若干相叠层的金属元件中并与之相互作用。镍生成物,如镍氧化物,影响焊接与接合工艺。此外,这类反应产物难以用常规的酸清洗除去。
公布于1994年11月1日的授予J.A.Abys等人的美国专利5360991号,描述了一种引线框架,它包括一种基底金属,一种位于此基底金属上的镍层和一种位于此镍层上的保护性组合式金属层。这一组合层从镍层开始依次包括一种钯的触击电镀或软金的触击电镀层,一种钯-镍合金层,一种钯层和一种金层。取决于工艺和使用条件,特别是经历了250℃以上的热处理条件后,各种层的厚度要足以有效地阻止铜和镍以及各自的腐蚀物迁移到引线框架的表面。通常上述组合层淀积的总厚度在10-300微英寸的范围内,其中金层厚度为1-100微英寸。但是,总希望能减少贵重金属的用量,甚至不使用金,而仍能保持引线框架表面具有优良的可焊接特性。
通过提供一种位于镍表面上的贵金属的超薄组合层,已使上述问题得到了解决。该组合层的厚度可在2.5-11微英寸之间变化,从镍开始顺次包括:一种0.5-3.5微英寸的钯或金的触击电镀层;一种0.5-5微英寸厚的钯-镍合金层,此合金层中,镍和重量占此合金总重量的10-90%;一种0.5-5微英寸厚的钯层以及一种0-1微英寸厚的金层。金层用于期望达到较钯的焊料浸湿速度更高的焊料浸湿速度的场合。适用的超薄涂层可通过双卷盘(reel-to-reel)金属淀积工艺,作多层淀积来最有效地获得。
图1是一种典型的现有技术引线框架的示意性顶视图,此引线框架上安装有一个IC单元;
图2是一种密封元件沿图1的2-2线所取截面的示意性侧视图;
图3是引线的一个纵向的小部分截面的放大示意图,显示了依据本发明的组合式涂层。
图1示出了一个用于集成电路单元11(用虚线表示)的典型引线框架的顶视图。此引线框架包括上面接合有一个IC单元的片12和引线13。暂时与引线13互连的堤棒14,后者在封装介质加到虚线15所示的区域后被除掉。
为了用实例加以说明,参照一个IC封装对本发明加以描述,其中的封装介质是一种模制的塑性材料,例如环氧树脂。然而,本发明也可以以其他方式加以实施,其中的IC单元和引线密封于一个陶瓷或者一个陶瓷和金属混合的封装中。本发明也可用于在一个绝缘基座上装有金属型板的印刷电路板。
图2示出了一个封装16的示意性截面侧视图。这一封装包括IC单元11,片12和引线13。IC单元用焊剂或粘合剂17结合在片上,通过金属丝或接头18与引线电连接。IC单元11,片12,金属丝18和与片相接的部分引线密封于一个模制封装介质19中。引线包括一种基底金属20,一种位于基底金属上的镍层21和镍层上的一种保护性组合层22。
基底金属20一般为铜或铜合金。铜合金,例如CDA No.102(99.95%的Cu,其余包括Ag),CDA No.103(99.95%的Cu加上0.001-0.005%的P,还有Au),No.151(99.9%的Cu,0.1%的Zn),No.155(97.8%的Cu,0.034%的Ag,0.058%的P,0.11%的Mg),No.194(97.5%的Cu,2.35%的Fe,0.003%的P,0.12%的Zn)和KLF125(94.55%的Cu,3.2%的Ni,1.25%的Sn,0.7%的Si),它们代表了目前用于引线框架的材料。其他的合金,如铁/镍合金也可以用作基底金属。
为解决铜,镍及其反应产物向引线框架的引线表面扩散的问题,可以在镍层21的顶部淀积具有多层结构的保护性组合层22,来阻止或至少是明显减少铜和铜的反应产物及镍和镍的反应产物向引线外部表面上的迁移。图3所示的是一个放大的代表引线13部分截面的示意图。组合层22从镍层21开始按升序包括一个钯或软金的触击电镀层23,一种钯-镍合金层24和一种钯层25。作为选择,组合层也可以包括一种金的薄层26。淀积的组合层的总厚度可以在约2.5-11微英寸范围内变动,最好在2.5-10微英寸的范围内。此组合层位于厚度一般为20-200微英寸(510-5100纳米)的镍层上。
位于镍和钯-镍合金层之间的作为一种接合(粘合)层的钯或软金的触击电镀层23淀积的厚度为0.5-3.5微英寸,优选0.5-3微英寸,特别推荐1-3微英寸(25-76纳米)。薄于0.5微英寸的层供接合用时可能是不够的,而3.5微英寸或更厚的层又不会提供任何附加的优点。钯或金的触击电镀层是一种具有低孔隙率的层,除了它所具有的接合特性外,还有助于生长减小了孔隙率的后续层,其结果则又减少了铜和镍向顶层的潜在的扩散。参考公布于1993年1月12日的授予J.A.Abys等人的美国专利号为4178475的专利文献,这里最好是用其中描述的一种钯的触击电镀溶液来淀积钯的触击电镀层。Frank H.Reed和WilliamGoldie所著书“Gold Plating technology”(ElectrochemicalPublications Limited,8 Barns Street,Ayr,Scotland,Third printing1987)中的26页和46页公开了用于淀积软金的组成例子和电镀条件。
淀积的钯-镍合金层24厚度在0.5-5微英寸的范围内,最好为0.5-4微英寸,特别推荐1-4微英寸(25-100纳米)。生长于钯或软金触击电镀层上的钯-镍合金层是一个低孔隙率层。这一层的主要用途是阻止或至少减少铜、铁和镍及其反应产物如氧化物向引线表面,特别是向被焊接的表面扩散。薄于0.5微英寸的层作为铜和镍扩散的一个阻挡层可能是不够的,而比5微英寸厚的层又不能提供附加的优点。Pd-Ni合金中镍的重量含量为10%-90%,最好为10%-30%。这里参考了两份同时公布于1990年3月27日的授予J.A.Abys等人的美国专利号为4911798和4911799的专利文献,最好用其中描述的一种钯电镀液来淀积钯-镍合金。
淀积的钯层25厚度在0.5-5微英寸的范围内,最好为0.5-4微英寸,特别推荐1-4微英寸(25-100纳米)。这一层的主要用途是进一步减小位于其下面的层中孔隙率的影响,并且阻止或至少是减慢镍从钯镍合金层24向用于焊接的表面的扩散。薄于0.5微英寸的层作为来自钯镍合金层中镍扩散的阻挡层可能是不够的,而比5微英寸厚的层又不会带来附加的好处。这一层的厚度依赖于Pd-Ni合金层的厚度和其中Ni的含量。Pd-Ni合金层中Ni的含量越高,钯层就应越厚以阻止或至少减慢Ni进入和穿过Pd层的扩散。这里参考了公布于1990年3月27日的授予J.A.Abys等人的美国专利4911799号,最好用其中描述的钯电镀液来淀积钯层。
一种供选择的金层淀积厚度为0-1微英寸(0-25纳米)。这一金层用于期望用焊剂使相应表面高速润湿的场合。在用试样号1、2和3代表的应用中,钯或金触击电镀的、Pd-Ni合金的以及Pd的薄层能提供充分的保护而无需使用过多的昂贵的金。在用试样号4和5代表的应用中,由两层为0.5-2微英寸的Pd或Au触击电镀、Pd-Ni合金和Pd等的极薄层和仅有1微英寸厚的金共同构成的组合物,为330℃以下的应用提供了充分的保护。金层可使用电镀金的任何常规溶液来淀积。最好用高效镀液将金层淀积成软金,Frank H.Reed和William Goldie所著的书:“Gold Plating Technology”(Electrochemical PublicationsLimited,8 Barns Street,Ayr,Scotland,Third Pirnting 1987)中的26页和46页公开了用于淀积软金的组成的例子和淀积软金的电镀条件。
当把上述组合物用于330℃或更低温度下处理时,可以不必使用金,淀积的Pd或金的触击电镀层的厚度至少为1微英寸,Pd-Ni合金层的厚度至少为2微英寸,Pd层厚度至少为1微英寸。在使用金的那些场合中,是期望达到焊剂高速润湿的目的,所用的三层中,每一层的厚度至少为0.5微英寸,后面紧跟一个厚度约为1微英寸的金层。
为获得适用的超薄涂层,各种层是用双卷盘金属淀积工艺来淀积的。这种工艺还可以包括在双卷盘工序中于基底金属上淀积镍层。由于无法满足这种金属淀积的要求时可能会导致保护不充分,而需要厚得多的金属镀层。双卷盘金属淀积镀层工艺为本领域所周知,因而无需对其进行特别解释。
金属淀积完成后,开始进行IC单元安装到引线框架上的工序。以一种已知的方式如焊接或粘附将IC单元11安装到引线框架10的片12的部分上。IC单元11和引线13的电连接通过金属丝或接头18来完成。重要的是引线的表面应可与金属丝接合。此外,没有不希望的铜和/或镍的反应产物的可焊接的表面也适合用于金属丝的接合。带有不希望的铜或镍的反应产物的表面可能无法与金属丝接合或接合得很差,以致无法得到适用的连接,即使暂时连接上,工作时也会断开。如果接合处引线的外部表面有一薄层氧化镍,连接效果会更差。铜的反应产物,例如铜的氧化物和硫化物,可以在IC单元安装、金属丝接合和焊接前通过清洗表面来除去。然而,这种镍的副产品如氧化镍附着力很强,用常规洗液很难除去。
IC和金属丝接合的工艺步骤完成后,将每一组件放于一个模塑设备中,将塑性密封材料注入到每个IC单元及其与引线连接部分的周围,从而形成一个外部IC单元封装。从模塑设备中取出组件后,通过从引线框架中分离引线的端部并除去引线间的堤部,将模塑IC封装与引线框架分离。然后将引线弯成需要的形状,如鸥翼、“J”或平接形式。暴露于模塑料之外的引线部分用有机溶剂和等离子体清洗并焊接到安装板的焊块上。一个实例是将清洗后的引线放于与粘附在安装板上的焊料隆起物或焊料接触的地方,并通过加热而焊接到安装板的焊块上。在另一个实例中,将清洗后的引线浸泡于一个熔融的焊料池中,然后放于安装板上与熔剂热焊块相接触。
在IC单元和安装板之间具有可靠的连接是绝对必要的,引线应当具备可焊接的表面。这意味着引线上固定到板上焊块处的这部分的表面应当可以得到一个充分连续的焊剂涂层。带有覆盖95%或更多焊接区域的焊料涂层的表面作为可焊接表面是合格的。另外,表面的焊剂涂层每平方厘米的孔隙数应当很小,如小于28-30个,最好每平方厘米少于25个孔隙。
在制作这一密封元件的工艺过程中,包括那些能影响氧化、交互扩散沾污、蒸汽沾污、开裂以及沾污表面的损坏等在内,对引线框架进行了大量的工艺处理。这些处理步骤包括:使热塑材料注射模塑形成为一个塑料骨架(150℃,30分钟),电路连接,热扩展连接(150℃,30分钟),修整并形成引线,用氧等离子体清洗或激光H2O2清洗除去所有有机杂质,元件连接包括小片与环氧树脂粘结处理(165℃,1小时),涂层附着(165℃,1小时)和实现结构应力释除和整体测试的老化(125℃/24小时)。这些处理步骤在本领域内是公知的,无需进一步的描述。塑料模塑封装的形成和各焊接工序可在高达250℃的温度下进行。
为确定引线框架的表面用于可靠的连接是否合适,对带有或不带有密封材料的引线框架进行了包括金属丝接合和可焊接性测试在内的可靠性测试。金属丝接合测试用来证实这种接合类型的可重复性及可靠性。例如,AT&T标准的A-87AL1919确定了失败和合格准则的模式。一般工业用户对金属丝接合所进行的测试包括预处理,如热老化或等离子体清洗等步骤。可焊接性测试的一例是一种军用规格883C,方法2003,它用作可接受的合格标准。这一标准包括在95℃和90%的相对湿度下进行蒸汽老化4、8或16个小时。这被设想用于模拟至少6个月的贮存寿命。此后,将试样中露出的金属引线涂复非活性焊剂并在250℃的条件下浸润在焊剂中5秒。然后在放大10倍的情况下来评估试样的焊剂涂层。可焊接性合格的涂层必须具备至少95%范围的高质量的均匀焊剂,每平方厘米的孔隙数小于28-30个,最好少于25个孔隙。这里阐述的蒸汽老化测试方法虽然用于一般的焊剂涂层,但也可以用于测试非焊剂涂复的衬底。在所进行的测试中假定了测试表面能接收焊剂涂层。使用SO2气体进行的孔隙测试可根据ASTM B799-88,November 1988,页463-465中概述的内容。
当暴露于可引起涂层劣化的热漂移,氧和有机物中时,焊接被认为是电子封装中最敏感的步骤之一。其结果会导致缺乏可焊接性和产品失效。考虑到这一点,测试了带有超薄保护涂层的一系列多层涂层来确定它们是否能经受更高的温度以及等离子体处理等其他的环境破坏而仍然具有可焊接性。总厚度在2.5-11微英寸范围内的结构经证明能提供优良的接合特性。将某些熔融物涂布到SMT板上,这甚至在O2等离子体处理后仍显示出良好的性能。
由于在许多的应用中需要包括将已涂复的引线框架作热暴露,在热老化条件下使层与层之间的金属扩散,假如下面的金属扩散到更昂贵的金属表面层如镍扩散到金,都可以导致表面质量的下降。因此,除蒸汽老化以外,还希望对镀层表面施以热老化处理。现在还不存在标准化的热老化的必要条件。为了判断依据本发明的涂层在不同热状态下适合于可焊接的性能,对涂层施以一段时间的热测试,200℃下为1、2和5个小时,250℃下为5、10和15分钟,330℃下为1和2分钟。
热测试是在具有一个镍层的铜板上进行的,这一镍层上涂有总厚度为2.5-11微英寸的组合物。镍层以及组合物层22的厚度示于表1中。这一组合层从镍层开始顺次包括Pd触击电镀层,Pd-Ni(80/20)合金层和Pd层,以及可选择的金层。有关试样是在一个双卷盘生产线中制作的。这些试样涂有大于98%范围的焊剂。当进行一段时间的热处理:200℃下为1、2和5个小时,250℃下为5、10和15分钟,330℃下为1分钟,试样仍保持大于98%的焊剂范围。当对试样施以8小时的蒸汽老化(95℃,95%湿度)时,焊剂范围也维持足够高(>98%)。然而,在330℃时暴露于热老化中2分钟则会导致焊剂的范围小于90%。
表1示出了超薄保护涂层的各种组成。表2示出了用这些涂层所获得的效果的例子。表2中,P表示“通过”并代表>95%的可焊接性范围,M表示“临界”并代表不具可重复性的P的百分比,F表示“失效”并代表<95%的可焊接性范围。
表1
多层涂层的测试真值表
试样 | Ni(μ”) | Pd触击电镀(μ”) | PdNi(μ”) | Pd(μ”) | Au(μ”) |
1 | 36-43 | 2-3 | 3-4 | 3-4 | 0 |
2 | 33-44 | 2-3 | 3-4 | 2-3 | 0 |
3 | 29-41 | 1-2 | 2-3 | 1-2 | 0 |
4 | 20-28 | 0.5-1 | 0.5-1 | 0.5-1 | 1 |
5 | 28-34 | 1-2 | 1-2 | 1-2 | 1 |
表2
多层涂层的可焊接性热老化效应
温度
时间(min)试样#12345 | 200℃60 120 300P P PP P PP P F | 250℃5 10 15P PP PP PP P PP P P | 330℃1 2P FP FP FP MP M |
可将多层涂层设计成能通过产品的金属丝接合和可焊接性测试,而所述产品则处在暴露条件下来满足衬底在大范围内的热处理和“清洗”处理。试样1、2、3、4和5显示了优良的可焊接性(在250℃下,高达5小时)。在330℃时进行了1分钟的热测试后,试样1、2、3、4和5仍显示了合格的可焊接性能。后两种结构(试样4和5)在多层涂层的钯上还涂有一超薄的金涂层。这一变化所带来的好处大大超过了所增加的费用,因为甚至在老化测试后,一些实例仍能保持有1秒或稍低的湿焊速度。这些涂层相当经济并仍能满足用于高速金属丝接合的衬底温度条件。
对熟悉本领域的人员而言,可以容易地得知本发明的其余的优点和变形。因此,从更宽的角度来说,本发明并不局限于特定的描述,代表的元件以及所显示和描述的例子。因此,在不脱离后附的权利要求及其等同内容所限定的总体发明的精神和范围的情况下是可以作出种种变更形式的。
Claims (21)
1.一种IC封装,它包括至少一个IC单元和一些密封于一个保护封装中的引线,其中,所述引线包括一个基底金属,在这层基底金属上的镍层和在此镍层上面的若干金属层的组合物,所述组合物淀积的厚度在2.5-11微英寸的范围内,该组合物从镍层开始依次包括:0.5-3.5微英寸厚的钯或软金触击电镀层;0.5-5微英寸厚的钯-镍合金层,其中含有10-90%重量的镍;0.5-5微英寸厚的钯层以及0-1微英寸厚的金层。
2.如权利要求1所述的IC封装,特征在于:所述钯或金触击电镀层厚度为0.5-3微英寸,所述钯-镍合金层的厚度为0.5-4微英寸,所述钯层厚度为0.5-4微英寸,所述外部金层厚度在0-1微英寸的范围内。
3.如权利要求1所述的IC封装,特征在于:所述钯或软金触击电镀层厚度为1-3微英寸,所述钯-镍合金层厚度为2-4微英寸,所述钯层厚度为1-4微英寸。
4.如权利要求1所述的IC封装,特征在于:所述钯或软金触击电镀层厚度为0.5-2微英寸,所述钯-镍合金层厚度为0.5-2微英寸,所述钯层厚度为0.5-2微英寸,所述外部金层厚度约为1微英寸。
5.如权利要求1所述的IC封装,特征在于:所述基底金属包括有铜,所述Pd-Ni合金含有20%重量的镍。
6.如权利要求1所述的IC封装。特征在于:所述外部金层由软金触击电镀层构成。
7.如权利要求1所述的IC封装,特征在于:所述金属层是使用双卷盘淀积工艺淀积而成的金属层。
8.一种为集成电路单元提供电接触的引线框架,它包括几个与集成电路电连接的引线,每条引线包括一个基底金属,一个基底金属上的镍层和一个淀积于镍层上的若干金属层的组合物,其中:所述组合层厚度为2.5-11微英寸,从镍层开始依次包括有:0.5-3.5微英寸厚的钯或软金的触击电镀层;0.5-5微英寸厚的钯-镍合金层,其中含有10-90%重量的镍;0.5-5微英寸厚的钯层和0-1微英寸厚的金属。
9.如权利要求8所述的引线框架,特征在于:所述钯的触击电镀层的厚度为0.5-3微英寸,所述钯-镍合金层的厚度为0.5-4微英寸,所述钯层的厚度为0.5-4微英寸,所述外部金层的厚度在0-1微英寸的范围内。
10.如权利要求8所述的引线框架,特征在于:所述钯或软金触击电镀层厚度为1-3微英寸,所述钯-镍合金层厚度为2-4微英寸,所述钯层厚度为1-4微英寸。
11.如权利要求8所述的引线框架,特征在于:所述钯或软金触击电镀层厚度为0.5-2微英寸,所述钯-镍合金层厚度为0.5-2微英寸,所述钯层厚度为0.5-2微英寸,所述外部金层厚度约为1微英寸。
12.如权利要求8所述的引线框架,特征在于:所述基底金属由铜构成,所述Pd-Ni合金含有20%重量的镍。
13.如权利要求8所述的引线框架,特征在于:所述外部金层由软金的触击电镀层构成。
14.如权利要求8所述的引线框架,特征在于:所述各层是由双卷盘淀积工艺淀积而成。
15.一种制品,它包括一种基底金属,一种位于基底金属上的镍层和一种位于镍层上的若干层的组合物,所述组合层厚度为2.5-11微英寸,从镍层开始依次包括:0.5-3.5微英寸厚的钯或软金的触击电镀层;0.5-5微英寸厚的钯-镍合金层,含有10-90%重量的镍;0.5-5微英寸厚的钯层和0-1微英寸厚的金层。
16.如权利要求15所述的制品,特征在于:所述钯或软金的触击电镀层厚度为0.5-3微英寸,所述钯-镍合金层厚度为0.5-4微英寸,所述钯层厚度为0.5-4微英寸,所述外部金层厚度在0-1微英寸的范围内。
17.如权利要求15所述的制品,特征在于:所述钯或软金的触击电镀层厚度为1-3微英寸,所述钯-镍合金层厚度为2-4微英寸,所述钯层厚度为1-4微英寸。
18.如权利要求15所述的制品,特征在于:所述钯或软金的触击电镀层厚度为0.5-2微英寸,所述钯-镍合金层厚度为0.5-2微英寸,所述钯层厚度为0.5-2微英寸,所述外部金层厚度约为1微英寸。
19.如权利要求15所述的制品,特征在于所述基底金属包括有铜,所述Pd-Ni合金包含20%重量的镍。
20.如权利要求15所述的制品,特征在于:所述外部金的触击电镀层由软金的触击电镀层构成。
21.如权利要求15所述的制品,特征在于:所述金层是用双卷盘淀积工艺淀积而成。
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US494,476 | 1995-06-26 | ||
US08/494,476 US5675177A (en) | 1995-06-26 | 1995-06-26 | Ultra-thin noble metal coatings for electronic packaging |
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CN1146075A true CN1146075A (zh) | 1997-03-26 |
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US (1) | US5675177A (zh) |
EP (1) | EP0751564A3 (zh) |
JP (1) | JP3062086B2 (zh) |
CN (1) | CN1146075A (zh) |
MY (1) | MY132281A (zh) |
SG (1) | SG44960A1 (zh) |
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- 1996-06-24 JP JP8163271A patent/JP3062086B2/ja not_active Expired - Fee Related
- 1996-06-25 CN CN96108768A patent/CN1146075A/zh active Pending
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CN100426590C (zh) * | 2004-04-28 | 2008-10-15 | 信荣高科技股份有限公司 | 连接器用连接端子及其表面处理方法 |
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JPH0917932A (ja) | 1997-01-17 |
US5675177A (en) | 1997-10-07 |
MY132281A (en) | 2007-09-28 |
EP0751564A3 (en) | 1998-08-12 |
SG44960A1 (en) | 1997-12-19 |
EP0751564A2 (en) | 1997-01-02 |
JP3062086B2 (ja) | 2000-07-10 |
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