CN114556563B - 半导体集成电路装置 - Google Patents
半导体集成电路装置 Download PDFInfo
- Publication number
- CN114556563B CN114556563B CN202080072108.5A CN202080072108A CN114556563B CN 114556563 B CN114556563 B CN 114556563B CN 202080072108 A CN202080072108 A CN 202080072108A CN 114556563 B CN114556563 B CN 114556563B
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- gate wiring
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- dummy gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
- H10D30/43—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
- H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/117—Shapes of semiconductor bodies
- H10D62/118—Nanostructure semiconductor bodies
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/117—Shapes of semiconductor bodies
- H10D62/118—Nanostructure semiconductor bodies
- H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
- H10D62/121—Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
- H10D84/903—Masterslice integrated circuits comprising field effect technology
- H10D84/907—CMOS gate arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/10—Integrated device layouts
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0172—Manufacturing their gate conductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
- H10D84/903—Masterslice integrated circuits comprising field effect technology
- H10D84/907—CMOS gate arrays
- H10D84/909—Microarchitecture
- H10D84/935—Degree of specialisation for implementing specific functions
- H10D84/937—Implementation of digital circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
- H10D84/903—Masterslice integrated circuits comprising field effect technology
- H10D84/907—CMOS gate arrays
- H10D84/968—Macro-architecture
- H10D84/974—Layout specifications, i.e. inner core regions
- H10D84/975—Wiring regions or routing
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019191448 | 2019-10-18 | ||
| JP2019-191448 | 2019-10-18 | ||
| PCT/JP2020/038662 WO2021075434A1 (ja) | 2019-10-18 | 2020-10-13 | 半導体集積回路装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114556563A CN114556563A (zh) | 2022-05-27 |
| CN114556563B true CN114556563B (zh) | 2025-04-22 |
Family
ID=75538496
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202080072108.5A Active CN114556563B (zh) | 2019-10-18 | 2020-10-13 | 半导体集成电路装置 |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US12356714B2 (https=) |
| JP (1) | JP7610128B2 (https=) |
| CN (1) | CN114556563B (https=) |
| WO (1) | WO2021075434A1 (https=) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7640861B2 (ja) * | 2019-10-18 | 2025-03-06 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| US12363977B2 (en) | 2021-08-31 | 2025-07-15 | International Business Machines Corporation | Forming dielectric sidewall and bottom dielectric isolation in Fork-FET devices |
| US20230114214A1 (en) * | 2021-09-24 | 2023-04-13 | Intel Corporation | Single-sided nanosheet transistors |
| WO2023248772A1 (ja) * | 2022-06-20 | 2023-12-28 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| WO2024116853A1 (ja) * | 2022-11-29 | 2024-06-06 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| WO2025115361A1 (ja) * | 2023-11-30 | 2025-06-05 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| WO2025126580A1 (ja) * | 2023-12-14 | 2025-06-19 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| WO2025126581A1 (ja) * | 2023-12-14 | 2025-06-19 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| WO2025126579A1 (ja) * | 2023-12-14 | 2025-06-19 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| WO2025169526A1 (ja) * | 2024-02-06 | 2025-08-14 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| WO2025177613A1 (ja) * | 2024-02-21 | 2025-08-28 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| WO2025177614A1 (ja) * | 2024-02-21 | 2025-08-28 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| WO2025211200A1 (ja) * | 2024-04-01 | 2025-10-09 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| WO2025211201A1 (ja) * | 2024-04-01 | 2025-10-09 | 株式会社ソシオネクスト | 半導体集積回路装置 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109643688A (zh) * | 2016-08-01 | 2019-04-16 | 株式会社索思未来 | 半导体集成电路装置 |
| CN109860178A (zh) * | 2017-11-30 | 2019-06-07 | 英特尔公司 | 用于先进的集成电路结构制造的栅极线插塞结构 |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2576253B2 (ja) * | 1990-02-09 | 1997-01-29 | 日本電気株式会社 | D/a変換装置 |
| JPH0567634A (ja) * | 1991-09-06 | 1993-03-19 | Oki Electric Ind Co Ltd | Mis型半導体装置の製造方法 |
| JP2009016525A (ja) * | 2007-07-04 | 2009-01-22 | Renesas Technology Corp | 半導体装置 |
| CN106663594B (zh) * | 2014-06-23 | 2020-08-25 | 美商新思科技有限公司 | 具有含不同数量的纳米线或2d材料带的晶体管的存储单元和逻辑单元 |
| US9711414B2 (en) * | 2014-10-21 | 2017-07-18 | Samsung Electronics Co., Ltd. | Strained stacked nanosheet FETS and/or quantum well stacked nanosheet |
| KR102413610B1 (ko) * | 2016-03-02 | 2022-06-24 | 삼성전자주식회사 | 레이아웃 디자인 시스템, 이를 이용한 반도체 장치 및 그 제조 방법 |
| CN109314080B (zh) | 2016-07-01 | 2022-09-30 | 株式会社索思未来 | 半导体集成电路装置 |
| WO2018030107A1 (ja) * | 2016-08-08 | 2018-02-15 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| CN109863588B (zh) | 2016-10-17 | 2022-09-30 | 株式会社索思未来 | 半导体集成电路装置 |
| US10977417B2 (en) * | 2018-09-28 | 2021-04-13 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure, device, and method |
-
2020
- 2020-10-13 JP JP2021552400A patent/JP7610128B2/ja active Active
- 2020-10-13 WO PCT/JP2020/038662 patent/WO2021075434A1/ja not_active Ceased
- 2020-10-13 CN CN202080072108.5A patent/CN114556563B/zh active Active
-
2022
- 2022-04-14 US US17/720,802 patent/US12356714B2/en active Active
-
2025
- 2025-06-11 US US19/235,178 patent/US20250311421A1/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109643688A (zh) * | 2016-08-01 | 2019-04-16 | 株式会社索思未来 | 半导体集成电路装置 |
| CN109860178A (zh) * | 2017-11-30 | 2019-06-07 | 英特尔公司 | 用于先进的集成电路结构制造的栅极线插塞结构 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20250311421A1 (en) | 2025-10-02 |
| JP7610128B2 (ja) | 2025-01-08 |
| CN114556563A (zh) | 2022-05-27 |
| WO2021075434A1 (ja) | 2021-04-22 |
| US20220246644A1 (en) | 2022-08-04 |
| US12356714B2 (en) | 2025-07-08 |
| JPWO2021075434A1 (https=) | 2021-04-22 |
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| GR01 | Patent grant |