CN114551415A - 半导体封装 - Google Patents

半导体封装 Download PDF

Info

Publication number
CN114551415A
CN114551415A CN202111411622.XA CN202111411622A CN114551415A CN 114551415 A CN114551415 A CN 114551415A CN 202111411622 A CN202111411622 A CN 202111411622A CN 114551415 A CN114551415 A CN 114551415A
Authority
CN
China
Prior art keywords
interposer
package substrate
top surface
semiconductor chip
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111411622.XA
Other languages
English (en)
Inventor
郭旻根
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN114551415A publication Critical patent/CN114551415A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/117—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

可以提供一种半导体封装，该半导体封装包括第一封装基板、在第一封装基板的顶表面上的第一半导体芯片、在第一半导体芯片的顶表面上的电连接到第一封装基板的内插器、以及配置为覆盖第一封装基板和第一半导体芯片的模制层。内插器可以包括：内插器沟槽，从内插器的底表面凹陷，内插器的底表面面对第一半导体芯片的顶表面和第一封装基板的顶表面两者；以及穿透内插器的内插器孔。模制层可以包括填充在第一封装基板和内插器之间的区域的填充部分、填充内插器孔的贯穿部分、以及覆盖内插器的顶表面的至少一部分的覆盖部分。

Description

半导体封装
技术领域
本公开涉及半导体封装以及用于制造该半导体封装的方法。更具体地，本公开涉及层叠封装(POP)半导体封装和/或用于制造该POP半导体封装的方法。
背景技术
随着电子产业的发展，对电子部件的高功能性、高速度和小型化的需求日益增加。根据这一趋势，可以使用在一个封装基板上堆叠和安装多个半导体芯片或者在封装上堆叠封装的方法。例如，可以使用封装内封装(PIP)半导体封装或层叠封装(POP)半导体封装。
POP半导体封装可以包括用于在上封装和下封装之间的电连接的内插器(interposer)。内插器可以促进在上封装和下封装之间的电连接，并防止上封装和下封装的翘曲。
发明内容
本公开的一些方面提供具有提高的产品可靠性的半导体封装。
本公开的一些方面还提供用于制造具有提高的产品可靠性的半导体封装的方法。
根据本公开的一些方面，一种半导体封装可以包括第一封装基板、在第一封装基板的顶表面上的第一半导体芯片、在第一半导体芯片的顶表面上的电连接到第一封装基板的内插器以及配置为覆盖第一封装基板和第一半导体芯片的模制层。内插器可以包括从内插器的底表面凹陷的内插器沟槽以及穿透内插器的内插器孔，内插器的底表面面对第一半导体芯片的顶表面和第一封装基板的顶表面两者。模制层可以包括填充在第一封装基板和内插器之间的区域的填充部分、填充内插器孔的贯穿部分、以及覆盖内插器的顶表面的至少一部分的覆盖部分。
根据本公开的一些方面，一种半导体封装可以包括封装基板、在封装基板的顶表面上的半导体芯片、以及在半导体芯片的顶表面上的内插器，该内插器与半导体芯片间隔开并电连接到封装基板。内插器可以包括：内插器沟槽，从内插器的底表面凹陷并配置为在平面图中与半导体芯片至少部分地重叠，内插器的底表面面对半导体芯片的顶表面和封装基板的顶表面两者；以及从内插器沟槽延伸以穿透内插器的内插器孔，该内插器孔具有比内插器沟槽的宽度小的宽度。
根据本公开的一些方面，一种半导体封装可以包括：第一封装基板；在第一封装基板的顶表面上的第一半导体芯片；在第一半导体芯片的顶表面上的第二封装基板；在第二封装基板的顶表面上的第二半导体芯片；与第一半导体芯片间隔开并在第一半导体芯片和第二封装基板之间的内插器；在第一封装基板和内插器之间的第一连接构件，该第一连接构件将第一封装基板电连接到内插器；在第一封装基板的顶表面上的模制层，该模制层覆盖第一封装基板和第一半导体芯片；以及在内插器和第二封装基板之间的第二连接构件，该第二连接构件将内插器电连接到第二封装基板。内插器可以包括：从内插器的底表面凹陷的内插器沟槽，该内插器的底表面面对第一半导体芯片的顶表面和第一封装基板的顶表面两者；以及穿透内插器的内插器孔，该模制层可以填充内插器沟槽和内插器孔。
根据本公开的一些方面，一种用于制造半导体封装的方法可以包括：提供第一封装基板；将第一半导体芯片安装在第一封装基板的顶表面上；将内插器设置在第一半导体芯片的顶表面上，该内插器电连接到第一封装基板，该内插器包括从内插器的底表面凹陷的内插器沟槽和穿透内插器的内插器孔，内插器的该底表面面对第一半导体芯片的顶表面和第一封装基板的顶表面两者；以及在第一封装基板和内插器之间注入模制材料以形成覆盖第一封装基板和第一半导体芯片的模制层。
然而，本公开的方面不限于这里阐述的那些。通过参照下面给出的本公开的详细描述，本公开的以上和其它的方面对于本公开所属的领域内的普通技术人员将变得更加明显。
附图说明
通过参照附图详细描述本公开的一些示例实施方式，本公开的以上和其它的方面和特征将变得更加明显，附图中：
图1是示出根据一些示例实施方式的半导体封装的示例布局图。
图2是沿着图1的线A-A截取的示意性剖视图。
图3是示出图2的区域R的放大图。
图4是用于说明根据一些示例实施方式的半导体器件的效果的示意性剖视图。
图5至图8是示出根据一些示例实施方式的半导体封装的各种示意性剖视图。
图9是示出根据一些示例实施方式的半导体封装的示例布局图。
图10是沿着图9的线B-B截取的示意性剖视图。
图11和图12是示出根据一些示例实施方式的半导体封装的各种示例布局图。
图13至图17是示出根据一些示例实施方式的用于制造半导体封装的方法的中间步骤的视图。
图18和图19是示出根据一些示例实施方式的用于制造半导体封装的方法的中间步骤的视图。
具体实施方式
当术语“约”或“基本上”在本说明书中结合数值使用时，所意欲的是相关数值包括所述数值周围的制造或操作公差(例如±10％)。此外，当词语“大体上”和“基本上”与几何形状结合使用时，所意欲的是不要求几何形状的精度，但是该形状的活动余地(latitude)在本公开的范围内。此外，不管数值或形状是否被修饰为“约”或“基本上”，将理解，这些值和形状应当被解释为包括所述数值或形状周围的制造或操作公差(例如±10％)。
在下文，将参照图1至图12描述根据一些示例实施方式的半导体封装。
图1是示出根据一些示例实施方式的半导体封装的示例布局图。图2是沿着图1的线A-A截取的示意性剖视图。图3是示出图2的区域R的放大图。图4是用于说明根据一些示例实施方式的半导体器件的效果的示意性剖视图。
参照图1至图4，根据一些示例实施方式的半导体封装包括第一封装基板100、第一半导体芯片110、内插器200、第一模制层170、第二封装基板300、第二半导体芯片310和第二模制层270。
第一封装基板100可以是用于封装的基板。例如，第一封装基板100可以是印刷电路板(PCB)、陶瓷基板等。在一些示例实施方式中，第一封装基板100也可以是以晶片级制造的晶片级封装(WLP)基板。第一封装基板100可以配置为单层或多层。第一封装基板100可以包括彼此相对的底表面和顶表面。
第一封装基板100可以包括第一下焊盘102、第一上焊盘104和第一芯片焊盘106。第一下焊盘102可以从第一封装基板100的底表面暴露。第一上焊盘104和第一芯片焊盘106中的每个可以从第一封装基板100的顶表面暴露。第一下焊盘102、第一上焊盘104和第一芯片焊盘106中的每个可以连接到形成在第一封装基板100中的电路(例如布线图案)。也就是，第一下焊盘102、第一上焊盘104和第一芯片焊盘106中的每个可以是第一封装基板100的布线图案等通过其连接到外部的部分(例如图案或焊盘)。
在一些示例实施方式中，第一连接构件190可以形成在第一封装基板100的底表面上。第一连接构件190可以将第一封装基板100电连接到外部装置。例如，第一连接构件190可以接触第一封装基板100的第一下焊盘102。因此，第一连接构件190可以向第一封装基板100提供外部装置的电信号，或者可以向外部装置提供第一封装基板100的电信号。
第一连接构件190可以是例如球形、半球形或椭圆球形凸块，但是不限于此。第一连接构件190可以包括例如锡(Sn)、铟(In)、铋(Bi)、锑(Sb)、铜(Cu)、银(Ag)、锌(Zn)、铅(Pb)或其组合，但是本公开不限于此。
在一些示例实施方式中，电路元件140可以设置在第一封装基板100上。电路元件140被示出为设置在第一封装基板100的底表面上，但是这仅是一示例。电路元件140可以包括各种有源元件(诸如晶体管)或者各种无源元件(诸如电容器、电阻器和/或电感器)。作为一个示例，电路元件140可以是电容器。
第一半导体芯片110可以安装在第一封装基板100之上。作为一个示例，第一半导体芯片110可以安装在第一封装基板100的顶表面之上。第一半导体芯片110可以是具有集成在其中的数百至数百万个半导体元件的集成电路(IC)芯片。例如，第一半导体芯片110可以是存储器芯片(诸如易失性存储器(例如DRAM)或非易失性存储器(例如ROM或闪存))、应用处理器(AP)芯片(诸如中央处理单元(CPU)、图形处理单元(GPU)、现场可编程门阵列(FPGA)、数字信号处理器、加密处理器、微处理器或微控制器)、或者逻辑芯片(诸如模数转换器(ADC)或专用IC(ASIC))，但是不限于此。此外，第一半导体芯片110可以用它们的组合来配置。
在图1和图2中，示出仅一个第一半导体芯片110安装在第一封装基板100之上，但是这仅是一示例。与示出的示例不同，多个第一半导体芯片110可以并排安装在第一封装基板100之上，或者多个第一半导体芯片110可以依次堆叠在第一封装基板100之上。
在一些示例实施方式中，第一芯片凸块120可以形成在第一封装基板100和第一半导体芯片110之间。第一芯片凸块120可以将第一封装基板100电连接到第一半导体芯片110。例如，第一半导体芯片110可以通过倒装芯片接合方法安装在第一封装基板100之上。作为一个示例，第一芯片凸块120可以包括第一柱层122和第一焊料层124。
第一柱层122可以具有从第一半导体芯片110的底表面突出的柱状结构。此外，第一柱层122可以电连接到第一半导体芯片110。第一柱层122可以包括例如铜(Cu)、铜合金、镍(Ni)、镍合金、钯(Pd)、铂(Pt)、金(Au)、钴(Co)或其组合，但是本公开不限于此。
第一焊料层124可以将第一柱层122电连接到第一封装基板100。例如，第一焊料层124可以接触第一封装基板100的第一芯片焊盘106。第一焊料层124可以是例如球形、半球形或椭圆球形结构。第一焊料层124可以包括例如锡(Sn)、铟(In)、铋(Bi)、锑(Sb)、铜(Cu)、银(Ag)、锌(Zn)、铅(Pb)或其组合，但是本公开不限于此。
在一些示例实施方式中，底部填充物130可以形成在第一封装基板100和第一半导体芯片110之间。底部填充物130可以填充在第一封装基板100和第一半导体芯片110之间的区域。此外，底部填充物130可以覆盖第一芯片凸块120。第一芯片凸块120可以穿透底部填充物130以将第一封装基板100电连接到第一半导体芯片110。
底部填充物130可以通过将第一半导体芯片110固定到第一封装基板100来减轻或防止第一半导体芯片110的破裂。底部填充物130例如可以包括绝缘聚合物材料，诸如环氧模塑料(EMC)，但是不限于此。
在一些示例实施方式中，底部填充物130可以包括不同于随后将描述的第一模制层170的材料。例如，底部填充物130可以包括具有比第一模制层170更好的流动性的绝缘材料。因此，底部填充物130可以有效地填充在第一封装基板100和第一半导体芯片110之间的狭窄空间。
内插器200可以设置在第一封装基板100的顶表面和第一半导体芯片110的顶表面之上。此外，内插器200可以插置在第一封装基板100和随后将描述的第二封装基板300之间。内插器200可以促进第一封装基板100和第二封装基板300之间的电连接。此外，内插器200可以减轻或防止第一封装基板100和第二封装基板300的翘曲。
内插器200可以包括彼此相对的底表面和顶表面。例如，内插器200的底表面可以面对第一封装基板100的顶表面，内插器200的顶表面可以面对第二封装基板300的底表面。
内插器200可以包括第二下焊盘202和第二上焊盘204。第二下焊盘202可以从内插器200的底表面暴露。第二上焊盘204可以从内插器200的顶表面暴露。第二下焊盘202和第二上焊盘204中的每个可以连接到形成在内插器200中的电路(例如布线图案)。也就是，第二下焊盘202和第二上焊盘204中的每个可以是内插器200的布线图案等通过其连接到外部的部分(例如图案或焊盘)。
在一些示例实施方式中，内插器200还可以包括贯穿通路208。贯穿通路208可以穿透内插器200。例如，贯穿通路208可以在与内插器200的顶表面相交的第一方向Z上延伸以穿透内插器200。穿透内插器200的贯穿通路208可以将第二下焊盘202电连接到第二上焊盘204。
内插器200可以电连接到第一封装基板100。例如，第二连接构件290可以形成在第一封装基板100和内插器200之间。第二连接构件290可以将第一封装基板100电连接到内插器200。例如，第二连接构件290可以接触第一封装基板100的第一上焊盘104和内插器200的第二下焊盘202。
第二连接构件290可以是例如球形、半球形或椭圆球形凸块，但是不限于此。第二连接构件290可以包括例如锡(Sn)、铟(In)、铋(Bi)、锑(Sb)、铜(Cu)、银(Ag)、锌(Zn)、铅(Pb)或其组合，但是本公开不限于此。
在一些示例实施方式中，第二连接构件290可以设置到第一半导体芯片110的侧部。例如，如图1所示，多个第二连接构件290可以设置为在平面图中围绕第一半导体芯片110。
内插器200可以与第一封装基板100间隔开。例如，在第一封装基板100和内插器200之间的分离距离D1可以为约100μm至约200μm。例如，在第一封装基板100和内插器200之间的分隔距离D1可以为约130μm至约190μm。
在一些示例实施方式中，内插器200可以与第一半导体芯片110间隔开。例如，如图2所示，相对于第一封装基板100的顶表面，第二连接构件290的顶表面可以定位得高于第一半导体芯片110的顶表面。例如，在第一半导体芯片110和内插器200之间的分隔距离D2可以为约5μm至约100μm。例如，在第一半导体芯片110和内插器200之间的分隔距离D2可以为约10μm至约50μm。
内插器200可以包括内插器沟槽200T和内插器孔200H。
内插器沟槽200T可以通过从内插器200的底表面凹陷而形成，内插器200的该底表面面对第一半导体芯片110的顶表面和第一封装基板100的顶表面两者。例如，内插器沟槽200T可以在第一方向Z上从内插器200的底表面凹陷。
在一些示例实施方式中，内插器沟槽200T的深度可以小于内插器200的厚度。这里，深度或厚度表示在与内插器200的底表面相交的方向(例如第一方向Z)上的深度或厚度。例如，如图3所示，内插器200在第一方向Z上的厚度D3可以大于内插器沟槽200T在第一方向Z上的深度D4。因此，内插器沟槽200T可以不从内插器200的顶表面暴露。
内插器200的厚度D3可以为例如约50μm至约200μm。例如，内插器200的厚度D3可以为约70μm至约120μm。
内插器沟槽200T的深度D4可以为例如约10μm至约100μm。当内插器沟槽200T的深度D4小于约10μm时，在注射模制材料以形成随后将描述的第一模制层170的工艺期间，模制材料的流动性可能降低。当内插器沟槽200T的深度D4大于约100μm时，内插器200的强度可能降低，因此翘曲可能严重并且操纵可能是困难的。因此，例如，内插器沟槽200T的深度D4可以为约30μm至约50μm。
在一些示例实施方式中，内插器沟槽200T可以沿着平行于内插器200的底表面的第二方向Y伸长。例如，如图1所示，内插器沟槽200T可以包括在第二方向Y上延伸的长边以及在平行于内插器200的底表面并与第二方向Y相交的第三方向X上延伸的短边。
在一些示例实施方式中，内插器200可以包括彼此间隔开的多个内插器沟槽200T。所述多个内插器沟槽200T可以例如沿着第三方向X排列。
内插器孔200H可以形成为穿透内插器200。例如，内插器孔200H可以在第一方向Z上延伸以穿透内插器200。内插器孔200H可以从内插器200的顶表面暴露。
在一些示例实施方式中，内插器200可以包括彼此间隔开的多个内插器孔200H。所述多个内插器孔200H可以在包括例如第二方向Y和第三方向X的平面上二维地布置。在图1中，九个内插器孔200H以网格形式布置，但是这仅是一示例，内插器孔200H的布置或数量可以变化。此外，每个内插器孔200H被示出为具有圆柱形状，但是这仅是一示例，每个内插器孔200H可以具有各种其它形状，诸如多边形柱等。
内插器沟槽200T的至少一部分和内插器孔200H的至少一部分可以每个与第一半导体芯片110重叠。在本公开中，重叠表示在平面图中重叠。例如，内插器沟槽200T的一部分和内插器孔200H可以每个在第一方向Z上与第一半导体芯片110重叠。
在一些示例实施方式中，内插器沟槽200T的至少一部分可以与第一半导体芯片110的边缘重叠。例如，内插器沟槽200T的一部分可以与第一半导体芯片110的在第二方向Y上延伸的边缘重叠。此外，内插器沟槽200T的另一部分可以与第一半导体芯片110的在第三方向X上延伸的边缘的一部分重叠。
在一些示例实施方式中，所述多个内插器孔200H中的至少一些可以与内插器沟槽200T重叠。例如，如图2所示，内插器孔200H可以从内插器沟槽200T延伸以穿透内插器200。
在一些示例实施方式中，内插器孔200H的宽度可以小于内插器沟槽200T的宽度。这里，宽度表示在平行于内插器200的底表面的方向(例如，第三方向X)上的宽度。例如，如图3所示，内插器沟槽200T可以在第三方向X上具有第一宽度W1，并且内插器孔200H可以在第三方向X上具有第二宽度W2。在这种情况下，内插器孔200H的第二宽度W2可以小于内插器沟槽200T的第一宽度W1。
内插器沟槽200T的第一宽度W1可以在与内插器沟槽200T的延伸方向交叉的方向上为例如约100μm至约300μm。当内插器沟槽200T的第一宽度W1小于约100μm时，在注射模制材料以形成将随后描述的第一模制层170的工艺期间，模制材料的流动性可能降低。当内插器沟槽200T的第一宽度W1大于约300μm时，内插器200的强度降低，因此翘曲可能严重，并且操纵可能是困难的。因此，例如，内插器沟槽200T的第一宽度W1可以为约150μm至约250μm。
内插器孔200H的第二宽度W2可以为例如约50μm至约150μm。当内插器孔200H的第二宽度W2小于约50μm时，可能出现在第一模制层170中的空隙可能不容易排出。当内插器孔200H的第二宽度W2大于约150μm时，内插器200的强度降低，因此翘曲可能严重并且操纵可能是困难的。因此，例如，内插器孔200H的第二宽度W2可以为约70μm至约130μm。
第一模制层170可以设置在第一封装基板100的顶表面上。第一模制层170可以覆盖第一封装基板100、第一半导体芯片110和第二连接构件290。第一模制层170可以填充在第一封装基板100和内插器200之间的区域。例如，第二连接构件290可以穿透第一模制层170以将第一封装基板100电连接到内插器200。第一模制层170可以包括例如绝缘聚合物材料，诸如环氧模塑料(EMC)，但是不限于此。
在一些示例实施方式中，第一模制层170可以包括填充部分172、贯穿部分174和覆盖部分176。填充部分172、贯穿部分174和覆盖部分176可以一体地形成。
填充部分172可以覆盖第一封装基板100、第一半导体芯片110和第二连接构件290。例如，填充部分172可以覆盖第一封装基板100的顶表面、第一半导体芯片110的顶表面和侧表面以及第二连接构件290的侧表面。填充部分172可以填充在第一封装基板100和内插器200之间的区域。由于内插器200可以与第一半导体芯片110间隔开，所以填充部分172可以填充在第一半导体芯片110和内插器200之间的区域。此外，填充部分172可以填充内插器沟槽200T。
贯穿部分174可以从填充部分172延伸。贯穿部分174可以填充内插器孔200H。也就是，贯穿部分174可以是第一模制层170的穿透内插器200的部分。在一些示例实施方式中，由于内插器200可以包括彼此间隔开的多个内插器孔200H，所以第一模制层170可以包括彼此间隔开的多个贯穿部分174。
覆盖部分176可以从贯穿部分174延伸。例如，贯穿部分174可以将填充部分172连接到覆盖部分176。覆盖部分176可以覆盖内插器200的顶表面的至少一部分。也就是，覆盖部分176可以是第一模制层170的设置在内插器200的顶表面上的部分。在一些示例实施方式中，在平面图中，覆盖部分176的至少一部分可以与第一半导体芯片110重叠。
在一些示例实施方式中，覆盖部分176可以将彼此间隔开的所述多个贯穿部分174彼此连接。例如，如所示的，覆盖部分176可以形成为与第一方向Z交叉的板形状以连接彼此间隔开的所述多个贯穿部分174。形成为板形状的覆盖部分176可以牢固地支撑内插器200以提高强度。此外，形成为板形状的覆盖部分176可以提供用于产品标记的空间以提高产品识别性。
第二封装基板300可以设置在内插器200的顶表面之上。第二封装基板300可以是用于封装的基板。例如，第二封装基板300可以是印刷电路板(PCB)、陶瓷基板等。在一些示例实施方式中，第二封装基板300也可以是以晶片级制造的晶片级封装(WLP)基板。第二封装基板300可以配置为单层或多层。第二封装基板300可以包括彼此相对的底表面和顶表面。例如，第二封装基板300的底表面可以面对内插器200的顶表面。
第二封装基板300可以包括第三下焊盘302和第二芯片焊盘306。第三下焊盘302可以从第二封装基板300的底表面暴露。第二芯片焊盘306可以从第二封装基板300的顶表面暴露。第三下焊盘302和第二芯片焊盘306中的每个可以连接到形成在第二封装基板300中的电路(例如布线图案)。也就是，第三下焊盘302和第二芯片焊盘306中的每个可以是第二封装基板300的布线图案等通过其连接到外部的部分(图案或焊盘)。
第二封装基板300可以电连接到内插器200。例如，第三连接构件390可以形成在内插器200和第二封装基板300之间。第三连接构件390可以将内插器200电连接到第二封装基板300。例如，第三连接构件390可以接触内插器200的第二上焊盘204和第二封装基板300的第三下焊盘302。
第三连接构件390可以是例如球形、半球形或椭圆球形凸块，但是不限于此。第三连接构件390可以包括例如锡(Sn)、铟(In)、铋(Bi)、锑(Sb)、铜(Cu)、银(Ag)、锌(Zn)、铅(Pb)或其组合，但是本公开不限于此。
在一些示例实施方式中，第二封装基板300可以与内插器200间隔开。例如，如图2所示，相对于内插器200的顶表面，第三连接构件390的顶表面可以定位得高于第一模制层170的覆盖部分176的顶表面。
第二半导体芯片310可以安装在第二封装基板300之上。例如，第二半导体芯片310可以安装在第二封装基板300的顶表面之上，第二封装基板300的该顶表面背对内插器200的顶表面。第二半导体芯片310可以是具有集成在其中的数百至数百万个半导体元件的集成电路(IC)。例如，第二半导体芯片310可以是存储器芯片(诸如易失性存储器(例如DRAM)或非易失性存储器(例如ROM或闪存))、应用处理器(AP)芯片(诸如中央处理单元(CPU)、现场可编程门阵列(FPGA)、数字信号处理器、加密处理器、微处理器或微控制器)或者逻辑芯片(诸如模数转换器(ADC)或专用IC(ASIC))，但是不限于此。此外，第二半导体芯片310可以用它们的组合来配置。
在一些示例实施方式中，第一半导体芯片110可以是应用处理器芯片，第二半导体芯片310可以是存储器芯片。
在图1和图2中，示出仅一个第二半导体芯片310安装在第二封装基板300之上，但是这仅是一示例。与示出的示例不同，多个第二半导体芯片310可以并排安装在第二封装基板300之上，或者多个第二半导体芯片310可以依次堆叠在第二封装基板300之上。
在一些示例实施方式中，第二芯片凸块320可以形成在第二封装基板300和第二半导体芯片310之间。第二芯片凸块320可以将第二封装基板300电连接到第二半导体芯片310。例如，第二半导体芯片310可以通过倒装芯片接合方法安装在第二封装基板300之上。作为一个示例，第二芯片凸块320可以包括第二柱层322和第二焊料层324。由于第二柱层322可以类似于第一柱层122并且第二焊料层324可以类似于第一焊料层124，所以下面将省略其详细描述。
第二模制层270可以设置在第二封装基板300的顶表面上。第二模制层270可以覆盖第二封装基板300和第二半导体芯片310。例如，第二模制层270可以覆盖第二封装基板300的顶表面以及第二半导体芯片310的顶表面和侧表面。第二模制层270可以包括例如绝缘聚合物材料，诸如EMC，但是不限于此。第二模制层270可以包括与第一模制层170相同的材料，或者可以包括与第一模制层170不同的材料。
随着电子器件越来越高度集成，需要小型化的半导体封装。然而，半导体封装的小型化导致其制造工艺中的各种问题。例如，在包括内插器的POP封装中，随着在内插器和下半导体芯片(例如第一半导体芯片110)之间的空间变得更窄，模制材料可能没有被有效地注入。这导致在由模制材料形成的模制层中出现空隙，从而降低产品可靠性。作为一个示例，在模制层中形成的空隙可能在高温工艺中扩大或移动，从而在连接构件(例如第二连接构件290)等中引起裂纹。
然而，根据一些示例实施方式的半导体封装可以通过包括内插器沟槽200T来抑制空隙出现在第一模制层170中。如上所述，内插器沟槽200T可以从内插器200的底表面凹陷，因此可以在第一半导体芯片110和内插器200之间确保额外的空间。这可以在形成第一模制层170的工艺中改善注射在第一封装基板100和内插器200之间以及在第一半导体芯片110和内插器200之间的模制材料的流动性。因此，可以抑制空隙出现在第一模制层170中，从而提供具有提高的产品可靠性的半导体封装。
此外，根据一些示例实施方式的半导体封装可以通过包括内插器孔200H而容易地排出可能出现在第一模制层170中的空隙。例如，如图4所示，空隙V可能出现在第一模制层170中。然而，由于第一模制层170可以具有穿透内插器200的贯穿部分174，所以空隙V可以容易地通过贯穿部分174和/或覆盖部分176排出到外部。因此，可以减轻或防止连接构件(例如第二连接构件290)等的裂纹，从而提供具有提高的产品可靠性的半导体封装。
图5至图8是示出根据一些示例实施方式的半导体封装的各种示意性剖视图。为了描述的简单，参照图1至图4进行的描述的冗余部分可以被概括或省略。
参照图5，在根据一些示例实施方式的半导体封装中，内插器200包括支撑部分210。
支撑部分210可以从内插器200的底表面突出。例如，支撑部分210可以是从内插器200的底表面突出的柱状结构。支撑部分210可以支撑设置在第一半导体芯片110上的内插器200的除了支撑部分210之外的部分。例如，支撑部分210可以接触第一半导体芯片110的顶表面。因此，可以改善内插器200的翘曲。
在一些示例实施方式中，多个支撑部分210可以从内插器200的底表面突出。在图5中，仅示出四个支撑部分210沿着第三方向X以相等的间隔布置，但是这仅是一示例，支撑部分210的布置或数量可以变化。此外，在图5中，仅示出所述多个支撑部分210都与第一半导体芯片110的顶表面接触，但是这仅是一示例。作为另一示例，取决于第二连接构件290的尺寸，所述多个支撑部分210中的至少一些可以与第一半导体芯片110间隔开。
参照图6，在根据一些示例实施方式的半导体封装中，第一封装基板100包括基板沟槽100T。
基板沟槽100T可以通过从第一封装基板100的顶表面凹陷而形成。例如，基板沟槽100T的底表面可以低于第一封装基板100的最上表面。
在一些示例实施方式中，第一半导体芯片110可以安装在基板沟槽100T的底表面之上。例如，第一芯片焊盘106可以从基板沟槽100T的底表面暴露。此外，第一芯片凸块120可以将第一芯片焊盘106电连接到第一半导体芯片110。在这种情况下，如所示的，可以在第一半导体芯片110和内插器200之间确保额外的空间，以改善在第一半导体芯片110和内插器200之间注入的模制材料的流动性。因此，能够提供具有提高的产品可靠性的半导体封装。在一些其它示例实施方式中，与所示的示例不同，在第一半导体芯片110和内插器200之间的分隔距离可以被保持或减小。因此，可以提供进一步小型化的半导体封装。
参照图7，在根据一些示例实施方式的半导体封装中，电路元件140设置在第一封装基板100中。
例如，电路元件140可以设置于在第一下焊盘102和第一上焊盘104之间的区域和/或在第一下焊盘102和第一芯片焊盘106之间的区域中。
参照图8，在根据一些示例实施方式的半导体封装中，第一半导体芯片110通过引线接合方法安装在第一封装基板100之上。
例如，第一附着层112可以形成在第一封装基板100和第一半导体芯片110之间。第一附着层112可以通过使用粘合手段将第一半导体芯片110的底表面附着到第一封装基板100的顶表面。第一附着层112可以包括例如液体环氧树脂、粘合带、导电介质或其组合，但是不限于此。
此外，第一接合引线116可以将第一封装基板100电连接到第一半导体芯片110。例如，第一接合焊盘114可以形成在第一半导体芯片110的顶表面上。第一接合引线116可以将第一接合焊盘114电连接到第一芯片焊盘106。
在一些示例实施方式中，第二半导体芯片310可以通过引线接合方法安装在第二封装基板300之上。例如，第二附着层312可以形成在第二封装基板300和第二半导体芯片310之间。由于第二附着层312可以类似于第一附着层112，所以下面将省略其详细描述。
此外，第二接合引线316可以将第二封装基板300电连接到第二半导体芯片310。例如，第二接合焊盘314可以形成在第二半导体芯片310的顶表面上。第二接合引线316可以将第二接合焊盘314电连接到第二芯片焊盘306。
在一些示例实施方式中，多个半导体芯片可以堆叠在第一封装基板100或第二封装基板300之上。例如，第三半导体芯片410可以堆叠在第二半导体芯片310之上。例如，第三附着层412可以形成在第二半导体芯片310和第三半导体芯片410之间。由于第三附着层412可以类似于第一附着层112或第二附着层312，所以下面将省略其详细描述。
此外，可以形成第三接合引线416以将第二封装基板300电连接到第三半导体芯片410。例如，第三接合焊盘414可以形成在第三半导体芯片410的顶表面上。第三接合引线416可以将第三接合焊盘414电连接到第二芯片焊盘306。
图9是示出根据一些示例实施方式的半导体封装的示例布局图。图10是沿着图9的线B-B截取的示意性剖视图。为了描述的简单，参照图1至图4进行的描述的冗余部分可以被概括或省略。
参照图9和图10，在根据一些示例实施方式的半导体封装中，所述多个内插器孔200H中的至少一些不与内插器沟槽200T重叠。
例如，如所示的，所述多个内插器孔200H中的一些可以设置在内插器沟槽200T内部，并且所述多个内插器孔200H中的一些其它内插器孔可以与内插器沟槽200T间隔开。
与内插器沟槽200T重叠的内插器孔200H可以从内插器沟槽200T延伸以穿透内插器200。不与内插器沟槽200T重叠的内插器孔200H可以从内插器200的底表面延伸到内插器200的顶表面以穿透内插器200。
尽管仅示出五个内插器孔200H沿着第三方向X以相等的间隔布置，但是这仅是一示例，内插器孔200H的布置或数量可以变化。
图11和图12是示出根据一些示例实施方式的半导体封装的各种示例布局图。为了描述的简单，参照图1至图4进行的描述的冗余部分可以被概括或省略。
参照图11，在根据一些示例实施方式的半导体封装中，内插器沟槽200T包括第一子沟槽T1和第二子沟槽T2。
第一子沟槽T1和第二子沟槽T2可以彼此交叉。例如，第一子沟槽T1可以沿着第二方向Y伸长，第二子沟槽T2可以沿着第三方向X伸长。
在一些示例实施方式中，第一子沟槽T1的至少一部分可以与第一半导体芯片110的在第二方向Y上延伸的边缘重叠，第二子沟槽T2的至少一部分可以与第一半导体芯片110的在第三方向X上延伸的边缘重叠。
仅示出与第一子沟槽T1重叠的内插器孔200H，但是这仅是一示例，内插器孔200H中的至少一些可以与第二子沟槽T2重叠。
参照图12，在根据一些示例实施方式的半导体封装中，内插器沟槽200T沿着平行于内插器200的底表面并不同于第二方向Y和第三方向X的第四方向W伸长。
例如，第四方向W可以与第三方向X形成锐角θ。锐角θ可以大于0°且小于90°。锐角θ可以根据模制材料沿其被注入以形成第一模制层170的方向而变化。
在下文，将参照图1至图4和图13至图19描述根据一些示例实施方式的用于制造半导体封装的方法。
图13至图17是示出根据一些示例实施方式的用于制造半导体封装的方法的中间步骤的视图。为了描述的简单，参照图1至图4进行的描述的冗余部分可以被概括或省略。
参照图13，提供第一封装基板100。
第一封装基板100可以是例如印刷电路板(PCB)、陶瓷基板等。第一封装基板100可以包括第一下焊盘102、第一上焊盘104和第一芯片焊盘106。
在一些示例实施方式中，电路元件140可以设置在第一封装基板100上。电路元件140可以是例如电容器。
参照图14，在第一封装基板100之上安装第一半导体芯片110。
例如，可以提供其上形成有第一芯片凸块120的第一半导体芯片110。第一芯片凸块120可以形成在第一半导体芯片110的底表面上。随后，第一芯片凸块120可以连接到第一芯片焊盘106。作为一个示例，第一芯片凸块120可以包括第一柱层122和第一焊料层124。第一焊料层124可以通过焊接等附着到第一芯片焊盘106上。因此，第一封装基板100和第一半导体芯片110可以彼此电连接。
在一些示例实施方式中，第一半导体芯片110可以是应用处理器芯片。
在一些示例实施方式中，可以在第一封装基板100和第一半导体芯片110之间进一步形成底部填充物130。底部填充物130可以填充在第一封装基板100和第一半导体芯片110之间的区域。
参照图15，内插器200设置在第一封装基板100的顶表面和第一半导体芯片110的顶表面之上。
内插器200可以包括第二下焊盘202和第二上焊盘204。在一些示例实施方式中，内插器200还可以包括贯穿通路208。
内插器200可以电连接到第一封装基板100。例如，第二连接构件290可以形成在第一封装基板100和内插器200之间。第二连接构件290可以通过焊接等附接到第一封装基板100的第一上焊盘104和内插器200的第二下焊盘202上。因此，第二连接构件290可以将第一封装基板100电连接到内插器200。
内插器200可以包括内插器沟槽200T和内插器孔200H。内插器沟槽200T可以通过从内插器200的底表面凹陷而形成。例如，内插器沟槽200T可以在第一方向Z上从内插器200的底表面凹陷。内插器孔200H可以形成为穿透内插器200。例如，内插器孔200H可以在第一方向Z上延伸以穿透内插器200。
内插器沟槽200T的至少一部分和内插器孔200H的至少一部分可以每个与第一半导体芯片110重叠。在一些示例实施方式中，内插器沟槽200T的至少一部分可以设置为与第一半导体芯片110的边缘重叠。在一些示例实施方式中，所述多个内插器孔200H中的至少一些可以与内插器沟槽200T重叠。在一些示例实施方式中，内插器孔200H的宽度可以小于内插器沟槽200T的宽度。
参照图16，形成第一模制层170。
例如，可以在第一封装基板100和内插器200之间注入流体模制材料。模制材料可以包括例如绝缘聚合物材料，诸如环氧模塑料(EMC)，但是不限于此。
在第一封装基板100和内插器200之间注入和流动的模制材料可以填充在第一封装基板100和内插器200之间的区域。流动的模制材料可以填充内插器沟槽200T以及在第一半导体芯片110和内插器200之间的区域。因此，可以形成包括填充部分172的第一模制层170。由于内插器沟槽200T可以从内插器200的底表面凹陷，所以可以在第一半导体芯片110和内插器200之间确保额外的空间以改善模制材料的流动性。
此外，流动的模制材料可以穿过内插器孔200H并从内插器200的顶表面排出。排出的模制材料可以覆盖内插器200的顶表面的至少一部分。因此，可以形成包括贯穿部分174和覆盖部分176的第一模制层170。在一些示例实施方式中，覆盖部分176可以将彼此间隔开的所述多个贯穿部分174彼此连接。
在一些示例实施方式中，模制材料可以沿着内插器沟槽200T的延伸方向被注入。例如，内插器沟槽200T可以沿着第二方向Y伸长，并且模制材料可以被注入以沿着第二方向Y流动。
参照图17，切割第一封装基板100和内插器200。
例如，可以提供限定在第一半导体芯片110周围的单位封装区域的划片槽SL(见图16)。第一封装基板100和内插器200可以沿着划片槽SL(见图16)切割。因此，可以提供按包括第一半导体芯片110的每个单位封装区域切割的半导体封装。
仅示出在形成第一模制层170之后切割第一封装基板100和内插器200，但是这仅是一示例。作为另一示例，第一模制层170可以在第一封装基板100和内插器200被切割之后形成。
随后，参照图1至图4，在内插器200之上形成第二封装基板300、第二半导体芯片310和第二模制层270。因此，能够提供一种用于制造具有提高的产品可靠性的半导体封装的方法。
图18和图19是示出根据一些示例实施方式的用于制造半导体封装的方法的中间步骤的视图。为了简化描述，将简要给出或省略与参照图1至图4和图13至图17的描述重叠的描述。作为参考，图18是用于描述在图15之后的步骤的图。
参照图18，在内插器200的顶表面上提供模具500。
模具500可以包括空腔500T。空腔500T可以从模具500的底表面凹陷。当模具500设置在内插器200的顶表面上时，空腔500T可以流体地连接到内插器孔200H。例如，空腔500T可以设置为在第一方向Z上与所述多个内插器孔200H重叠。
参照图19，使用模具500形成第一模制层170。
例如，在将模具500设置在内插器200的顶表面上之后，可以在第一封装基板100和内插器200之间注入流体模制材料。流动的模制材料可以穿过内插器孔200H以填充空腔500T。因此，可以形成包括贯穿部分174和覆盖部分176的第一模制层170。在形成第一模制层170之后，可以移除模具500。
随后，可以执行以上参照图16和图17以及图1至图4描述的步骤。因此，能够提供一种用于制造具有提高的产品可靠性的半导体封装的方法。
在结束详细描述时，本领域技术人员将理解，在实质上不脱离本发明构思的原理的情况下，可以对所公开的示例实施方式进行许多变化和修改。因此，本发明构思的所公开的示例实施方式仅以一般性和描述性的含义来使用，而不是为了限制的目的。

Claims (20)

1.一种半导体封装，包括：
第一封装基板；
第一半导体芯片，在所述第一封装基板的顶表面上；
电连接到所述第一封装基板的内插器，在所述第一半导体芯片的顶表面上；以及
模制层，配置为覆盖所述第一封装基板和所述第一半导体芯片，
其中所述内插器包括从所述内插器的底表面凹陷的内插器沟槽和穿透所述内插器的内插器孔，所述内插器的所述底表面面对所述第一半导体芯片的所述顶表面和所述第一封装基板的所述顶表面两者，以及
所述模制层包括填充在所述第一封装基板和所述内插器之间的区域的填充部分、填充所述内插器孔的贯穿部分、以及覆盖所述内插器的顶表面的至少一部分的覆盖部分。
2.根据权利要求1所述的半导体封装，其中所述内插器与所述第一半导体芯片的所述顶表面间隔开，以及
所述填充部分还填充在所述第一半导体芯片和所述内插器之间的区域。
3.根据权利要求1所述的半导体封装，其中在平面图中，所述内插器沟槽的至少一部分和所述内插器孔的至少一部分与所述第一半导体芯片重叠。
4.根据权利要求3所述的半导体封装，其中在平面图中，所述内插器沟槽的至少一部分与所述第一半导体芯片的边缘重叠。
5.根据权利要求1所述的半导体封装，其中所述内插器沟槽沿着平行于所述内插器的所述底表面的第一方向布置为多个。
6.根据权利要求5所述的半导体封装，其中布置为多个的所述内插器沟槽沿着平行于所述第一封装基板的所述顶表面并与所述第一方向交叉的第二方向延伸。
7.根据权利要求1所述的半导体封装，其中所述填充部分、所述贯穿部分和所述覆盖部分是一体的主体的不同部分。
8.根据权利要求1所述的半导体封装，其中所述内插器孔从所述内插器沟槽延伸。
9.根据权利要求1所述的半导体封装，其中所述内插器包括从所述内插器的所述底表面暴露的下焊盘、从所述内插器的所述顶表面暴露的上焊盘、以及穿透所述内插器以将所述下焊盘连接到所述上焊盘的贯穿通路。
10.根据权利要求1所述的半导体封装，还包括：
在所述第一封装基板的所述顶表面上的连接构件，所述连接构件将所述第一封装基板电连接到所述内插器，
其中所述模制层覆盖所述连接构件。
11.根据权利要求1所述的半导体封装，还包括：
在所述内插器的所述顶表面上的第二封装基板，所述第二封装基板电连接到所述内插器；以及
第二半导体芯片，在所述第二封装基板的顶表面上，所述第二封装基板的所述顶表面背对所述内插器的所述顶表面。
12.根据权利要求1所述的半导体封装，其中所述模制层包括环氧模塑料(EMC)。
13.一种半导体封装，包括：
封装基板；
半导体芯片，在所述封装基板的顶表面上；以及
在所述半导体芯片的顶表面上的内插器，所述内插器与所述半导体芯片间隔开并电连接到所述封装基板，
其中所述内插器包括，
内插器沟槽，从所述内插器的底表面凹陷并配置为在平面图中与所述半导体芯片至少部分地重叠，所述内插器的所述底表面面对所述半导体芯片的所述顶表面和所述封装基板的所述顶表面两者，以及
内插器孔，从所述内插器沟槽延伸以穿透所述内插器，所述内插器孔具有比所述内插器沟槽的宽度小的宽度。
14.根据权利要求13所述的半导体封装，其中所述内插器沟槽在平行于所述封装基板的顶表面的第一方向上延伸。
15.根据权利要求14所述的半导体封装，其中在平行于所述封装基板的所述顶表面并与所述第一方向交叉的第二方向上，所述内插器孔的宽度小于所述内插器沟槽的宽度。
16.根据权利要求13所述的半导体封装，其中在平面图中，所述内插器沟槽的至少一部分与所述半导体芯片的边缘重叠。
17.根据权利要求13所述的半导体封装，还包括：
模制层，覆盖所述封装基板和所述半导体芯片并填充所述内插器沟槽和所述内插器孔。
18.根据权利要求17所述的半导体封装，其中所述模制层的一部分覆盖所述内插器的顶表面的至少一部分。
19.一种半导体封装，包括：
第一封装基板；
在所述第一封装基板的顶表面上的第一半导体芯片；
在所述第一半导体芯片的顶表面上的第二封装基板；
在所述第二封装基板的顶表面上的第二半导体芯片；
内插器，与所述第一半导体芯片间隔开并在所述第一半导体芯片和所述第二封装基板之间；
第一连接构件，在所述第一封装基板和所述内插器之间，所述第一连接构件将所述第一封装基板电连接到所述内插器；
在所述第一封装基板的所述顶表面上的模制层，所述模制层覆盖所述第一连接构件和所述第一半导体芯片；以及
在所述内插器和所述第二封装基板之间的第二连接构件，所述第二连接构件将所述内插器电连接到所述第二封装基板，
其中所述内插器包括从所述内插器的底表面凹陷的内插器沟槽和穿透所述内插器的内插器孔，所述内插器的所述底表面面对所述第一半导体芯片的所述顶表面和所述第一封装基板的所述顶表面两者，以及
所述模制层填充所述内插器沟槽和所述内插器孔。
20.根据权利要求19所述的半导体封装，其中所述模制层的一部分覆盖所述内插器的顶表面的至少一部分。
CN202111411622.XA 2020-11-25 2021-11-25 半导体封装 Pending CN114551415A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2020-0159485 2020-11-25
KR1020200159485A KR20220072169A (ko) 2020-11-25 2020-11-25 반도체 패키지 및 그 제조 방법

Publications (1)

Publication Number Publication Date
CN114551415A true CN114551415A (zh) 2022-05-27

Family

ID=81658604

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111411622.XA Pending CN114551415A (zh) 2020-11-25 2021-11-25 半导体封装

Country Status (3)

Country Link
US (1) US11923283B2 (zh)
KR (1) KR20220072169A (zh)
CN (1) CN114551415A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024125036A1 (zh) * 2022-12-13 2024-06-20 海光信息技术股份有限公司 封装结构、芯片、电子设备、封装结构的制造方法及芯片封装方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230000725A (ko) * 2021-06-25 2023-01-03 삼성전자주식회사 반도체 패키지

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5504035A (en) 1989-08-28 1996-04-02 Lsi Logic Corporation Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate
US5530288A (en) 1994-10-12 1996-06-25 International Business Machines Corporation Passive interposer including at least one passive electronic component
JP4324773B2 (ja) 2003-09-24 2009-09-02 セイコーエプソン株式会社 半導体装置の製造方法
US7331796B2 (en) 2005-09-08 2008-02-19 International Business Machines Corporation Land grid array (LGA) interposer utilizing metal-on-elastomer hemi-torus and other multiple points of contact geometries
US9070679B2 (en) 2009-11-24 2015-06-30 Marvell World Trade Ltd. Semiconductor package with a semiconductor die embedded within substrates
US8426961B2 (en) 2010-06-25 2013-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded 3D interposer structure
US20130147026A1 (en) 2011-12-12 2013-06-13 Ati Technologies Ulc Heatsink interposer
US9299650B1 (en) 2013-09-25 2016-03-29 Stats Chippac Ltd. Integrated circuit packaging system with single metal layer interposer and method of manufacture thereof
KR102245770B1 (ko) 2013-10-29 2021-04-28 삼성전자주식회사 반도체 패키지 장치
US9741649B2 (en) 2014-06-04 2017-08-22 Invensas Corporation Integrated interposer solutions for 2D and 3D IC packaging
US10453785B2 (en) 2014-08-07 2019-10-22 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming double-sided fan-out wafer level package
KR101653563B1 (ko) 2015-06-11 2016-09-02 앰코 테크놀로지 코리아 주식회사 적층형 반도체 패키지 및 이의 제조 방법
KR102327548B1 (ko) * 2017-10-17 2021-11-16 삼성전자주식회사 반도체 패키지

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024125036A1 (zh) * 2022-12-13 2024-06-20 海光信息技术股份有限公司 封装结构、芯片、电子设备、封装结构的制造方法及芯片封装方法

Also Published As

Publication number Publication date
US20220165651A1 (en) 2022-05-26
KR20220072169A (ko) 2022-06-02
US11923283B2 (en) 2024-03-05

Similar Documents

Publication Publication Date Title
US11133296B2 (en) Semiconductor package
US10734367B2 (en) Semiconductor package and method of fabricating the same
US10410968B2 (en) Semiconductor package and method of manufacturing the same
US10297582B2 (en) BVA interposer
KR101479512B1 (ko) 반도체 패키지의 제조방법
KR102448248B1 (ko) Pop형 반도체 패키지 및 그 제조 방법
US20230207416A1 (en) Semiconductor packages
CN110797321B (zh) 半导体封装件
US20240194626A1 (en) Semiconductor package
US11610864B2 (en) Chip package structure and method of forming the same
CN114551415A (zh) 半导体封装
US20120083096A1 (en) Semiconductor device having a simplified stack and method for manufacturing tehreof
US20190295909A1 (en) Package substrate for semiconductor package, semiconductor package including the same and method of manufacturing the same
KR101227078B1 (ko) 반도체 패키지 및 그 형성방법
CN115295540A (zh) 半导体封装
US11515262B2 (en) Semiconductor package and method of fabricating the same
CN116454051A (zh) 半导体封装
CN114171510A (zh) 包括具有外绝缘层的基板的半导体封装
US20240074049A1 (en) Printed circuit board
US11990441B2 (en) Semiconductor package
US20230026211A1 (en) Semiconductor package and method of fabricating the same
CN116053243A (zh) 封装衬底和包括该封装衬底的半导体封装
KR20230154588A (ko) 반도체 패키지
CN117878090A (zh) 半导体封装
CN113725198A (zh) 半导体封装

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination