CN114171510A - 包括具有外绝缘层的基板的半导体封装 - Google Patents

包括具有外绝缘层的基板的半导体封装 Download PDF

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Publication number
CN114171510A
CN114171510A CN202110717235.2A CN202110717235A CN114171510A CN 114171510 A CN114171510 A CN 114171510A CN 202110717235 A CN202110717235 A CN 202110717235A CN 114171510 A CN114171510 A CN 114171510A
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Prior art keywords
insulating layer
layer
semiconductor package
substrate
connection pad
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CN202110717235.2A
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English (en)
Inventor
金应叫
金钟润
全光宰
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN114171510A publication Critical patent/CN114171510A/zh
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Abstract

一种半导体封装，可以包括：基板和在基板上的半导体芯片。基板可以包括：内绝缘层；再分布层，在内绝缘层中；外绝缘层，在内绝缘层上；连接焊盘，设置在外绝缘层中并且电连接到再分布层；以及，接地电极，在外绝缘层中。连接焊盘的顶表面可以通过外绝缘层的顶表面暴露，并且连接焊盘的顶表面的高度可以低于外绝缘层的顶表面的高度。接地电极的底表面的高度可以高于再分布层的顶表面的高度，并且外绝缘层覆盖接地电极的顶表面。

Description

包括具有外绝缘层的基板的半导体封装
相关申请的交叉引用
本申请要求于2020年9月11日向韩国知识产权局递交的韩国专利申请No.10-2020-0117172的优先权，其公开内容通过引用全部合并于此。
技术领域
本公开涉及半导体封装，具体涉及其中设置有具有外绝缘层的基板的半导体封装。
背景技术
半导体封装被配置为允许集成电路芯片被容易地用作电子产品的一部分。通常，半导体封装包括诸如印刷电路板(PCB)和/或再分布层(RDL)之类的基板、以及安装在其上的半导体芯片。每个半导体封装中安装有多个半导体芯片。半导体芯片被配置为具有各种功能。例如，可以将多个存储器芯片和至少一个逻辑芯片安装在一个基板上。存储器芯片通过硅通孔(TSV)彼此电连接，并且被设置为具有堆叠的形状。这种类型的半导体封装可以被称为“2.5D封装”。由于半导体封装的输入/输出端子的数量已经增多，半导体封装的尺寸也已经增大。因此，用于减小半导体封装的尺寸的技术会变得重要。
发明内容
本发明构思的实施例提供了一种防止在连接端子之间形成短路的半导体封装以及制造该半导体封装的方法。
本发明构思的实施例提供了一种在其中设置小间距的连接端子的半导体封装以及制造该半导体封装的方法。
本发明构思的实施例提供了一种被配置为具有改善的信号完整性(SI)特性的半导体封装以及制造该半导体封装的方法。
本发明构思的实施例提供了一种可以容易地执行下填充层的填充工艺的半导体封装以及制造该半导体封装的方法。
本发明构思的实施例提供了一种被配置为防止或抑制翘曲问题的半导体封装以及制造该半导体封装的方法。
根据本发明构思的实施例，一种半导体封装，可以包括：基板和在基板上的半导体芯片。基板可以包括：内绝缘层；再分布层，在内绝缘层中；外绝缘层，在内绝缘层上；连接焊盘，设置在外绝缘层中并且电连接到再分布层；以及，接地电极，在外绝缘层中。连接焊盘的顶表面可以通过外绝缘层的顶表面暴露，并且连接焊盘的顶表面的高度可以低于外绝缘层的顶表面的高度。接地电极的底表面的高度可以高于再分布层的顶表面的高度，并且外绝缘层覆盖接地电极的顶表面。
根据本发明构思的一个实施例，一种半导体封装，可以包括：基板；逻辑芯片，在基板上；以及，高宽带存储器(HBM)，设置在基板上并且与逻辑芯片水平地间隔开。基板可以包括：内绝缘层；再分布层，在内绝缘层中；外绝缘层，在内绝缘层上；连接焊盘，设置在外绝缘层中并且电连接到再分布层；以及，连接通路，将连接焊盘连接到再分布层。连接焊盘的顶表面可以通过外绝缘层的顶表面暴露，并且连接焊盘的顶表面的高度可以低于外绝缘层的顶表面的高度。
根据本发明构思的一个实施例，一种半导体封装，可以包括：再分布基板；半导体芯片，在再分布基板上；下部球，将再分布基板电连接到半导体芯片；以及，下填充层，在再分布基板和半导体芯片之间。再分布基板可以包括：内绝缘层；再分布层，在内绝缘层中；外绝缘层，在内绝缘层上；连接焊盘，设置在外绝缘层中并且电连接到再分布层；连接通路，将连接焊盘连接到再分布层；以及，接地电极，在外绝缘层中。连接焊盘可以设置在暴露孔中，暴露孔设置在外绝缘层中，并且连接焊盘的顶表面的高度可以低于外绝缘层的顶表面的高度。接地电极可以与连接焊盘水平地间隔开，并且接地电极的底表面的高度可以与连接焊盘的底表面的高度相同。外绝缘层可以覆盖接地电极的顶表面。下部球可以通过在下部球和连接焊盘之间形成的中间层电连接到连接焊盘。下填充层的一部分可以填充暴露孔的一部分。
附图说明
根据下列结合附图的简要描述，将更清楚地理解示例实施例。附图表示本文所述的非限制性示例实施例。
图1是示出了根据本发明构思的实施例的半导体封装的截面图。
图2是示出了根据示例实施例的图1的部分X1的放大截面图。
图3是示出了根据本发明构思的实施例的制造半导体封装的方法的流程图。
图4至图20是示出了根据示例实施例的使用图3的流程图所示的制造半导体封装的方法来制造半导体封装的过程的截面图。
图21是示出了根据本发明构思的实施例的半导体封装的截面图。
应当注意，这些附图旨在说明在某些示例实施例中使用的方法、结构和/或材料的一般特性，并补充下面提供的书面描述。但是，这些附图没有按比例绘制且不能精确地反映任何给定实施例的精确结构或性能特性，并且不应被解释为限定或限制示例实施例所包含的值或特性的范围。例如，为了清楚起见，分子、层、区域和/或结构元件的相对厚度和定位可被减小或夸大。在各种附图中使用相似或相同的附图标记旨在表示存在相似或相同的元件或特征。
具体实施方式
现在将参考示出了示例性实施例的附图来更全面地描述本发明构思的示例实施例。
图1是示出了根据本发明构思的实施例的半导体封装的截面图。
在下文中，图1中的附图标记“D1”和“D2”将分别被称为第一方向和第二方向，并且被描绘为与第一方向D1和第二方向D2相交的附图标记D3将被称为第三方向。
参考图1，可以提供半导体封装P。半导体封装P可以表示电子组件，在该电子组件中将半导体芯片结合到基板，并且该电子组件被配置为安装在电子产品上。例如，半导体封装P可以用2.5D封装的形式提供，如图1所示。然而，本发明构思不限于这个示例，并且在实施例中，半导体封装P可以用另一种形式提供。然而，为了便于描述，将在下面的描述中示例性地描述2.5D封装。
半导体封装P可以包括下基板7、基板1、半导体芯片SC、连接端子2、下填充层4和模制层M。
下基板7可以被配置为将半导体芯片SC和基板1电连接到另一个元件。例如，下基板7可以通过基板1电连接到半导体芯片SC，因此，半导体芯片SC可以通过下基板7连接到另一个元件。下基板7可以包括印刷电路板(PCB)，但是本发明构思不限于这个示例。
可以将基板1设置在下基板7上。可以将基板1结合到下基板7。基板1可以包括再分布层(RDL)基板或印刷电路板(PCB)。基板1可以用于将下基板7电连接到半导体芯片SC。例如，基板1可以是中介层(interposer)。下面将更详细地描述基板1。
半导体芯片SC可以表示其中设置有集成电路的电子组件。半导体芯片SC可以设置在基板1上。半导体芯片SC可以通过连接端子2耦接到基板1。下半导体芯片SC可以通过基板1电连接到下基板7。半导体芯片SC可以包括各种芯片。例如，半导体芯片SC可以包括逻辑芯片3和高宽带存储器(HBM)5。逻辑芯片3和HBM 5可以彼此水平地间隔开。逻辑芯片3的厚度可以小于HBM 5的厚度。HBM 5可以包括多个存储器芯片和/或至少一个逻辑芯片。至此，已经将半导体封装P描述为2.5D封装，但是本发明构思不限于这个示例。例如，在半导体封装P是另一种类型的封装的情况下，半导体芯片SC可以包括与上面示例的芯片种类不同种类的芯片。
在一个实施例中，可以设置多个连接端子2。连接端子2可以沿第二方向D2和第三方向D3彼此间隔开。下面将更详细地描述连接端子2。
下填充层4可以位于半导体芯片SC和基板1之间。可以将下填充层4设置为包围连接端子2的侧表面。下填充层4可以保护连接端子2。
可以将模制层M设置在基板1上，以围绕半导体芯片SC。模制层M可以由环氧树脂模制化合物形成或包括环氧树脂模制化合物。
图2是示出了根据示例实施例的图1的部分X1的放大截面图。
参考图2，基板1可以包括内绝缘层11、外绝缘层13、再分布层12、连接焊盘14、接地电极16、外连接焊盘18和外连接球1b。
内绝缘层11可以由绝缘材料中的至少一种形成或包括绝缘材料中的至少一种。例如，内绝缘层11可以包括光敏环氧树脂。更具体地，内绝缘层11可以包括光成像电介质(PID)。可以将内绝缘层11设置在外绝缘层13下方。可以将再分布层12等设置在内绝缘层11中。内绝缘层11可以包括多个层。例如，内绝缘层11可以包括第一内绝缘层111、第二内绝缘层112、第三内绝缘层113和第四内绝缘层114。可以将外连接焊盘18设置在第一内绝缘层111中。可以将第二内绝缘层112设置在第一内绝缘层111上。第一再分布层121可以被设置在第二内绝缘层112中，并且可以通过连接通路电连接到外连接焊盘18。可以将第三内绝缘层113设置在第二内绝缘层112上。第二再分布层122可以被设置在第三内绝缘层113中，并且可以通过连接通路连接到第一再分布层121。可以将第四内绝缘层114设置在第三内绝缘层113上。第三再分布层123可以被设置在第四内绝缘层114中，并且可以通过连接通路电连接到第二再分布层122。至此，已经将内绝缘层11描述为由四层组成，但是本发明构思不限于这个示例。例如，构成内绝缘层11的层的数量可以不是4。在一个实施例中，所有的内绝缘层可以由相同的材料形成或包括相同的材料。在这种情况下，在内绝缘层之间可以没有可观察到的界面。下面将更详细地描述形成内绝缘层的方法。
可以将外绝缘层13设置在内绝缘层11上。外绝缘层13可以由绝缘材料中的至少一种形成或包括绝缘材料中的至少一种。例如，外绝缘层13可以包括光敏环氧树脂。更具体地，外绝缘层13可以包括光成像电介质(PID)。可以将连接焊盘14和接地电极16设置在外绝缘层13中。外绝缘层13可以设置暴露孔13h。可以将连接焊盘14设置在暴露孔13h中。暴露孔13h可以暴露连接焊盘14。更具体地，连接焊盘14的顶表面14u可以通过外绝缘层13的顶表面13u暴露。下填充层4的一部分可以位于暴露孔13h的区域中。例如，除了由连接焊盘14占据的区域以外，可以利用下填充层4来填充暴露孔13h的其余区域。外绝缘层13的顶表面13u的高度(1evel)可以高于连接焊盘14的顶表面14u的高度。外绝缘层13的顶表面13u和连接焊盘14的顶表面14u之间的高度差可以被称为d1。例如，外绝缘层13的顶表面13u和连接焊盘14的顶表面14u之间的高度差d1可以在从约3μm至约5μm的范围内。外绝缘层13的厚度可以在从约8μm至约12μm的范围内。下面将更详细地进行描述。外绝缘层13和内绝缘层11可以由相同的材料形成或包括相同的材料。例如，在内绝缘层11和外绝缘层13之间可以没有可观察到的界面。下面将更详细地描述形成外绝缘层的方法。
可以将再分布层12设置在内绝缘层11中。再分布层12可以包括第一再分布层121、第二再分布层122和第三再分布层123。如上所述，第一再分布层121、第二再分布层122和第三再分布层123中的每一个可以置于第二内绝缘层112、第三内绝缘层113和第四内绝缘层114中的对应的一个中。第一再分布层121、第二再分布层122和第三再分布层123可以彼此竖直地重叠。每个再分布层的厚度可以在从约1μm至约4μm的范围内。第一再分布层121、第二再分布层122和第三再分布层123可以彼此电连接。更具体地，第一再分布层121、第二再分布层122和第三再分布层123可以通过再分布通路或连接通路(未示出)彼此连接。再分布层12可以被配置为提供电信号的传导路径。再分布层12可以置于接地电极16下方。更具体地，再分布层12的最上面的表面123u的高度可以低于接地电极16的底表面16b的高度。在示例实施例中，第一再分布层121、第二再分布层122和第三再分布层123中的每一个可以包括籽晶阻挡层。
可以将连接焊盘14设置在外绝缘层13中。连接焊盘14可以通过连接通路电连接到第三再分布层123。连接焊盘14可以包括焊盘层141和籽晶阻挡层143。焊盘层141可以由铜(Cu)形成或包括铜(Cu)。在一个实施例中，焊盘层141可以由铜(Cu)、镍(Ni)和/或金(Au)形成或包括铜(Cu)、镍(Ni)和/或金(Au)。籽晶阻挡层143可以由铜(Cu)和/或钛(Ti)形成或包括铜(Cu)和/或钛(Ti)。连接焊盘14的顶表面14u可以通过外绝缘层13的顶表面13u暴露。连接焊盘14的顶表面14u可以连接到连接端子2。可以通过连接焊盘14将再分布层12电连接到连接端子2。连接焊盘14的顶表面14u的高度可以低于外绝缘层13的顶表面13u的高度。连接焊盘14的厚度可以被称为d2。连接焊盘14的厚度d2可以等于或大于约4μm。
可以将接地电极16设置在外绝缘层13中。接地电极16可以与连接焊盘14水平地间隔开。接地电极16可以包括接地层161和籽晶阻挡层163。接地层161可以由与焊盘层141的材料实质上相同的材料形成或包括与焊盘层141的材料实质上相同的材料。例如，接地层161可以由铜(Cu)形成或包括铜(Cu)。在一个实施例中，接地层161可以由铜(Cu)、镍(Ni)和/或金(Au)形成或包括铜(Cu)、镍(Ni)和/或金(Au)。籽晶阻挡层163可以由铜(Cu)和/或钛(Ti)形成或包括铜(Cu)和/或钛(Ti)。接地电极16的底表面16b的高度可以高于再分布层12的最上面的表面123u的高度。接地电极16的底表面16b的高度可以等于连接焊盘14的底表面的高度或与连接焊盘14的底表面的高度相似。接地电极16的顶表面16u的高度可以等于连接焊盘14的顶表面14u的高度或与连接焊盘14的顶表面14u的高度相似。例如，接地电极16的厚度可以等于连接焊盘14的厚度或与连接焊盘14的厚度相似。例如，接地电极16的厚度可以等于或大于约4μm。接地电极16可以覆盖有外绝缘层13。例如，接地电极16的顶表面16u可以覆盖有外绝缘层13。外绝缘层13可以被设置为使得接地电极16不暴露于外部。接地电极16可以电连接到接地球(未示出)。下面将更详细地进行描述。
可以将外连接焊盘18设置在第一内绝缘层111中。外连接焊盘18的底表面可以通过内绝缘层11的底表面暴露。
外连接球1b可以耦接到外连接焊盘18的底表面。外连接球1b可以电连接到再分布层12。外连接球1b可以耦接到下基板焊盘73。可以通过外连球1b将再分布层12电连接到下基板7。在一个实施例中，可以设置多个外连接球1b。外连接球1b可以包括接地球(未示出)。接地球可以电连接到接地电极16。接地球可以用于使接地电极16接地到外部。
逻辑芯片3可以包括芯片主体31和下焊盘33。芯片主体31可以包括设置在其中的各种集成电路。可以将下焊盘33设置在芯片主体31下方。可以将连接端子2耦接到下焊盘33。
连接端子2可以包括柱部21和下部球23。可以将柱部21耦接到下焊盘33。柱部21可以从下焊盘33向下延伸。可以通过下焊盘33将柱部21电连接到芯片主体31中的集成电路。在一个实施例中，柱部21可以由铜(Cu)形成或包括铜(Cu)。例如，柱部21可以表示铜柱。柱部21的直径可以被称为r1。柱部21的直径r1可以大于下焊盘33的宽度r2。柱部21的直径r1可以在从约30μm至约60μm的范围内。下部球23可以结合到柱部21的底部。下部球23可以包括焊剂。例如，下部球23可以由Sn-Ag等形成或包括Sn-Ag等。可以将下部球23耦接到连接焊盘14。如果下部球23耦接到连接焊盘14，则下部球23可以变形。更具体地，在通过回流工艺或热压缩结合工艺将下部球23耦接到连接焊盘14的情况下，下部球23可以变形。例如，下部球23可以沿焊盘层141的顶表面水平地变宽。可以在下部球23和焊盘层141之间形成中间层I。中间层I可以是金属间化合物(IMC)。可以通过下部球23和连接焊盘14之间的结合形成中间层I。中间层I可以是在下部球23和连接焊盘14之间的金属间化合物(IMC)。更具体地，中间层I可以是在下部球23和焊盘层141之间的金属间化合物(IMC)。可以通过中间层I将下部球23耦接到连接焊盘14。可以将下部球23电连接到连接焊盘14。例如，可以通过中间层I将下部球23电连接到焊盘层141。
下基板7可以包括下基板主体71和下基板焊盘73。可以将下基板焊盘73耦接到外连接球1b。可以通过外连球1b将下基板焊盘73电连接到基板1。
图3是示出了根据本发明构思的实施例的制造半导体封装的方法的流程图。
参考图3，可以提供用于制造半导体封装的方法(S)。图1的半导体封装P可以通过图3的制造方法(S)来制造。制造方法(S)可以包括：形成初步再分布基板(步骤S1)；将半导体芯片耦接到初步再分布基板(步骤S2)；执行模制工艺(步骤S3)；将外连接球耦接到初步再分布基板(步骤S4)；切割初步再分布基板以形成再分布基板(步骤S5)；以及，将再分布基板耦接到PCB(步骤S6)。
形成初步再分布基板(步骤S1)可以包括：形成外连接焊盘(步骤S11)；形成再分布层(步骤S12)；形成连接焊盘(步骤S13)；以及，形成外绝缘层(步骤S14)。
在下文中，将参考图4至图20更详细地描述图3的制造方法S的每个步骤。
图4至图20是示出了根据示例实施例的使用图3的流程图所示的制造半导体封装的方法来制造半导体封装的过程的截面图。
结合图3参考图4和图5，可以对承载基板C执行形成外连接焊盘(步骤S11)。可以在晶片状态下处理初步再分布基板1′。例如，可以在晶片状态下而不是在单个芯片的形状下处理和形成初步再分布基板1′。可以将粘合层B设置承载基板C上。第一初步籽晶阻挡层SB1可以形成在承载基板C上。可以通过介于第一初步籽晶阻挡层SB1和承载基板C两者之间的粘合层B将第一初步籽晶阻挡层SB1耦接到承载基板C。第一光掩模图案M1可以形成在第一初步籽晶阻挡层SB1上。可以将第一光掩模图案M1形成为具有开口，将在开口中形成外连接焊盘18。第一光掩模图案M1可以通过形成、曝光和显影光刻胶层而形成。外连接焊盘18可以形成在第一光掩模图案M1的开口中。例如，外连接焊盘18可以通过电镀工艺形成，在电镀工艺中，将第一初步籽晶阻挡层SB1用作电极。在形成外连接焊盘18以后，可以去除第一光掩模图案M1。在去除第一光掩模图案M1以后，可以形成第一内绝缘层111(例如，参见图6)。第一内绝缘层111可以通过涂敷工艺(例如，旋涂工艺或狭缝涂敷工艺)形成。可以通过曝光和显影工艺来图案化第一内绝缘层111。
结合图3参考图6和图7，形成再分布层(步骤S12)可以包括：在外连接焊盘18和图案化的第一内绝缘层111上形成第二初步籽晶阻挡层SB2和第二光掩模图案M2。可以将第二光掩模图案M2形成为具有开口，并且第一再分布层121可以形成在第二光掩模图案M2的开口中。第一再分布层121可以通过电镀工艺形成，在电镀工艺中，第二初步籽晶阻挡层SB2用作电极。
参考图8，可以去除第二光掩模图案M2。此外，可以从除了第一再分布层121的下部区域以外的区域去除第二初步籽晶阻挡层SB2。第二初步籽晶阻挡层SB2可以通过各种方法去除。例如，第二初步籽晶阻挡层SB2可以通过蚀刻工艺去除。然而，本发明构思不限于这个示例，并且在一个实施例中，第二初步籽晶阻挡层SB2可以通过各种其他方法去除。
参考图9，可以在第一内绝缘层111和第一再分布层121上形成第二再分布层122和第三再分布层123。第二再分布层122和第三再分布层123可以通过与用于第一再分布层121的方法相同的方法形成。
结合图3参考图10和图11，形成连接焊盘(步骤S13)可以包括：在再分布层12和内绝缘层11上形成连接焊盘14和接地电极16。连接焊盘14和接地电极16可以通过与用于再分布层12的方法相似的方法形成。例如，连接焊盘14和接地电极16可以通过电镀工艺形成，在电镀工艺中，籽晶阻挡层用作电极。连接焊盘14和接地电极16可以通过一次执行电镀工艺而同时形成。因此，连接焊盘14的底表面14b的高度可以等于接地电极16的底表面16b的高度或与接地电极16的底表面16b的高度相似。连接焊盘14的顶表面14u的高度可以等于接地电极16的顶表面16u的高度或与接地电极16的顶表面16u的高度相似。可以将连接焊盘14电连接到再分布层12。更具体地，可以将连接焊盘14连接到第三再分布层123的顶表面。
在根据本发明构思的实施例的半导体封装及其制造方法中，连接焊盘和接地电极可以通过单个工艺同时形成。因此，连接焊盘和接地电极可以由相同的材料形成或包括相同的材料。此外，因为连接焊盘和接地电极同时形成，所以可以减少工艺步骤的数量并且由此简化总体制造工艺。因此，可以减少工艺时间和制造成本。
结合图3参考图12和图13，形成外绝缘层(步骤S14)可以包括：形成外绝缘层13′以覆盖接地电极16。可以图案化外绝缘层13′。更具体地，外绝缘层13′可以被图案化以暴露连接焊盘14。例如，外绝缘层13′可以被图案化为限定暴露孔13h′。可以将连接焊盘14设置在暴露孔13h′中。即使在外绝缘层13′被图案化时，接地电极16也可以不暴露。例如，接地电极16可以覆盖有外绝缘层13′。
参考图14和图15，可以在外绝缘层13′固化以后形成外绝缘层13。在外绝缘层13′固化以后，限定暴露孔13h的外绝缘层13的侧表面可以相对于外绝缘层13的顶表面以某一角度倾斜。
参考图3和图16，将半导体芯片耦接到初步再分布基板(步骤S2)可以包括：在晶片状态下将半导体芯片SC耦接到初步再分布基板1′。在一个实施例中，当以2.5D封装的形式提供半导体封装时，半导体芯片SC可以包括逻辑芯片3和HBM 5。可以通过连接端子2将逻辑芯片3连接到初步再分布基板1′。HBM 5可以包括多个半导体芯片。例如，HBM 5可以是在其中下逻辑芯片51、第一存储器芯片52、第二存储器芯片53、第三存储器芯片54和第四存储器芯片55竖直地堆叠的结构。下逻辑芯片51可以通过连接端子2连接到初步再分布基板1′。可以经由硅通孔(TSV)将多个竖直堆叠的半导体芯片彼此电连接。逻辑芯片3和HBM 5可以彼此水平地间隔开。设置或耦接逻辑芯片3和HBM 5的顺序可以进行不同的改变。在一个实施例中，半导体芯片SC可以通过热压缩结合工艺耦接到初步再分布基板1′。然而，本发明构思不限于这个示例，并且半导体芯片SC可以通过回流工艺耦接到初步再分布基板1′。在一个实施例中，在结合半导体芯片SC以前，还可以在半导体芯片SC和初步再分布基板1′之间设置下填充层4(例如，参见图17)。可以使用毛细现象在半导体芯片SC和初步再分布基板1′之间填充下填充层4。随着半导体芯片SC和初步再分布基板1′之间的距离减小，下填充层4的填充工艺可以更高效地执行。
参考图3和图17，执行模制工艺(步骤S3)可以包括：在晶片状态下在初步再分布基板1′上形成模制层M′。模制层M′可以围绕半导体芯片SC的侧表面。更具体地，模制层M′可以围绕逻辑芯片3和HBM 5的侧表面。在HBM 5的顶表面覆盖有模制层M′的情况下，可以研磨模制层M′的上部以暴露HBM 5的顶表面。
参考图18，可以去除承载基板C(例如，参见图17)。更具体地，可以去除承载基板C、粘合层B和第一初步籽晶阻挡层SB1。可以通过蚀刻工艺来执行第一初步籽晶阻挡层SB1的去除。作为去除第一初步籽晶阻挡层SB1的结果，外连接焊盘18可以暴露。更具体地，外连接焊盘18的底表面可以通过初步再分布基板1′的底表面11b′暴露。
参考图3和图19，将外连接球耦接到初步再分布基板(步骤S4)可以包括：将外连接球1b耦接到外连接焊盘18。更具体地，外连接球1b可以耦接到通过图18中的去除第一初步籽晶阻挡层SB1而暴露的外连接焊盘18的底表面。外连接球1b可以包括焊剂球。外连接焊盘18可以通过外连接球1b电连接到外部。
参考图3和图20，切割初步再分布基板以形成再分布基板(步骤S5)可以包括：将初步再分布基板1′(例如，参见图19)和模制层切割成希望的半导体封装的尺寸。初步再分布基板的切割件可以被称为基板或再分布基板1。在第二方向D2上，模制层M的宽度可以等于基板1的宽度或与基板1的宽度相似。
将再分布基板耦接到PCB(步骤S6)可以包括：将下基板7(例如，参见图1)耦接到所切割的形状的基板1的底部。基板1和下基板7可以通过外连接球1b彼此电连接。
在根据本发明构思的实施例的半导体封装及其制造方法中，外绝缘层可以设置在比基板的连接焊盘的顶表面更高的高度处。因此，当将连接端子结合到连接焊盘时，可以防止连接端子的一部分偏斜到连接焊盘之外的区域。更具体地，即使当连接端子由于热和压力水平地变形时，外绝缘层也可以防止连接端子过度地偏斜。因此，可以防止连接端子向外偏斜的部分与相邻的连接端子接触。根据示例实施例的半导体封装，可以防止在连接端子之间形成短路问题。因此，可以减少半导体封装的故障率和提高半导体封装的良品率。
在根据本发明构思的示例实施例的半导体封装及其制造方法中，因为通过外绝缘层防止了连接端子之间的短路问题，所以可以减小半导体封装中使用的连接端子的直径。例如，即使在使用小的连接端子时，也可以防止短路问题并且由此提高半导体封装的良品率。
在根据本发明构思的示例实施例的半导体封装及其制造方法中，因为外绝缘层的顶表面的高度高于连接焊盘的顶表面的高度，所以可以进一步减小半导体芯片和基板之间的距离。例如，可以减小半导体芯片的底表面和基板的顶表面之间的距离。因此，可以改善半导体封装的翘曲问题。因此，可以提高半导体封装的性能和良品率。
在根据本发明构思的示例实施例的半导体封装及其制造方法中，因为半导体芯片的底表面和基板的顶表面之间的距离小，所以可以容易地利用下填充层填充它们之间的区域。例如，可以使用毛细现象以下填充层填充半导体芯片和基板之间的空间。半导体芯片的底表面和基板的顶表面之间的距离越小，毛细力越大。因此，如果半导体芯片的底表面和基板的顶表面之间的距离小，则下填充层的填充工艺可以更高效地执行。因此，可以防止在下填充层中形成空隙。
在根据本发明构思的示例实施例的半导体封装及其制造方法中，接地电极可以设置在其中形成有连接焊盘的层中。因此，接地电极可以设置在相对靠近半导体芯片的区域中。因此，通过接地电极可以更高效地实现信号完整性(SI)的改善。
在根据本发明构思的示例实施例的半导体封装及其制造方法中，接地电极和连接焊盘可以通过一次执行相同的工艺而同时形成。因此，可以减少工艺步骤的总数量和简化总体制造。例如，可以减少半导体封装的工艺时间和制造成本。
图21是示出了根据本发明构思的实施例的半导体封装的截面图。
在以下描述中，将省略与参考图1至图20描述的半导体封装的特征重复的特征。
参考图21，可以在形成基板1″以前设置半导体芯片SC。例如，图21的半导体封装P′可以通过芯片优先(chip-first)工艺制造。可以在半导体芯片SC的底表面上形成基板1″。更具体地，可以通过与参考图4至图15描述的方法相似的方法在半导体芯片SC的底表面上形成基板1″。外绝缘层13″可以位于低于内绝缘层11″的高度处。连接焊盘14″可以耦接到外连接球1b。
在根据本发明构思的示例实施例的半导体封装及其制造方法中，可以防止在连接端子之间形成短路问题。
在根据本发明构思的示例实施例的半导体封装及其制造方法中，可以减小连接端子的间距。
在根据本发明构思的示例实施例的半导体封装及其制造方法中，可以改善信号完整性(SI)特性。
在根据本发明构思的示例实施例的半导体封装及其制造方法中，可以容易地执行下填充层的填充工艺。
在根据本发明构思的示例实施例的半导体封装及其制造方法中，可以防止或抑制翘曲问题。
虽然已具体示出和描述了本发明构思的示例实施例，但是本领域普通技术人员将理解，在不脱离所附权利要求的精神和范围的情况下，可以对其进行形式和细节上的改变。

Claims (20)

1.一种半导体封装，包括：
基板；以及
半导体芯片，在所述基板上；
其中，所述基板包括：
内绝缘层，
再分布层，在所述内绝缘层中；
外绝缘层，在所述内绝缘层上；
连接焊盘，设置在所述外绝缘层中并且电连接到所述再分布层；以及
接地电极，在所述外绝缘层中，
其中，所述连接焊盘的顶表面通过所述外绝缘层的顶表面暴露，
其中，所述连接焊盘的顶表面的高度低于所述外绝缘层的顶表面的高度，
其中，所述接地电极的底表面的高度高于所述再分布层的顶表面的高度，并且
其中，所述外绝缘层覆盖所述接地电极的顶表面。
2.根据权利要求1所述的半导体封装，其中，所述接地电极的底表面的高度与所述连接焊盘的底表面的高度相同。
3.根据权利要求1所述的半导体封装，其中，所述外绝缘层的厚度在从8μm至12μm的范围内。
4.根据权利要求1所述的半导体封装，其中，所述外绝缘层包括与所述内绝缘层的材料相同的材料。
5.根据权利要求1所述的半导体封装，其中，所述接地电极包括与所述连接焊盘的材料相同的材料。
6.根据权利要求5所述的半导体封装，其中，所述接地电极包括铜Cu、镍Ni和金Au中的至少一种。
7.根据权利要求1所述的半导体封装，其中，所述基板还包括外连接球，所述外连接球连接到所述基板的与所述外绝缘层的顶表面相对的底表面，
其中，所述外连接球包括被接地的接地球，并且
其中，所述接地电极电连接到所述接地球。
8.根据权利要求1所述的半导体封装，其中，所述半导体芯片包括下焊盘，并且
其中，所述半导体封装还包括在所述下焊盘和所述连接焊盘之间的连接端子。
9.根据权利要求8所述的半导体封装，其中，所述连接端子包括：
柱部，耦接到所述下焊盘的底表面；以及
下部球，在所述柱部和所述连接焊盘之间。
10.根据权利要求8所述的半导体封装，其中，所述连接端子的一部分位于比所述外绝缘层的顶表面的高度低的高度处。
11.一种半导体封装，包括：
基板；
逻辑芯片，在所述基板上；以及
高宽带存储器HBM，设置在所述基板上并且与所述逻辑芯片水平地间隔开，
其中，所述基板包括：
内绝缘层，
再分布层，在所述内绝缘层中；
外绝缘层，在所述内绝缘层上；
连接焊盘，设置在所述外绝缘层中并且电连接到所述再分布层；以及
连接通路，将所述连接焊盘连接到所述再分布层，
其中，所述连接焊盘的顶表面通过所述外绝缘层的顶表面暴露，并且
其中，所述连接焊盘的顶表面的高度低于所述外绝缘层的顶表面的高度。
12.根据权利要求11所述的半导体封装，还包括设置在所述基板下方的下基板。
13.根据权利要求11所述的半导体封装，还包括：在所述逻辑芯片和所述基板之间的下填充层。
14.根据权利要求11所述的半导体封装，其中，所述逻辑芯片包括下焊盘，
其中，所述半导体封装还包括在所述下焊盘和所述连接焊盘之间的连接端子，并且
其中，所述连接端子包括：
柱部，耦接到所述下焊盘的底表面；以及
下部球，在所述柱部和所述连接焊盘之间，
其中，所述下部球的至少一部分位于比所述外绝缘层的顶表面的高度低的高度处。
15.根据权利要求11所述的半导体封装，还包括在所述外绝缘层中的接地电极，
其中，所述接地电极的底表面的高度高于所述再分布层的顶表面的高度，并且
其中，所述外绝缘层覆盖所述接地电极的顶表面。
16.一种半导体封装，包括：
再分布基板；
半导体芯片，在所述再分布基板上；
下部球，将所述再分布基板电连接到所述半导体芯片；以及
下填充层，在所述再分布基板和所述半导体芯片之间，
其中，所述再分布基板包括：
内绝缘层；
再分布层，在所述内绝缘层中；
外绝缘层，在所述内绝缘层上；
连接焊盘，设置在所述外绝缘层中并且电连接到所述再分布层；
连接通路，将所述连接焊盘连接到所述再分布层；以及
接地电极，在所述外绝缘层中，
其中，所述连接焊盘设置在暴露孔中，所述暴露孔设置在所述外绝缘层中，
其中，所述连接焊盘的顶表面的高度低于所述外绝缘层的顶表面的高度，
其中，所述接地电极与所述连接焊盘水平地间隔开，
其中，所述接地电极的底表面的高度与所述连接焊盘的底表面的高度相同，
其中，所述外绝缘层覆盖所述接地电极的顶表面，
其中，所述下部球通过在所述下部球和所述连接焊盘之间形成的中间层电连接到所述连接焊盘，并且
其中，所述下填充层的一部分填充所述暴露孔的一部分。
17.根据权利要求16所述的半导体封装，其中，所述外绝缘层的厚度在从8μm至12μm的范围内，并且
其中，所述连接焊盘的厚度等于或大于4μm。
18.根据权利要求16所述的半导体封装，其中，所述中间层包括：在所述连接焊盘和所述下部球之间的金属间化合物。
19.根据权利要求16所述的半导体封装，其中，所述接地电极的厚度与所述连接焊盘的厚度相同。
20.根据权利要求16所述的半导体封装，其中，所述再分布层包括多个再分布层，所述多个再分布层彼此竖直地重叠，并且
其中，所述多个再分布层中的最上面的层的顶表面的高度低于所述接地电极的底表面的高度。
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