CN114512533A - 碳化硅结型场效应管 - Google Patents

碳化硅结型场效应管 Download PDF

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CN114512533A
CN114512533A CN202011283253.6A CN202011283253A CN114512533A CN 114512533 A CN114512533 A CN 114512533A CN 202011283253 A CN202011283253 A CN 202011283253A CN 114512533 A CN114512533 A CN 114512533A
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张梓豪
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Pn Junction Semiconductor Hangzhou Co ltd
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    • H01L29/808Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
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    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • HELECTRICITY
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    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices

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Abstract

本发明涉及一种碳化硅结型场效应管。该碳化硅结型场效应管包括碳化硅衬底(101)、设置在碳化硅衬底上的碳化硅外延层(102)、阻断注入区(103)、设置在碳化硅外延层(102)的左右两侧的两个栅极注入区(104)和两个源极注入区(105)、以及栅极金属电极(107)和源极金属电极(106),该栅极注入区(104)的正向截面为L型,包括竖直边和垂直边,在侧向沿整个碳化硅外延层(102)延伸,两个栅极注入区(104)的L型截面的竖直边相背对;源极注入区(105)设置在对应的L型截面的横边上,沿整个碳化硅外延层(102)的侧向延伸,阻断注入区(103)与两个栅极注入区(104)的L型截面的竖直边分别通过第一连通柱(110)相连接。

Description

碳化硅结型场效应管
技术领域
本发明涉及半导体技术,尤其涉及碳化硅结型场效应管。
背景技术
碳化硅半导体的优异性能使得基于碳化硅的电力电子器件与硅基器件相比具有突出的优点。碳化硅器件具有更低的导通电阻、更高的击穿电压、更好的热导性以及耐高温性能。同时,碳化硅制成的电力电子器件正向和反向特性随温度的变化很小,具有更高的稳定性。由于开关损耗小、开关频率高,碳化硅有望替代硅成为功率器件的主流材料。其中,碳化硅(SiC)JFET是碳化硅结型场效应管,具有导通电阻低、开关速度快、耐高温及热稳定性高等优点。
当前,碳化硅JFET大多为常开型器件。常开型碳化硅JFET在没有驱动信号时处于导通状态,容易造成桥臂的直通危险,降低了功率电路的安全可靠性。
发明内容
本发明鉴于现有技术的以上情况作出,用以克服或缓解现有技术中存在的一种或更多种问题,至少提供一种有益的选择。
为实现上述目的,提供了一种碳化硅结型场效应管,所述碳化硅结型场效应管包括碳化硅衬底、设置在所述碳化硅衬底上的碳化硅外延层、阻断注入区、设置在所述碳化硅外延层的左右两侧的两个栅极注入区和两个源极注入区、以及栅极金属电极和源极金属电极,所述栅极注入区在正向截面为L型,包括竖直边和垂直边,在侧向沿整个碳化硅外延层延伸,所述两个栅极注入区的L型截面的竖直边相背对;所述源极注入区设置在对应的所述栅极注入区的L型截面的横边上,所述源极注入区沿整个碳化硅外延层的侧向延伸,所述阻断注入区与所述两个栅极注入区的L型截面的竖直边分别通过第一连通柱相连接。
根据一种实施方式,所述第一连通柱为方柱,其横向的宽度与所述栅极注入区的所述竖直边的宽度一致,其侧向的宽度比所述竖直边的宽度窄。
根据一种实施方式,所述碳化硅结型场效应管还包括绝缘层,所述绝缘层使得所述源极金属电极和所述栅极金属电极之间实现电性能隔离。
根据一种实施方式,所述碳化硅结型场效应管还包括第二连通柱,所述第二连通柱用来连通所述源极金属电极和所述源极注入区,所述第二连通柱的横向宽度窄于所述源极注入区的横向宽度,所述第二连通柱的侧向宽度窄于所述源极注入区的侧向宽度,所述第二连通柱设置在所述源极注入区的远离栅极注入区的所述竖直边的位置。
根据一种实施方式,所述第一连通柱的横向宽度大于所述第二连通柱的横向宽度,所述栅极注入区的厚度大于所述源极注入区的厚度。
根据一种实施方式,所述竖直边的高度被设置为使得可以通过改变所述栅极注入区的掺杂浓度而在未通电的情况下,所述栅极注入区的耗尽区和所述阻断注入区的耗尽区之间能够形成沟道。
根据一种实施方式,所述竖直边的高度被设置为使得可以通过改变所述栅极注入区的掺杂浓度而在未通电的情况下所述栅极注入区的耗尽区和所述阻断注入区的耗尽区之间不形成沟道。
根据本发明的一些实施方式,提供了一种垂直型的碳化硅JFET结构,具有优良的耐压能力,适用于大功率应用。
根据本发明的一些实施方式,提供了一种垂直型的碳化硅JFET结构,其正向导通电阻低,可通过调节注入区的位置和掺杂浓度来控制器件的常开和常闭。
附图说明
结合附图可以更好地理解本发明的实施方式。应该注意,这些附图只是示意性的,并不是按照比例绘制的。在附图中:
图1示出了依据本发明一种实施方式的碳化硅JFET的立体结构示意图;
图2为图1的立体结构的透视图;
图3为图1、图2中A-A'截面的结构示意图;
图4为图1、图2中B-B'截面的结构示意图;
图5为示出了依据本发明另一实施方式的碳化硅JFET结构在B-B'截面的结构示意图。
具体实施方式
现在结合附图对本发明的碳化硅结型场效应管的实施方式进行说明,这些实施方式仅仅是示意性的,不是对本发明的保护范围的限制。
图1示出了依据本发明一种实施方式的碳化硅结型场效应管(JFET)的立体结构示意图;图2为图1的立体结构的透视图;图3为图1、图2中A-A'截面的结构示意图;图4为图1、图2中B-B'截面的结构示意图。根据一种实施方式,该碳化硅结型场效应管可以为载流子倒流的碳化硅结型场效应管。
如图1到图4所示,依据本发明的一种实施方式的一种碳化硅结型场效应管包括碳化硅衬底101,该碳化硅衬底101的掺杂类型为第一导电类型。在碳化硅衬底101背面覆盖有漏极金属电极108。在碳化硅衬底101上生长有碳化硅外延层102,其中该碳化硅外延层102的外延掺杂类型为第一导电类型。在碳化硅外延层102上设有阻断注入区103,在其两侧设有栅极注入区104和源极注入区105。
其中,阻断注入区103和栅极注入区104的掺杂类型为第二导电类型,源极注入区105的掺杂类型为第一导电类型。在碳化硅外延层102上还覆盖有源极金属电极106、栅极金属电极107以及绝缘层111。绝缘层111的存在使得各个金属电极之间实现电性能隔离。
根据一种实施方式,从图1和图2中立体图的正面(正向)看,栅极注入区104的截面为L型,在图中立体图的侧面(侧向),栅极注入区104沿整个碳化硅衬底101的侧向延伸。源极注入区105的截面为矩形,从正向看,源极注入区105设置在该栅极注入区104的L型截面的横向边上。横向为图中立体图的正面的从左到右或从右到左的方向。竖直方向和厚度方向为图中立体图的从上到下或从下到上的方向。
源极注入区105沿整个碳化硅外延层102的侧向延伸。该左右两侧的栅极注入区104的L型截面的竖直边相背对,在上方以及中间形成沟道区域。阻断注入区103的下侧与左右两侧的栅极注入区104的L型截面的竖直边分别通过第一连通柱110相连接,从而阻断注入区103、两个第一连通柱110、与左右两侧的栅极注入区104形成类似π型结构。第一连通柱110为柱状,其横向的宽度与栅极注入区104的L型截面的竖直边的宽度一致,其侧向的宽度比栅极注入区104的L型截面的竖直边的宽度窄。尽管在图中将第一连通柱110的柱体示出为矩形柱,但也可以是其他形状的柱体。
阻断注入区103的左右两侧的外侧面,例如通过形成缺口而与第二连通柱109相连接。第二连通柱109的掺杂类型为第一导电类型,用来连通源极金属电极106和源极注入区105。第二连通柱109仅与源极注入区105的一部分相连接。根据一种实施方式,第二连通柱109侧向和横向的宽度均窄于源极注入区105的侧向和横向的宽度,第二连通柱109与源极注入区105的远离栅极注入区104的L型截面的竖直边的位置对应。
根据本发明的实施方式,第二连通柱109的掺杂类型为第一导电类型,连通了源极金属电极106和源极注入区105,引入源极电流形成源极区。第一连通柱110的掺杂类型为第二导电类型,连通阻断注入区103和栅极注入区104。因阻断注入区103与栅极金属电极107相连,从而栅极注入区104与栅极金属电学性能上相通,可与阻断注入区103一同受到栅极电压的控制。即,通过第二连通柱109和第一连通柱110的连通作用,阻断注入区103和栅极注入区104可受到栅极金属电极107的控制,源极注入区105可受到源极金属电极106的控制。
该第一导电类型可以为N型或P型。第二导电类型为P型或N型。。根据一种实施方式,第一导电类型为N型,第二导电类型为P型。根据另一种实施方式,第一导电类型为P型,第二导电类型为N型。
在进行制作时,可首先在碳化硅衬底101上外延生长碳化硅外延层102,通过光刻窗口依次注入第二导电类型的栅极注入区104、第一导电类型的源极注入区105、第二导电类型的阻断注入区103、第二导电类型的第一连通柱110和第一导电类型的第二连通柱109。最后,分别沉积生长正面的栅极和源极金属,背面的漏极金属,并退火完成相应欧姆接触。
根据一种实施方式,如图4所示,栅极注入区104的竖直边的高度被设置为使得可以通过改变该栅极注入区的掺杂浓度而在未通电的情况下栅极注入区104的耗尽区和阻断注入区103的耗尽区之间能够形成沟道。在图4中,虚线表示器件开通时阻断注入区103和栅极注入区104的耗尽区,箭头则表示器件开通时载流子的运动方向,可观察到载流子从源极注入区105先倒流向上运动,后在碳化硅外延层102中向下运动,最终到达漏极金属电极108,实现导通。本实施例为常开型JFET,当栅极施加一定的反向电压时,阻断注入区103和栅极注入区104的耗尽区面积会相应的变大,直至夹断沟道,令器件关闭。
图5为依据本发明另一实施方式的碳化硅JFET结构在B-B'截面的结构示意图。如图5所示,栅极注入区104的竖直边的高度被设置为使得可以通过改变该栅极注入区104的掺杂浓度而在未通电的情况下栅极注入区104的耗尽区和阻断注入区103的耗尽区之间不形成沟道。图5所示的实施方式与图1至图4所示的实施方式相比,除BB’截面不同外,其他结构以及AA’截面与第一实施例一致,因此对相同的部分不予赘述。如图5所示,该实施方式只是更改了源极注入区104的注入形貌(掺杂位置与掺杂浓度),使阻断注入区103和栅极注入区104形成的耗尽区足够近,能够夹断沟道,从而保持器件为常闭型器件。当栅极施加一定的正向电压时,阻断注入区103和栅极注入区104的耗尽区面积则会变小,令沟道开通,器件开启。如此设置栅极注入区104的竖直边的高度能够提高产品合格率。
根据一种实施方式,栅极注入区104的竖直边的高度被设置为:使得可以通过改变该栅极注入区104的掺杂浓度,而既能在未通电的情况下栅极注入区104的耗尽区和阻断注入区103的耗尽区之间不形成沟道,也能在未通电的情况下栅极注入区104的耗尽区和阻断注入区103的耗尽区之间形成沟道。利用这样的实施方式,可以利用相同的工艺工具来实现常开型和常闭型的器件两者的生产,极大地节约成本。
根据一种实施方式,第一连通柱110的宽度大于第二连通柱109的宽度。根据一种实施方式,栅极注入区104的厚度大于源极注入区105的厚度。
本发明可通过调节注入区的掺杂浓度和位置来使器件成为常开型器件和常闭型器件。
应该注意,本发明的前后上下、横向、纵向等方向词,均是为了使本领域的技术人员更容易理解本发明而结合附图和上下文而设定的,并不一定是器件实际的位置和朝向。
应该理解的是,本发明的上述具体实施方式仅仅用于示例性说明或解释本发明的原理,而不构成对本发明的限制。因而,在不偏离本发明的精神和范围的情况下所做的任何修改、等同替换、改进等,均应包括在本发明的保护范围之内。此外,本发明的权利要求旨在涵盖落入权利要求范围和边界或者这种范围和边界的等同形式内的全部变型和改进。

Claims (9)

1.一种碳化硅结型场效应管,其特征在于,
所述碳化硅结型场效应管包括碳化硅衬底(101)、设置在所述碳化硅衬底(101)上的碳化硅外延层(102)、阻断注入区(103)、设置在所述碳化硅外延层(102)的左右两侧的两个栅极注入区(104)和两个源极注入区(105)、以及栅极金属电极(107)和源极金属电极(106),
所述栅极注入区(104)在正向截面为L型,包括竖直边和垂直边,在侧向沿整个碳化硅外延层(102)延伸,所述两个栅极注入区(104)的L型截面的竖直边相背对;
所述源极注入区(105)设置在对应的所述栅极注入区(104)的L型截面的横边上,所述源极注入区(105)沿整个碳化硅外延层(102)的侧向延伸,
所述阻断注入区(103)与所述两个栅极注入区(104)的L型截面的竖直边分别通过第一连通柱(110)相连接。
2.根据权利要求1所述的碳化硅结型场效应管,其特征在于,所述第一连通柱(110)为矩形柱,其横向的宽度与所述栅极注入区的所述竖直边的宽度一致,其侧向的宽度比所述竖直边的宽度窄。
3.根据权利要求1所述的碳化硅结型场效应管,其特征在于,所述碳化硅结型场效应管还包括绝缘层(111),所述绝缘层(111)使得所述源极金属电极(106)和所述栅极金属电极(107)之间实现电性能隔离。
4.根据权利要求1所述的碳化硅结型场效应管,其特征在于,所述碳化硅结型场效应管还包括第二连通柱(109),所述第二连通柱(109)用来连通所述源极金属电极(106)和所述源极注入区(105),所述第二连通柱(109)的横向宽度窄于所述源极注入区(105)的横向宽度,所述第二连通柱(109)的侧向宽度窄于所述源极注入区(105)的侧向宽度,所述第二连通柱(109)设置在所述源极注入区(105)的远离栅极注入区(104)的所述竖直边的位置。
5.根据权利要求4所述的碳化硅结型场效应管,其特征在于,所述第一连通柱(110)的横向宽度大于所述第二连通柱(109)的横向宽度。
6.根据权利要求5所述的碳化硅结型场效应管,其特征在于,所述栅极注入区(104)的厚度大于所述源极注入区(105)的厚度。
7.根据权利要求1所述的碳化硅结型场效应管,其特征在于,所述竖直边的高度被设置为使得可以通过改变所述栅极注入区(104)的掺杂浓度而在未通电的情况下,所述栅极注入区(104)的耗尽区和所述阻断注入区(103)的耗尽区之间能够形成沟道。
8.根据权利要求1或7所述的碳化硅结型场效应管,其特征在于,所述竖直边的高度被设置为使得可以通过改变所述栅极注入区(104)的掺杂浓度从而使在未通电的情况下所述栅极注入区(104)的耗尽区和所述阻断注入区(103)的耗尽区之间不形成沟道。
9.根据权利要求4所述的碳化硅结型场效应管,其特征在于,所述第二连通柱(109)和所述源极注入区(105)的掺杂类型为第一导电类型,所述第一连通柱(110)、所述阻断注入区(103)和所述栅极注入区(104)的掺杂类型为第二导电类型,所述碳化硅衬底(101)和碳化硅外延层(102)的掺杂类型为第一导电类型。
CN202011283253.6A 2020-11-17 2020-11-17 碳化硅结型场效应管 Pending CN114512533A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116936610A (zh) * 2023-09-18 2023-10-24 成都功成半导体有限公司 一种深掺杂碳化硅耐压jfet结构及其制备方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116936610A (zh) * 2023-09-18 2023-10-24 成都功成半导体有限公司 一种深掺杂碳化硅耐压jfet结构及其制备方法
CN116936610B (zh) * 2023-09-18 2023-12-01 成都功成半导体有限公司 一种深掺杂碳化硅耐压jfet结构及其制备方法

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