CN114448418B - Multiplex chip pin circuit and communication chip - Google Patents
Multiplex chip pin circuit and communication chip Download PDFInfo
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- CN114448418B CN114448418B CN202210357589.5A CN202210357589A CN114448418B CN 114448418 B CN114448418 B CN 114448418B CN 202210357589 A CN202210357589 A CN 202210357589A CN 114448418 B CN114448418 B CN 114448418B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/01759—Coupling arrangements; Interface arrangements with a bidirectional operation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018592—Coupling arrangements; Interface arrangements using field effect transistors only with a bidirectional operation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention provides a multiplexing chip pin circuit and a communication chip, wherein the multiplexing chip pin circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a diode, a capacitor and a control module; the control module comprises a first inverter, a second inverter, a third inverter, a NAND gate and a NOR gate; the chip pin bidirectional multiplexing end is used for connecting a chip pin which can be multiplexed as an external power supply voltage port or a communication signal output port, and the voltage value of the external power supply voltage is larger than that of the internal power supply voltage. Compared with the related technology, the technical scheme of the invention enables the chip pin to realize the multiplexing of the communication output chip pin and the high-voltage power supply chip pin, and when the high-voltage power supply chip pin is realized, the multiplexing chip pin circuit can be compatible with high voltage resistance and backflow prevention; when the communication output chip pin is realized, the high level output by the chip pin is lossless transmission of the internal power supply voltage.
Description
Technical Field
The invention relates to the technical field of circuits, in particular to a multiplexing chip pin circuit and a communication chip.
Background
At present, as the functions and applications of chips are more and more, the number of chip pins (IO) is more and more, and the multiplexing of chip pins is very important for the application of chips.
The related art communication chip has a large number of communication driving chip pins and high-voltage power supply chip pins.
However, in the communication driving chip pin among the chip pins of the related art, when the power supply voltage of the chip pin outputs a high level through the driving tube among the communication driving chip pins, there is a high level voltage loss. If multiplexing the communication drive chip pin as the high voltage power supply chip pin, then the circuit in the chip pin can't be high voltage resistant, because the voltage value of high voltage is greater than the mains voltage of chip pin for the circuit in the chip pin voltage backward flow phenomenon appears, the risk of chip function failure appears. Therefore, how to multiplex the communication driving chip pin and the high-voltage power supply chip pin is a technical problem to be solved.
Therefore, it is necessary to provide a new circuit and chip to solve the above problems.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a multiplexing circuit which enables a chip pin to realize multiplexing of a communication output chip pin and a high-voltage power supply chip pin, and when the high-voltage power supply chip pin is realized, a multiplexing chip pin circuit can be compatible with high voltage resistance and backflow prevention; when the communication output chip pin is realized, the high level output by the chip pin is a multiplexing chip pin circuit and a communication chip for lossless transmission of the internal power supply voltage.
In order to solve the above technical problem, in a first aspect, an embodiment of the present invention provides a multiplexing chip pin circuit, where the multiplexing chip pin circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a diode, a capacitor, and a control module;
the control module comprises a first inverter, a second inverter, a third inverter, a NAND gate and a NOR gate;
the input end of the first inverter is connected to the first input end of the NAND gate and is used for being connected to an enable signal, and the output end of the first inverter is respectively connected to the gate of the fourth transistor and the first input end of the NOR gate;
the input end of the second inverter is used for being connected to a communication signal, and the output end of the second inverter is connected to the second input end of the NAND gate;
the output end of the NAND gate is connected to the input end of the third inverter, and the output ends of the third inverter are respectively connected to the grid electrode of the third transistor and the second input end of the NOR gate;
a first end of the capacitor is respectively connected to a drain electrode of the fourth transistor, an output end of the diode, a grid electrode of the first transistor and a grid electrode of the second transistor; the source of the fourth transistor is connected to ground;
the output end of the NOR gate is connected to the second end of the capacitor;
an input terminal of the diode is connected to a drain of the first transistor and is used for being connected to an internal power supply voltage;
a source of the first transistor is connected to a source of the second transistor;
the drain electrode of the second transistor is connected to the drain electrode of the third transistor, and the drain electrode of the second transistor is used as a chip pin bidirectional multiplexing end;
a source of the third transistor is connected to ground;
the chip pin bidirectional multiplexing end is used for connecting a chip pin which can be multiplexed as an external power supply voltage port or a communication signal output port, and the voltage value of the external power supply voltage is greater than that of the internal power supply voltage.
Preferably, the first transistor, the second transistor, the third transistor, and the fourth transistor are all NMOS transistors.
Preferably, the enable signal is set to a low level, so that a chip pin connected with the chip pin bidirectional multiplexing terminal is used as an external power supply voltage port; the enabling signal is set to be in a high level, so that the chip pin connected with the chip pin bidirectional multiplexing terminal serves as a communication signal output port.
Preferably, the turn-on voltage of the diode is 0.7V, and the voltage value of the internal power supply voltage is greater than 1.4V.
In a second aspect, an embodiment of the present invention further provides a communication chip, which includes chip pins and the multiplexing chip pin circuit, which is connected to the chip pins, as provided in the embodiment of the present invention.
Compared with the prior art, the multiplexing chip pin circuit and the communication chip have the advantages that the first transistor, the second transistor and the third transistor are used as driving tubes, and the multiplexing of the communication output chip pin and the high-voltage power supply chip pin is realized through the matching control of the driving module and the fourth transistor. Specifically, when the chip pin can realize the high-voltage power supply chip pin, the first transistor, the second transistor and the third transistor are all cut off through the cooperation control of the driving module and the fourth transistor, so that the voltage influence and the backward flow of the high voltage at the chip pin on the multiplexing chip pin circuit are prevented, the multiplexing chip pin circuit is compatible, high-voltage resistance and backward flow prevention are realized, and the chip pin is used as the high-voltage power supply chip pin. And when the chip pin can realize the communication output chip pin, the connection is realized through the diode and the capacitor, the capacitor forms a bootstrap capacitor through the cooperation of the driving module and the fourth transistor, so that the first transistor and the second transistor transmit high level, the high level output by the chip pin is simultaneously the lossless transmission of the internal power voltage, the driving module controls the third transistor to realize the transmission of low level, the communication transmission function is implemented, and the chip pin is used as the communication output chip pin.
Drawings
The present invention will be described in detail below with reference to the accompanying drawings. The foregoing and other aspects of the invention will become more apparent and more readily appreciated from the following detailed description, taken in conjunction with the accompanying drawings. In the drawings:
FIG. 1 is a circuit diagram of the multiplexing chip pin circuit of the present invention;
FIG. 2 is a schematic diagram of a circuit application of the multiplexing chip pin circuit of the present invention;
FIG. 3 is a schematic diagram of another circuit application of the multiplexing chip pin circuit of the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings.
The embodiments/examples described herein are specific embodiments of the present invention, are intended to be illustrative of the concepts of the present invention, are intended to be illustrative and exemplary, and should not be construed as limiting the embodiments and scope of the invention. In addition to the embodiments described herein, those skilled in the art will be able to employ other technical solutions which are obvious based on the disclosure of the claims and the specification of the present application, and these technical solutions include those which make any obvious replacement or modification of the embodiments described herein, and all of which are within the scope of the present invention.
The present invention provides a multiplexing chip pin circuit 100.
Referring to fig. 1-3, fig. 1 is a circuit diagram of a multiplexing chip pin circuit 100 according to the present invention.
The multiplexing chip pin circuit 100 is connected to a chip pin 10. The multiplexing chip pin circuit 100 enables multiplexing of the communication output chip pin and the high voltage power supply chip pin by the chip pin 10.
In this embodiment, the power supply voltage when the internal circuit of the multiplexing chip pin circuit 100 operates is the internal power supply voltage VDD. When the chip pin 10 is used as a high voltage power supply chip pin, the chip pin 10 serves as an external power supply voltage port, wherein the external power supply voltage is VCC. The voltage value of the external power supply voltage VCC is greater than that of the internal power supply voltage VDD, namely, the external power supply voltage VCC corresponds to the internal power supply voltage VDD which is a high voltage.
The multiplexing chip pin circuit 100 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a diode, a capacitor C1, and a control module U1.
In this embodiment, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all NMOS transistors. The first transistor M1, the second transistor M2, and the third transistor M3 are used as driving transistors of the multiplexing chip pin circuit 100.
The control module U1 includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a NAND gate NAND1, and a NOR gate NOR 1.
The circuit connection relationship of the multiplexing chip pin circuit 100 is as follows:
an input end of the first inverter INV1 is connected to a first input end of the NAND gate NAND1 and is configured to be connected to the enable signal EN, and an output end of the first inverter INV1 is connected to a gate of the fourth transistor M4 and a first input end of the NOR gate NOR1, respectively.
An input of the second inverter INV2 is configured to be connected to the communication signal DATAIN, and an output of the second inverter INV2 is connected to a second input of the NAND gate NAND 1.
An output end of the NAND gate NAND1 is connected to an input end of the third inverter INV3, and output ends of the third inverter INV3 are connected to a gate of the third transistor M3 and a second input end of the NOR gate NOR1, respectively.
A first end of the capacitor C1 is connected to the drain of the fourth transistor M4, the output end of the diode, the gate of the first transistor M1 and the gate of the second transistor M2, respectively. The source of the fourth transistor M4 is connected to ground GND.
The output terminal of the NOR gate NOR1 is connected to the second terminal of the capacitor C1.
The input terminal of the diode is connected to the drain of the first transistor M1 and is used for connection to the internal supply voltage VDD.
The source of the first transistor M1 is connected to the source of the second transistor M2.
The drain of the second transistor M2 is connected to the drain of the third transistor M3. And the drain of the second transistor M2 is used as a chip pin bidirectional multiplexing terminal VIO.
The source of the third transistor M3 is connected to ground GND.
The chip pin bidirectional multiplexing end VIO is used for connecting a chip pin 10 which can be multiplexed as an external power supply voltage port or a communication signal output port.
When the chip pin bidirectional multiplexing terminal VIO is used for connecting the chip pin 10 serving as an external power supply voltage port, the enable signal EN is set to be at a low level. When the chip pin bidirectional multiplexing end VIO is used for connecting the chip pin 10 serving as a communication signal output port, the enable signal EN is set to be at a high level. That is, the enable signal is set to a low level so that the chip pin 10 connected to the chip pin bidirectional multiplexing terminal VIO serves as an external power supply voltage port. The enable signal is set to a high level so that the chip pin 10 connected to the chip pin bidirectional multiplexing terminal VIO serves as a communication signal output port.
The data transmitted by the communication signal DATAIN are a digital signal "1" and a digital signal "0", i.e., high and low levels represent data.
In this embodiment, the on voltage of the diode is 0.7V, and the voltage value of the internal power supply voltage VDD is greater than 1.4V. The voltage value of the internal power voltage VDD greater than 1.4V may satisfy that the first transistor M1 and the second transistor M2 realize lossless transfer of the internal power voltage VDD when turned on. For specific reasons, reference is made to the following description.
The working principle of the multiplexing chip pin circuit 100 is as follows:
(1) referring to fig. 2, when the chip pin 10 is used as a communication signal output port, the enable signal EN is set to a high level. At this time, the voltage of the Y1 node of the output end of the first inverter INV1 is at low level, and the fourth transistor M4 is turned off. The operating state of the multiplexing chip pin circuit 100 is controlled by the communication signal DATAIN. The method specifically comprises the following steps:
when the data transmitted by the communication signal DATAIN is a digital signal "0", that is, the communication signal DATAIN is at 0V level, the circuit logic of the control module U1 determines that: the Y2 node voltage of the output terminal of the NOR gate NOR1 is at 0V level, and the Y3 node voltage is at high level. The voltage at the node Y3 is high, so that the third transistor M3 is turned on, and the voltage at the drain of the third transistor M3 is pulled down to 0V of the ground GND, thereby implementing the pull-down 0V of the chip pin bidirectional multiplexing terminal VIO, and the process transmits the data transmitted by the communication signal DATAIN as a digital signal "0" to the chip pin bidirectional multiplexing terminal VIO and then outputs the digital signal "0" to the chip pin 10. Meanwhile, since the voltage at the node Y2 is at 0V level, the second terminal of the capacitor C1 is also pulled to 0V level, and the first terminal of the capacitor C1 is charged to VDD-0.7V by the internal power voltage VDD through the diode D1.
When the data transmitted by the communication signal DATAIN is a digital signal "1", that is, when the communication signal DATAIN is at a high level, the circuit logic of the control module U1 determines that: the Y2 node voltage at the output of the NOR gate NOR1 is high, and the Y3 node voltage is 0V level. The Y3 node voltage is at 0V level so that the third transistor M3 is turned off. The voltage at the node Y2 is high, so that the second terminal of the capacitor C1 is pulled up from 0V to the internal power voltage VDD, and the capacitor C1 is a bootstrap capacitor, so that the first terminal of the capacitor C1 is boosted up to 2 × VDD-0.7V by the internal power voltage VDD, thereby turning on both the first transistor M1 and the second transistor M2. Although there is a loss of threshold voltage when the first transistor M1 and the second transistor M2 are turned on as NMOS transistors, the voltage of the gates of the first transistor M1 and the second transistor M2 are already pumped to a voltage value of 2 × VDD-0.7V, so long as the voltage of the gates of the first transistor M1 and the second transistor M2 is guaranteed to be boosted to 2 × VDD-1.4V > VDD, that is, VDD >1.4V, so that lossless transmission of the high level of the chip pin bidirectional multiplexing terminal VIO equal to VDD can be realized. In this embodiment, the turn-on threshold voltage VTH of the transistor is also 0.7V. When transmitting high level, if the drain voltage of the second transistor M2 is equal to VDD, the gate voltage of the second transistor M2 is equal to or greater than VDD +0.7V, and the gate of the second transistor M2 is pumped to 2 x VDD-0.7V through the capacitor C1, so the voltage relationship needs to be satisfied: 2 VDD-0.7V > VDD +0.7V, i.e. VDD > 1.4V.
The above-described operation causes the multiplexing chip pin circuit 100 to implement a communication transmission function, thereby causing the chip pin 10 to be used as a communication output chip pin.
(2) Referring to fig. 3, the chip pin 10 is used as an external power voltage port, that is, the chip pin 10 is used as a high voltage power chip pin. The enable signal EN is set to a low level. I.e. the enable signal EN is set to the digital signal "0".
The chip pin 10 is connected to an external supply voltage VCC. The external power supply voltage VCC is connected to the high voltage operating circuit 20 inside the chip through an internal power supply line after passing through the chip pin 10, and is used as a power supply voltage for the circuit operation of the high voltage operating circuit 20.
The enable signal EN is a digital signal "0", and the voltage of the Y1 node becomes a high level after passing through the first inverter INV 1. The high level of the node Y1 turns on the fourth transistor M4, which pulls the voltage at the drain of the fourth transistor M4 low to 0V at ground GND. The 0V voltage causes the gate of the first transistor M1 and the gate of the second transistor M2 to be brought to the 0V voltage as well, while the first transistor M1 and the second transistor M2 are both in an off state. In another circuit in the control module U1, the enable signal EN is a digital signal "0" and passes through the NAND gate NAND1 and the third inverter INV3 in sequence, so that the voltage at the Y3 node becomes 0V, the gate input of the third transistor M3 is also pulled to 0V, and the third transistor M3 is also in an off state. This ensures that leakage between the circuit and the internal supply voltage VDD and ground GND is avoided after the external supply voltage VCC has passed through the chip pin 10. Thereby preventing the high voltage at the chip pin 10 from influencing and flowing backward the voltage of the multiplexing chip pin circuit 100, realizing that the multiplexing chip pin circuit 100 can be compatible with high voltage resistance and prevent flowing backward, and further enabling the chip pin 10 to be used as a high-voltage power supply chip pin.
It should be noted that the transistors, diodes, capacitors, inverters, nand gates, nor gates, or devices commonly used in the art are adopted in this embodiment, and the user selects the model and parameter performance according to the designed index, which is not described in detail herein.
The invention also provides a communication chip. The communication chip comprises chip pins 10 and the multiplexing chip pin circuit 100 connected to the chip pins.
Compared with the prior art, the multiplexing chip pin circuit and the communication chip have the advantages that the first transistor, the second transistor and the third transistor are used as driving tubes, and the multiplexing of the communication output chip pin and the high-voltage power supply chip pin is realized through the matching control of the driving module and the fourth transistor. Specifically, when the chip pin can realize the high-voltage power supply chip pin, the first transistor, the second transistor and the third transistor are all cut off through the cooperation control of the driving module and the fourth transistor, so that the voltage influence and the backward flow of the high voltage at the chip pin on the multiplexing chip pin circuit are prevented, the multiplexing chip pin circuit is compatible, high-voltage resistance and backward flow prevention are realized, and the chip pin is used as the high-voltage power supply chip pin. And when the chip pin can realize the communication output chip pin, the connection is realized through the diode and the capacitor, the capacitor forms a bootstrap capacitor through the cooperation of the driving module and the fourth transistor, so that the first transistor and the second transistor transmit high level, the high level output by the chip pin is simultaneously the lossless transmission of the internal power voltage, the driving module controls the third transistor to realize the transmission of low level, the communication transmission function is implemented, and the chip pin is used as the communication output chip pin.
It should be noted that the above-mentioned embodiments described with reference to the drawings are only intended to illustrate the present invention and not to limit the scope of the present invention, and it should be understood by those skilled in the art that modifications and equivalent substitutions can be made without departing from the spirit and scope of the present invention. Furthermore, unless the context indicates otherwise, words that appear in the singular include the plural and vice versa. Additionally, all or a portion of any embodiment may be utilized with all or a portion of any other embodiment, unless stated otherwise.
Claims (5)
1. A multiplexing chip pin circuit is characterized by comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a diode, a capacitor and a control module;
the control module comprises a first inverter, a second inverter, a third inverter, a NAND gate and a NOR gate;
the input end of the first inverter is connected to the first input end of the NAND gate and is used for being connected to an enable signal, and the output end of the first inverter is respectively connected to the gate of the fourth transistor and the first input end of the NOR gate;
the input end of the second inverter is used for being connected to a communication signal, and the output end of the second inverter is connected to the second input end of the NAND gate;
the output end of the NAND gate is connected to the input end of the third inverter, and the output ends of the third inverter are respectively connected to the grid electrode of the third transistor and the second input end of the NOR gate;
a first end of the capacitor is connected to a drain electrode of the fourth transistor, an output end of the diode, a grid electrode of the first transistor and a grid electrode of the second transistor respectively; a source of the fourth transistor is connected to ground;
the output end of the NOR gate is connected to the second end of the capacitor;
an input terminal of the diode is connected to a drain of the first transistor and is used for being connected to an internal power supply voltage;
a source of the first transistor is connected to a source of the second transistor;
the drain electrode of the second transistor is connected to the drain electrode of the third transistor, and the drain electrode of the second transistor is used as a chip pin bidirectional multiplexing end;
a source of the third transistor is connected to ground;
the chip pin bidirectional multiplexing end is used for connecting a chip pin which can be multiplexed as an external power supply voltage port or a communication signal output port, and the voltage value of the external power supply voltage is greater than that of the internal power supply voltage.
2. The multiplexing chip pin circuit of claim 1, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are all NMOS transistors.
3. The multiplexing chip pin circuit according to claim 1, wherein the enable signal is set to a low level to make the chip pin connected to the chip pin bidirectional multiplexing terminal as an external power supply voltage port; the enabling signal is set to be in a high level, so that the chip pin connected with the chip pin bidirectional multiplexing terminal serves as a communication signal output port.
4. The multiplexing chip pin circuit of claim 1 wherein the turn-on voltage of the diode is 0.7V and the voltage value of the internal supply voltage is greater than 1.4V.
5. A communication chip comprising chip pins and a multiplexed chip pin circuit according to any of claims 1 to 4 connected to the chip pins.
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| CN202210357589.5A CN114448418B (en) | 2022-04-07 | 2022-04-07 | Multiplex chip pin circuit and communication chip |
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| CN202210357589.5A CN114448418B (en) | 2022-04-07 | 2022-04-07 | Multiplex chip pin circuit and communication chip |
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| CN116165510B (en) * | 2022-12-29 | 2023-11-24 | 无锡晟朗微电子有限公司 | Communication device for chip test |
| CN117176134B (en) * | 2023-08-30 | 2024-07-23 | 北京中科格励微科技有限公司 | Repair and adjustment circuit and repair and adjustment method for multiplexing pins |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6087852A (en) * | 1997-12-19 | 2000-07-11 | Texas Instruments Incorporated | Multiplexing a single output node with multiple output circuits with varying output voltages |
| CN103066985A (en) * | 2012-12-06 | 2013-04-24 | 无锡中星微电子有限公司 | Chip provided with multiplex pin |
| US9444461B1 (en) * | 2015-04-02 | 2016-09-13 | Microsemi Semiconductor Ulc | Universal input buffer |
| US10756737B1 (en) * | 2019-09-24 | 2020-08-25 | Nanya Technology Corporation | Off chip driver circuit, off chip driver compensation system and signal compensation method |
| CN113659978A (en) * | 2021-08-26 | 2021-11-16 | 上海芯圣电子股份有限公司 | Multiplexing circuit of VPP port and VPP port reusable chip |
-
2022
- 2022-04-07 CN CN202210357589.5A patent/CN114448418B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6087852A (en) * | 1997-12-19 | 2000-07-11 | Texas Instruments Incorporated | Multiplexing a single output node with multiple output circuits with varying output voltages |
| CN103066985A (en) * | 2012-12-06 | 2013-04-24 | 无锡中星微电子有限公司 | Chip provided with multiplex pin |
| US9444461B1 (en) * | 2015-04-02 | 2016-09-13 | Microsemi Semiconductor Ulc | Universal input buffer |
| US10756737B1 (en) * | 2019-09-24 | 2020-08-25 | Nanya Technology Corporation | Off chip driver circuit, off chip driver compensation system and signal compensation method |
| CN113659978A (en) * | 2021-08-26 | 2021-11-16 | 上海芯圣电子股份有限公司 | Multiplexing circuit of VPP port and VPP port reusable chip |
Non-Patent Citations (1)
| Title |
|---|
| E/D PMOS中的几种电路结构介绍;朱玮等;《微电子技术》;20020425(第02期);第211-214页 * |
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