CN114444640A - 具有被焊电子元件的芯片卡模块的制造工艺 - Google Patents

具有被焊电子元件的芯片卡模块的制造工艺 Download PDF

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Publication number
CN114444640A
CN114444640A CN202111274137.2A CN202111274137A CN114444640A CN 114444640 A CN114444640 A CN 114444640A CN 202111274137 A CN202111274137 A CN 202111274137A CN 114444640 A CN114444640 A CN 114444640A
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solder
substrate
layer
chip card
conductive material
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CN202111274137.2A
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克里斯托夫·马蒂厄
纪尧姆·金伯特
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Linxens Holding SAS
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Linxens Holding SAS
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Publication of CN114444640A publication Critical patent/CN114444640A/zh
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/0716—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips at least one of the integrated circuit chips comprising a sensor or an interface to a sensor
    • G06K19/0718—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips at least one of the integrated circuit chips comprising a sensor or an interface to a sensor the sensor being of the biometric kind, e.g. fingerprint sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/072—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising a plurality of integrated circuit chips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/0723—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/0772—Physical layout of the record carrier
    • G06K19/07722—Physical layout of the record carrier the record carrier being multilayered, e.g. laminated sheets
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • G06K19/07747—Mounting details of integrated circuit chips at least one of the integrated circuit chips being mounted as a module
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
    • G06K19/07754—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna the connection being galvanic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07766—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card comprising at least a second communication arrangement in addition to a first non-contact communication arrangement
    • G06K19/07769—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card comprising at least a second communication arrangement in addition to a first non-contact communication arrangement the further communication means being a galvanic interface, e.g. hybrid or mixed smart cards having a contact and a non-contact interface
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/36—Electric or electronic devices
    • B23K2101/40—Semiconductor devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B23K35/262—Sn as the principal constituent
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C13/00—Alloys based on tin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/13099—Material
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    • H01L2224/132—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13201—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13211—Tin [Sn] as principal constituent
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
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    • H01L2224/132—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13201—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13213—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
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    • H01L2224/132—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13238—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13239—Silver [Ag] as principal constituent
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
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    • H01L2224/132—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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Abstract

本发明涉及芯片卡模块的制造工艺。该工艺包括一个或多个操作，其中将可熔焊料沉积在连接片上，该连接片形成于位于介电基板背面上的导电材料层，并且通过回流焊料将至少一个电子元件连接至这些连接片。使用该工艺获得的芯片卡模块。本发明还涉及包括该模块的芯片卡。

Description

具有被焊电子元件的芯片卡模块的制造工艺
技术领域
本发明涉及芯片卡领域。
背景技术
芯片卡通常由塑料卡体形成，其中容纳有包括芯片的模块，该芯片即集成电路，并且该芯片被电连接至接触件和/或天线以便与读卡器接触式通信或非接触式通信。除了天线和包括芯片的模块之外，其他电路部件和/或其他电子元件可以被集成到卡体内。当用于读取指纹的生物识别传感器被用于提高安全性或简化芯片卡的使用时，尤其如此。
然而，将电子元件集成到芯片卡体内可能会在卡体的各个组成层的层压过程中产生问题。具体而言，可能遇到的问题包括例如在层压过程中部件的劣化、由于在层之间插入一个或多个元件可能导致的影响美观的隆起，以及在层压后旨在用于电子元件连接的连接区位置的不精确。
一个解决方案在于将至少某些元件集成到已经包括芯片或旨在容纳芯片的模块中(例如，可以参考文件US2019294943A1、CA2503688A1和US2019340398A1中的在模块上有多个部件的芯片卡的示例)。具体而言，在层压卡的组成层之后，该模块被容纳在腔体中，该腔体通常通过铣削形成于卡体内。因此，部件不经受例如层压操作。
本发明针对该背景并且旨在至少部分地改进芯片卡模块的制造工艺，除了通常由该模块承载的芯片之外，该芯片卡模块还包括其他元件。
发明内容
因此，根据本发明，提供用于芯片卡的模块的制造工艺，该制造工艺包括以下操作：
-提供介电基板，该介电基板在该基板的第一主面上承载第一导电材料层，以及在该基板的第二主面上承载第二导电材料层，以及
-在该基板第一主面一侧，将集成电路固定至该基板，并且将该集成电路连接至第一连接片。
该工艺还包括一个或多个操作，其中将可熔焊料沉积在形成于第一导电材料层中的第二连接片上，并且通过回流预先沉积在第二连接片上的焊料而将至少一个电子元件连接至第二连接片。
因此，凭借本发明，可以在芯片卡模块的制造中使用可能对层压操作敏感的电子元件。可以使用引线键合或芯片倒装技术来连接集成电路。当使用芯片倒装技术连接芯片时，可以使用导电膏进行连接，或者甚至可以使用可熔焊料及回流该可熔焊料的操作(可选地，使用与允许一个或多个其他电子元件被连接的操作相同的操作)进行连接。当使用引线键合连接芯片时，两种连接技术，即引线键合和回流焊接，在给定的载体上的共同应用，不是本领域技术人员的惯常操作，本领域技术人员认为引线键合之前的回流步骤易对旨在用于引线键合的连接片造成污染，或者相反地，如果先使用引线键合连接芯片，那么回流温度可能会使芯片劣化。
用于芯片卡模块的该制造工艺可选地包括以下特征中的一个或多个，每个特征相互独立地考虑，或者每个特征与一个或多个其他特征组合考虑：
-其包括在回流焊料之前在基板的第一主面上沉积焊料掩模的操作；
-在将集成电路连接至第一连接片的操作之前，执行回流焊料的操作；或者，在将集成电路连接至第一连接片的操作之后，执行回流焊料的操作；
-使用导线将集成电路连接至第一连接片；
-焊料的熔点在130℃和250℃之间；
-使用从以下列表中选择的技术沉积焊料：喷射、接触分配、引脚转移和丝网印刷；
-其包括在集成电路和将该集成电路连接至第一连接片的导线上沉积封装材料的操作，而该封装材料不覆盖电子元件。
根据另一方面，本发明涉及一种芯片卡模块，其包括介电基板，该介电基板在该基板的第一主面上承载有第一导电材料层，在该基板的第二主面上承载有第二导电材料层，在该基板的第一主面一侧上承载有牢固地固定于该基板且可选地使用导线连接至第一连接片的集成电路。该模块还包括至少一个可焊电子元件，使用在焊料连接的第二片上沉积并回流的可熔焊料将该至少一个可焊电子元件连接于形成于第一导电材料层中的第二连接片。
该芯片卡模块可选地包括以下特征中的一个和/或另一个，每个特征相互独立地考虑，或者每个特征与一个或多个其他特征组合考虑：
-电子元件是无源元件；
-焊料为合金，该合金可以是包括以下列出的至少两种元素的合金：铋、锡、银和铜；
-封装材料围绕集成电路而不覆盖电子元件。
根据另一方面，本发明涉及一种芯片卡，该芯片卡包括卡体和腔体，在该腔体中容纳使用根据本发明的工艺制造的模块。
附图说明
本发明的其他方面、目的和优点将通过阅读以下详细描述并参考通过非限制性示例的方式给出的附图而变得明显易懂，其中：
[图1]示意性地示出芯片卡的一个示例的透视图。
[图2]示意性地示出诸如图1中所示的芯片卡的电路和元件的布置示例。
[图3]示意性地示出对应根据本发明的模块实施例的示例的印刷电路板的一部分的正视图。
[图4]示意性地示出对应图3中所示模块实施例的示例的印刷电路板的一部分的后视图；
[图5]示意性地示出图4的细节；
[图6]示意性地示出根据本发明的芯片卡模块的制造工艺的示例的各个步骤。
具体实施方式
根据本发明的芯片卡1的一个示例在图1中示出。在该示例中，芯片卡1是ID-1规格的银行卡。该芯片卡1包括具有连接器3和第二模块4的第一模块2。例如，第一模块2是符合ISO7810标准的EMV(EuroPay、MasterCard、Visa)模块。连接器3允许安装在第一模块2上的电子芯片5(见图6)电连接于读卡器，以便在芯片5和读卡器之间交换数据。
在双界面芯片卡1的情况下，即能够以接触式读取或非接触式读取的芯片卡，天线被集成于芯片卡1的本体6中。该天线被连接至例如位于第一模块2中的芯片。该天线允许在芯片5和非接触式读卡器之间非接触地交换数据。该天线或位于卡体6中的电路的另一部分也可以被电连接至集成到芯片卡1中的第二模块4。第二模块4是例如生物识别模块。该第二模块4则包括例如用于识别指纹的生物识别传感器。第二模块4可以确定由例如生物识别传感器读取的指纹是否与被授权使用该芯片卡1的用户的指纹对应。在该情况下，芯片5和读取器之间的非接触式通信可以被允许。其他部件(例如发光二极管)可选地被容纳在卡体6中。
如图2所示，第一模块2和第二模块4通过电路进行通信，该电路在使用介电载体形成的嵌入件上制成。该电路可以使用嵌入介电载体中的一根或多根导线形成，或者实际上使用与介电载体层压的导电材料层中所蚀刻的导电迹线形成，或者在将导电材料层层压至介电载体之前，使用从该导电材料层切割制成的导电迹线形成。然后将嵌入件及其电路与各塑料层(一层或多层补偿层、一层或多层终饰层、一层或多层印刷层等)层压以形成卡体6。在现有技术中，腔体通过在卡体6中铣削制成。第一模块2和第二模块4被集成到这些腔体中，在这些腔体中，第一模块2和第二模块4被连接至先前并入到卡体6内的电路。
本发明的一个优点是它允许优选地不放置在卡体6中的一个或多个电子元件7共同成组于第一模块2中。为此，第一模块2以特定的方式制造。
图3至图5示出印刷电路板8的一部分。该部分对应印刷电路板8的旨在形成模块的区域，而印刷电路板8包括许多与这些图中所示区域相同或相似的区域。这些区域在印刷电路板条带的宽度上以给定的间距重复，并且可选地在该印刷电路板条带的长度上以另一间距重复。使用下面描述的示例之一的工艺对条带连续地进行卷对卷处理。
第一模块2包括介电载体或基板9。该介电基板9具有两个主面：被称为“背面”或“接合面”的第一面以及被称为“正面”或“接触面”的第二面11。使用下述工艺在第一面10和第二面11的每一者上制成导电盘12。在第二面11(正面)上，导电盘12基本上对应于旨在通过与读卡器的接触建立临时通信的接触件13。在第一面10(背面)上，导电盘12对应于迹线14和连接片15、连接片16。连接片15、连接片16用于连接芯片5和被固定于第一面10的一个或多个电子元件7。一些第一连接片15被用于使用导电连接线17(见图6)将芯片5连接于导电迹线14的连接。一些第二连接片16被用于将一个或多个电子元件7焊接于导电迹线14的连接。此外，导电迹线14将第一连接片15和第二连接片16电连接于连接盘19，连接盘19旨在将第一模块2连接至集成到卡体6内的电路，或者导电迹线14将第一连接片15和第二连接片16电连接至连接井18，连接井18允许通过基板9与接触件13建立连接。
如图4和图5中所示，焊料掩模20被放置在第二连接片16周围。焊料掩模被沉积在基板9上。焊料掩模部分地覆盖连接于第二连接片16的导电迹线14，但不覆盖第二连接片16。在NSMD(NSMD代表非焊料掩模限定)设置中，在第二连接片16周围，在第二连接片16和焊料掩模20之间，留有宽度在例如50微米和200微米之间的空间。在SMD(SMD代表焊料掩模限定)设置中，宽度为例如50微米和200微米之间的重叠区覆盖第二连接片16。
已知在SMT工艺(SMT代表表面贴装技术)的实施过程中，在旨在将元件的端子焊接至印刷电路板片的回流操作期间可能会发生不良效应。这种被称为墓碑效应或曼哈顿效应，甚至芯片吊升的不良效应，导致部件转动远离印刷电路板平面。转动后的部件的一个端子可能通过焊料连接，但另一端子无连接(处于回流焊料之外)。图5示出在第二连接片16附近的一部分印刷电路板。这些连接片16具有长度X、宽度Y，并且被间隔开距离S。
发明人已观察到，对于0201型号的元件(根据EIAJ国际标准的元件型号编码规格：以长度和宽度以百分之一英寸为单位，编码的前2位或3位数字代表元件长度，后2位数字代表元件宽度。因此，对于0201元件，其尺寸为：元件长度为0.6±0.03毫米，元件宽度为0.3±0.03毫米，并且平行于长度的待焊端子的尺寸为0.15±0.05毫米)，当X值等于400微米，Y值等于400微米，并且距离S等于400微米时，在超过10％的情况下会出现墓碑效应。相反地，发明人还发现，对于0201型号的元件，如果X等于400±50微米，Y等于300±50微米，并且S等于300±50微米，则墓碑效应仅在不到1％的情况下发生。因此，在本文中描述的实施例的示例中有益地采用了X、Y和S的前述值。更一般地，如果连接片16之间的距离S小于、等于或接近对应部件长度减去平行于长度的待焊端子尺寸的两倍后所得差值，则墓碑效应减弱。换言之，电子元件7具有两个纵向端部及在每个纵向端部处的待焊端子，并且端子之间的距离大于、等于或接近相应的连接片16之间的距离S。更通用的元件尺寸如下所示。可选地，X、Y和S的值可被改变，这是鉴于一方面，如果距离S减小，则元件更多地靠置于回流焊料上，并且另一方面，如果连接片16的面积减小，则趋向于使元件转动远离的力减弱。这两种效应中的一者或两者均限制墓碑效应的出现频率。
下面参考图6描述第一模块2的实施例的一个示例的制造工艺的示例。
该工艺包括提供复合材料100，复合材料100包括由介电材料制成的基板9，由第一导电材料制成的第一层21或箔被层压于该基板(参见图6a)。例如，基板9的介电材料为聚酰亚胺或环氧玻璃复合材料，其厚度在25微米和100微米之间，优选地等于100微米，并且第一导电材料层21由铜或铜合金制成，其厚度在12微米和70微米之间，优选地等于35微米。
为使根据本发明的工艺实施具备工业上的高性能，该复合材料100有益地以料卷的形式提供并且以卷对卷的形式实施该工艺。复合材料100可以以覆层的形式提供，例如覆铜。或者，它可以以多层复合件(未示出)的形式提供，该多层复合件包括介电基板9、第一导电材料层21及在该介电基板和该第一导电材料层之间的粘合材料层(例如环氧树脂)。粘合材料具有例如10微米和25微米之间的厚度。该多层复合件100经过层压加工。粘合材料可能须经连续的干燥操作，以便在沉积时去除制剂中存在的溶剂。因此，粘合材料层允许将第一导电材料层固定至介电基板9的第一面10。层压之后可以是热固化粘合材料的操作。使用分层复合材料(在基板的第一主面10和第一导电材料层21之间没有粘合层)是优选的，因为它可能会避免在下面描述的回流操作期间与粘合剂流动相关的问题的产生，并且因为它可以避免在将芯片5连接至连接片的操作期间与连接线17的粘合相关的问题的产生。
有益地，该工艺还包括一个步骤(未示出)，其中将一个粘合材料层(该层与潜在已沉积的层不同，如上所述)沉积在基板9的第二主面11上，该粘合材料层具有例如10微米和25微米之间的厚度。该层粘合材料(例如环氧树脂)也可能经过连续干燥操作，以便在沉积时去除制剂中存在的溶剂。
因此，复合材料100有益地包括介电基板9，介电基板9在其第一主面10上承载有第一导电材料层21并且在其第二主面11上承载有粘合材料层。如此形成的复合材料100随后经过穿孔步骤(该步骤有益地是通过机械加工方式实施，但也可以可选地通过激光切割实施)以形成连接井18(见图6b)和驱动孔22(见图3和图4)。连接井18和驱动孔22直接穿过复合材料100(基板9、第一导电材料层21、基板和第一导电材料层21之间的可选粘合材料层以及另一粘合材料层)。
如此穿孔的复合材料100经过与第二导电材料层23的层压操作。该第二导电材料层23封闭至少某些连接井18以形成盲孔(见图6c)。
然后进行光刻操作，以允许在第一主面10上制成有连接片15、连接片16和连接迹线14，并在第二主面11上制成有接触件13。这些步骤包括将例如光刻干胶膜层压至覆盖基板9的第一主面10的第一导电材料层21和覆盖基板9的第二主面11的第二导电材料层23的操作，以及通过掩模曝光这些光刻胶膜、显影光刻胶和蚀刻第一导电材料层21和第二导电材料层23的某些区域的步骤，以形成连接片15、连接片16、连接迹线14或任何其他图案。
或者，在将连接片15、连接片16和连接迹线14层压至介电基板9的第一主面10之前，通过切割或蚀刻第一导电材料层21(引线框架技术)制成连接片15、连接片16和连接迹线14。
电沉积金属层24(例如铜、镍、金、钯、银或它们的合金)的步骤有益地在基板9的第一主面10和第二主面11中的两者或一者上进行。这些沉积旨在便于将例如连接线17焊接至连接片15、连接片16。
然后在旨在接收焊料25的第二连接片16周围沉积焊料掩模20(见图6e和图6f)。有益地，焊料掩模20由可光成像的环氧树脂材料制成。这更精确地允许，特别是卷到卷地，制成围绕第二连接片16的图案。焊料掩模20具有13微米和58微米之间的厚度，并且优选地等于38微米的厚度。
随后是将焊料25沉积在由焊料掩模20围绕并且旨在连接至电子元件7的第二连接片16上的操作(参见图6f和图6g)。例如，焊料25由被称为“SAC305”的锡(96.5％)、银(3％)和铜(0.5％)的合金组成，其熔点约为220℃。该沉积焊料25的步骤通过例如接触分配或通过喷射或通过丝网印刷或通过引脚转移来执行。对于尺寸较小的电子元件7的，通过喷射或接触分配进行沉积是有益的，因为焊料25的液滴尺寸必须足够小以便能够放置部件且可靠地放置部件。例如，对于0201或01005规格的元件的放置，希望焊料25的液滴直径不超过200微米，这通过喷射或接触分配比使用丝网印刷更容易实现。
然后将一个或多个电子元件7放置在已预先沉积有焊料25的液滴的第二连接片16上(见图6g)。一个或多个电子元件7是例如无源元件。更具体地，电子元件7可能涉及电容器，该电容器允许卡体6中存在的并且连接至第一模块2的天线电路的电容匹配。例如，该电子元件7具有基本上平行六面体的形状，其总长度在0.4毫米和1.0毫米之间，宽度在0.2毫米和0.5毫米之间，并且高度在0.2毫米和0.5毫米之间。在这些平行六面体的每个纵向端部形成有导电端子，该导电端子在电子元件7的整个宽度和整个高度上以及在对应这些电子元件7的长度的尺寸的一部分上延伸。这些电子元件7被使用拾放技术(pick-and-placetechnique)放置在第二连接片16上。实施这些可焊电子元件7的成本通常低于实施使用导线连接的电子元件7的成本。在图4中，已经示出连接片15的两个区26、27。在第一区26中，已经制成有两个连接片15，以便在其间连接一个电子元件7。在第二区27中，已经制成有四个连接片15，以便连接两个电子元件7。因此，可以根据需要连接可变数量的电子元件7。
接下来，预先获得的电路经受具有250℃峰值的温度曲线的回流，以便回流在第二连接片16上沉积的焊料25的液滴。焊料掩模20允许在回流操作期间控制焊料25的液滴的浸润和高度。
然后将芯片5沉积在基板的第一面上并使用导线17将芯片5连接至第二连接片16。该连接通过超声波实现。
然后将封装材料26(树脂)沉积在芯片5和导线7上以保护它们。为了不将第一模块2增加太多的厚度，封装材料26可以不沉积在电子元件7上。或者，也将封装材料26沉积在一个或多个电子元件7上。如果需要，必须容纳第一模块2的腔体被在卡体6中铣削至更大的深度。
有益地，连续地卷对卷实施上述所有操作。
在以上描述中，在放置和连接电子元件7的操作之后执行放置和连接芯片5的操作。根据一种变型，这些操作的顺序被调换。
上面描述了一种工艺，该工艺包括提供复合材料100，复合材料100包括由介电材料制成的基板9，由第一导电材料制成的第一层21或箔被层压至基板9，然后在连接井18的穿孔之后，向该基板施加第二导电材料层23。或者，该工艺包括提供复合材料(未示出)，该复合材料包括介电基板或载体，该介电基板或载体的每个面被层压有第一导电材料层和第二导电材料层。然后使用激光束形成穿过第一导电材料层和基板的连接井。

Claims (16)

1.芯片卡模块的制造工艺，包括以下操作：
提供介电基板，所述介电基板在所述介电基板的第一主面上承载第一导电材料层，以及在所述基板的第二主面上承载第二导电材料层，
在所述基板第一主面的一侧，将至少一个集成电路固定至所述基板，并且将所述至少一个集成电路连接至第一连接片，
包括一个或多个操作，其中将可熔焊料沉积在形成于所述第一导电材料层中的第二连接片上，并且通过回流所述焊料将至少一个电子元件连接至所述第二连接片。
2.根据权利要求1所述的工艺，包括在回流所述焊料之前，将焊料掩模沉积在所述基板的所述第一主面上的操作。
3.根据权利要求1或2所述的工艺，其中在将所述集成电路连接至所述第一连接片的所述操作之前，执行回流所述焊料的所述操作。
4.根据权利要求1或2所述的工艺，其中在将所述集成电路连接至所述第一连接片的所述操作之后，执行回流所述焊料的所述操作。
5.根据权利要求1所述的工艺，其中使用导线将所述集成电路连接至所述第一连接片。
6.根据权利要求1所述的工艺，其中所述焊料的熔点在130℃和250℃之间。
7.根据权利要求1所述的工艺，其中使用选自以下列表的技术沉积所述焊料：喷射、接触分配、引脚转移和丝网印刷。
8.根据权利要求1所述的工艺，包括将封装材料沉积在所述集成电路上的操作，所述封装材料不覆盖所述电子元件。
9.根据权利要求1所述的工艺，其中所述第二连接片的长度等于400±50微米，宽度等于300±50微米，并且其中所述第二连接片之间的距离等于300±50微米。
10.一种芯片卡模块，包括介电基板，所述介电基板在所述基板的第一主面上承载有第一导电材料层，在所述基板的第二主面上承载有第二导电材料层，在其第一主面上承载有牢固地固定于所述基板并且连接于第一连接片的集成电路，其中使用在所述第二连接片上沉积且回流的可熔焊料将至少一个可焊电子元件连接至形成于所述第一导电材料层中的第二连接片。
11.根据权利要求10所述的芯片卡模块，其中所述电子元件是无源元件。
12.根据权利要求10或11所述的芯片卡模块，其中所述焊料是包括以下列出的至少两种元素的合金：铋、锡、银和铜。
13.根据权利要求10所述的芯片卡模块，其中封装材料围绕所述集成电路，而不覆盖所述电子元件。
14.根据权利要求10所述的芯片卡模块，其中所述电子元件具有两个纵向端部和在每个纵向端部处的待焊端子，所述端子之间的距离大于或等于相应连接片之间的距离。
15.根据权利要求14所述的芯片卡模块，其中所述第二连接片的长度等于400±50微米，宽度等于300±50微米，并且其中所述第二连接片之间的距离等于300±50微米。
16.一种芯片卡，包括卡体和腔体，在所述腔体中容纳有根据权利要求10至14中任一项所述的模块。
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