CN1143315C - 非同步式先入先出存储装置的控制电路 - Google Patents
非同步式先入先出存储装置的控制电路 Download PDFInfo
- Publication number
- CN1143315C CN1143315C CNB991095278A CN99109527A CN1143315C CN 1143315 C CN1143315 C CN 1143315C CN B991095278 A CNB991095278 A CN B991095278A CN 99109527 A CN99109527 A CN 99109527A CN 1143315 C CN1143315 C CN 1143315C
- Authority
- CN
- China
- Prior art keywords
- mentioned
- signal
- clock
- event signal
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/06—Clock generators producing several clock signals
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System (AREA)
- Multi Processors (AREA)
- Information Transfer Systems (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR19863/98 | 1998-05-29 | ||
KR19863/1998 | 1998-05-29 | ||
KR1019980019863A KR19990086737A (ko) | 1998-05-29 | 1998-05-29 | 비동기식 선입선출 시스템의 제어 장치 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1238528A CN1238528A (zh) | 1999-12-15 |
CN1143315C true CN1143315C (zh) | 2004-03-24 |
Family
ID=19537925
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB991095278A Expired - Fee Related CN1143315C (zh) | 1998-05-29 | 1999-05-29 | 非同步式先入先出存储装置的控制电路 |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP3138865B2 (ko) |
KR (1) | KR19990086737A (ko) |
CN (1) | CN1143315C (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102931994A (zh) * | 2012-09-26 | 2013-02-13 | 成都嘉纳海威科技有限责任公司 | 应用于信号处理芯片的高速信号采样和同步的架构及方法 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004071103A (ja) | 2002-08-08 | 2004-03-04 | Sharp Corp | 自己同期型fifoメモリ装置 |
JP2005101771A (ja) * | 2003-09-22 | 2005-04-14 | Matsushita Electric Ind Co Ltd | クロック乗せ替え回路および方法 |
CN100536020C (zh) * | 2004-07-23 | 2009-09-02 | 华为技术有限公司 | 一种先入先出存储器及其读写地址的调整方法 |
WO2006131964A1 (ja) * | 2005-06-08 | 2006-12-14 | Fujitsu Limited | 半導体記憶装置および電子機器 |
-
1998
- 1998-05-29 KR KR1019980019863A patent/KR19990086737A/ko not_active Application Discontinuation
-
1999
- 1999-05-29 CN CNB991095278A patent/CN1143315C/zh not_active Expired - Fee Related
- 1999-05-31 JP JP11151735A patent/JP3138865B2/ja not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102931994A (zh) * | 2012-09-26 | 2013-02-13 | 成都嘉纳海威科技有限责任公司 | 应用于信号处理芯片的高速信号采样和同步的架构及方法 |
CN102931994B (zh) * | 2012-09-26 | 2015-11-25 | 成都嘉纳海威科技有限责任公司 | 应用于信号处理芯片的高速信号采样和同步的架构及方法 |
Also Published As
Publication number | Publication date |
---|---|
JP3138865B2 (ja) | 2001-02-26 |
KR19990086737A (ko) | 1999-12-15 |
JP2000011636A (ja) | 2000-01-14 |
CN1238528A (zh) | 1999-12-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20080028249A1 (en) | System and method for adaptive frequency scaling | |
CN109960671B (zh) | 一种数据传输系统、方法及计算机设备 | |
CN1993936A (zh) | FlexRay通信组件 | |
JP2001014269A (ja) | コンピュータシステム | |
CN1143315C (zh) | 非同步式先入先出存储装置的控制电路 | |
US6163584A (en) | Synchronization element for converting an asynchronous pulse signal into a synchronous pulse signal | |
US7613265B2 (en) | Systems, methods and computer program products for high speed data transfer using an external clock signal | |
US6584536B1 (en) | Bus transaction accelerator for multi-clock systems | |
CN1201212C (zh) | 数字信号处理方法与数据处理器 | |
CN101833431A (zh) | 基于fpga实现的双向高速fifo存储器 | |
WO2001024022A1 (en) | Method and apparatus for decoupling processor speed from memory subsystem speed in a node controller | |
US7899955B2 (en) | Asynchronous data buffer | |
US20080059830A1 (en) | Systems, methods and computer program products for high speed data transfer using a plurality of external clock signals | |
CN2502323Y (zh) | 改变数据存取速率的缓冲器及应用该缓冲器的系统 | |
CN114840458B (zh) | 读写模块、片上系统和电子设备 | |
CN115103032B (zh) | 通信协议控制电路和芯片 | |
Ning et al. | Design of a GALS Wrapper for Network on Chip | |
CN115834602A (zh) | 一种异步数据流通信交互系统 | |
CN116561036B (zh) | 数据访问控制方法、装置、设备及存储介质 | |
Fernández et al. | GALS SoC interconnect bus for wireless sensor network processor platforms | |
JP2004021938A (ja) | データ転送制御回路 | |
Yaver et al. | Adaptive readout technique for a sixteen channel peak sensing ADC in the FERA format | |
JP3892323B2 (ja) | ハンドシェークプロトコル変換用論理回路および非同期式lsiチップ用入出力インターフェース回路 | |
JP3921296B2 (ja) | インタフェース装置 | |
JP2694408B2 (ja) | スタッフ要求検出回路 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C06 | Publication | ||
PB01 | Publication | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20040324 Termination date: 20150529 |
|
EXPY | Termination of patent right or utility model |