CN1143315C - Control circuit of asynchronous first in first out system - Google Patents
Control circuit of asynchronous first in first out system Download PDFInfo
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- CN1143315C CN1143315C CNB991095278A CN99109527A CN1143315C CN 1143315 C CN1143315 C CN 1143315C CN B991095278 A CNB991095278 A CN B991095278A CN 99109527 A CN99109527 A CN 99109527A CN 1143315 C CN1143315 C CN 1143315C
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Abstract
The present invention relates to a control circuit of asynchronous first in first out storage device, especially relates to a control circuit for controlling the asynchronous first in first out storage device with self generated local clock effectively, which not only can achieve the first in first out storage device with much less storage devices than existing asynchronous first in first out storage device, but also system is effectively controlled by using necessary partial actions of self generated local clock, and unnecessary electric consumption is avoided, also the problem of complex clock distribution when carry out image and audio process system of portable wireless terminal and multimedia terminal with ASIC.
Description
The present invention relates to the control circuit of asynchronous first in first out system, particularly relate to and utilize the autonomous local clock that generates to control the control circuit of asynchronous first in first out system effectively.
Recently, because needs and development by the service of portable terminal device or wireless multimedia terminal have been quickened in the technology in multimedia service field and developing by leaps and bounds of semiconductor technology.This service can realize that its price competitiveness of asic chip of exploitation is decided by the degree of miniaturization, light weight, low power consumption recently by microminiature dedicated semiconductor (ASIC) chip.Also must possess above-mentioned condition when therefore, designing hardware.In the past few decades, the main flow of the design of nearly all digital display circuit all is the synchronous mode design, can carry out central centralized control, and control is simple, makes the everything of system be synchronized to system clock.Yet, be when computing machine is developed at first with asynchronous type design techniques design digital display circuit.But, therefore have the shortcoming of design complexity and specific implementation difficulty, so synchronous mode is designed to main flow because the asynchronous type design must realize part control at the position of each deal with data.
Recently, because development of semiconductor, comprised large-scale logic on the chip, therefore for the control of the clock of controlling a huge total system, very big burden when becoming semiconductor circuit design, the overhead that in fact is used for clock is very large, even to use about 1/3 of the whole logic regions of system as clock distribution, like this, not only design is very complicated and difficult, and can cause variety of issues such as wasting a lot of electric power.
Therefore, the present invention proposes in order to address the above problem, purpose provides a kind of control circuit of asynchronous first in first out system, local clock according to autonomous generation, only make necessary part activities, in addition part is failure to actuate, and promptly can prevent unnecessary power consumption, the clock distribution problem that occurs in the time of can solving the large scale system design simply.
In order to reach this purpose, of the present invention writing with the asynchronous type control setting and read-out processor between the circuit of first-in first-out FIFO storer in comprise: the clock generation part writes and the read-out processor input receives the request event signal and produces clock from above-mentioned; Write and read the address pointer generation part, input receives the clock of above-mentioned clock generation part, produce the address that is used to specify the storage data write the address pointer signal and be used to specify the address of having preserved sense data read the address pointer signal; The 1st alternative pack is according to the clock that transmits from above-mentioned clock generation part, writing and read by above-mentioned that the address pointer generation part transmits writes the address pointer signal and read the address pointer signal and be delivered to above-mentioned storer selectively; Write and read the enable signal generation part, input receives the clock from above-mentioned clock generation part, generation be used for the write-enable signal and being used to that data write above-mentioned storer read above-mentioned memory storage data read enable signal, and it is delivered to above-mentioned storer; The stored condition judgement part utilizes from above-mentioned and writes and read the address pointer generation part transmits write the address pointer signal and read the address pointer signal, differentiates data storage state in the above-mentioned storer; Confirm the event signal generation part, according to the clock of above-mentioned clock generation part transmission and the output signal of above-mentioned stored condition judgement part, write and read-out processor input reception request event signal from above-mentioned, produce and confirm event signal and it is delivered to above-mentioned writing and read-out processor.
Brief description of drawings
Fig. 1 is the block scheme of the asynchronous type first-in first-out device that is suitable for of the present invention.
Fig. 2 is the process flow diagram of the asynchronous type first-in first-out device action process of key diagram 1.
Fig. 3 is the block scheme of the embodiment that constitutes of the summary of expression asynchronous first in first out system control circuit of the present invention.
Fig. 4 is the pie graph of an embodiment of stored condition judegment part shown in Figure 3.
Fig. 5 a is the pie graph of an embodiment of the 1st affirmation event signal generating unit shown in Figure 3.
Fig. 5 b is the pie graph of an embodiment of the 2nd affirmation event signal generating unit shown in Figure 3.
Fig. 6 is the action timing diagram of asynchronous first in first out system control circuit shown in Figure 3.
Describe most preferred embodiment of the present invention with reference to the accompanying drawings in detail.
Fig. 1 is that the square frame of the asynchronous first in first out system that is suitable for of the present invention constitutes exemplary plot, have: SRAM 140, as first-in first-out (FIFO) storer of between transmitter side processor 110 (to call " writing processor " in the following text) and receiver side processor 120 (to call " read-out processor " in the following text), intercoursing data with asynchronous type, and the fifo control circuit 130 of controlling it.
In general, when under the asynchronous type circuit conditions, intercoursing data, beyond the divisor number of it is believed that, intercourse simultaneously and pay data request signal and the data acknowledge signal that adds, when confirming action each other, finish the communication between sender and the recipient, be called " signal exchange " (hand shaking).That is to say, sender 110 is when the data that output is finished dealing with, request signal ireq to the available regulation of fifo control circuit 130 these data of output after receiving from the affirmation signal iack of above-mentioned fifo control circuit 130 to this, finishes the processing and the transmission of next data again.Recipient 120 is in the moment of oneself wishing data processing, send the request signal oreq of regulation to above-mentioned fifo control circuit 130, after receiving the affirmation signal oack that exports when exporting after above-mentioned fifo control circuit is finished data processing, finish the processing and the reception of next data again.
Describe the action of asynchronous type first-in first-out device in detail with above-mentioned structure with reference to Fig. 2.
Fig. 2 is the course of action flow example figure of the asynchronous type first-in first-out device of Fig. 1.
With reference to Fig. 2, at first initialization writes and read-out processor 110,120, control circuit 130 and FIFO storer SRAM 140 (steps 201).At this moment, all the logical voltage level of incident event etc. is ' 0 ' state.Then, above-mentioned fifo control circuit 130 judges whether to have imported request event signal ireq, the oreq (step 202) from writing processor 110 or read-out processor 120.If imported from the request event signal ireq that writes processor 110, then above-mentioned fifo control circuit 130 produces and is used to handle address signal addr and the write-enable signal web that writes the request event of processor 110 from above-mentioned, write data recording that processor 110 applies to FIFO storer SRAM140 above-mentioned, notice is delivered to the above-mentioned processor 110 (step 203,204) that writes to the affirmation signal iack of request event signals security processing.
On the contrary, if above-mentioned request event signal is the request event signal oreq from above-mentioned read-out processor 120, then above-mentioned fifo control circuit 130 produces the address signal addr that is used to handle from the request event signal oreq of above-mentioned read-out processor 120, read out from the designated data of above-mentioned FIFO storer SRAM140 and be delivered to above-mentioned read-out processor 120, simultaneously, the signal oack that confirms data output is outputed to read-out processor 120 (step 203,204).
On the other hand, if in request event signal oreq input deterministic process 202 from read-out processor 120, not request event signal oreq, then turn back to deterministic process 202 from the request event signal ireq input that writes processor 110 from above-mentioned read-out processor 120.
Fig. 3 is the control device block scheme of the asynchronous type first-in first-out system of one embodiment of the invention.
As shown in Figure 3, the control circuit of asynchronous first in first out system of the present invention has: the 1st clock generating unit 310, input receive from the request event signal ireq that writes processor 110, produce clock; The 2nd clock generating unit 320, input receives the request event signal oreq from read-out processor 120, produces clock; Write address pointer generating unit 330, input receives the clock that the 1st clock generating unit 310 transmits, produce be used to specify the address of storing data write address pointer signal wptr; Read address pointer generating unit 340, input receives the clock that the 2nd clock generating unit 320 transmits, produce be used to specify that sense data stores the address read address pointer signal rptr; Phase inverter 351, input end is connected with the output terminal of the 1st clock generating unit 310, the clock paraphase that the 1st clock generating unit 310 is transmitted; Phase inverter 352, input end is connected with the output terminal of the 2nd clock generating unit 320, the clock paraphase that the 2nd clock generating unit 320 is transmitted; Selection portion 353, the 1st input end is connected with the output terminal that writes address pointer generating unit 330, the 2nd input end is connected with the output terminal of reading address pointer generating unit 340, the selecting side is connected with the output terminal of the 1st clock generating unit 310, clock according to the 1st clock generating unit 310 transmits is delivered to above-mentioned FIFO storer SRAM 140 to the address pointer signal wptr that writes that writes 330 transmission of address pointer generating unit selectively with the address pointer signal rptr that reads that reads 340 transmission of address pointer generating unit; Write and read enable signal generating unit 354, input receives the clock of phase inverter 351, what generation was used for that data were write the write-enable signal web of above-mentioned FIFO storer SRAM 140 and was used to read data that SRAM 140 stores reads enable signal reb, and they are delivered to above-mentioned FIFO storer SRAM 140; Latch portion 360,, latch the data FIFO OUT of above-mentioned FIFO storer SRAM 140 outputs and be delivered to read-out processor 120 according to the clock that the 2nd clock generating unit 340 transmits; Stored condition judegment part 370, utilization writes that address pointer generating unit 330 transmits write address pointer signal wptr and read that address pointer generating unit 340 transmits read address pointer signal rptr, differentiate the data storage state among the above-mentioned FIFO storer SRAM 140; The 1st confirms event signal generating unit 380, according to the clock wiclk of the 1st clock generating unit 310 transmission and the output signal full of stored condition judegment part 370, input receives from the request event signal ireq that writes processor 110 and produces confirms event signal iack, this affirmation event signal iack is delivered to writes processor 110; The 2nd confirms event signal generating unit 390, according to the clock riclk of the 2nd clock generating unit 320 transmission and the output signal e mpty of stored condition judegment part 370, input receives from the request event signal oreq of read-out processor 120 and produces confirms event signal oack, and oack is delivered to read-out processor 120 this affirmation event signal.
The 1st clock generating unit 310 has: delay portion 311 postpones from writing the request event signal ireq that processor 110 transmits; Clock generator 312, input receive from the request event signal that writes the processor 110 direct request event signal ireq that transmit and postpone by delay portion 311, and produce clock.
The clock generator 312 of the 1st clock generating unit 310 by to by an input end from write processor 110 directly input request event signal ireq and constitute by the partial sum gate XOR1 that delay portion 311 postpones to carry out from the request event signal of another input end input nonequivalence operation.
The 2nd clock generating unit 320 has: delay portion 321 postpones the request event signal oreq that transmits from read-out processor 120; Clock generator 322, input receive the request event signal oreq that directly transmits from read-out processor 120 and the request event signal by 321 delays of delay portion, and the generation clock.
The clock generator 322 of the 2nd clock generating unit 320 by to by an input end from read-out processor 120 directly input request event signal oreq and constitute by the partial sum gate XOR2 that delay portion 321 postpones to carry out from the request event signal of another input end input nonequivalence operation.
Writing address pointer generating unit 330 is made of counter 331, receive the initializing signal init that applies from the outside by the reseting terminal input, input terminal is connected with the output terminal of the partial sum gate 312 of clock generating unit 310, lead-out terminal is connected with the 1st input end of selection portion 353, and the clock that clock generating unit 310 transmits is counted.
Reading address pointer generating unit 340 is made of counter 341, receive the initializing signal init that applies from the outside by the reseting terminal input, input terminal is connected with the output terminal of the partial sum gate 322 of clock generating unit 320, lead-out terminal is connected with the 2nd input end of selection portion 353, and the clock that clock generating unit 320 transmits is counted.
Write and read enable signal generating unit 354 and be made of the delayer (not shown), input end is connected with the output terminal of phase inverter 351, and output terminal is connected with above-mentioned FIFO storer SRAM 140, and the clock wiclk that phase inverter 351 is transmitted postpones.
Latching portion 360 is made of d type flip flop 361, receive the initializing signal init that applies from the outside by the reseting terminal input, clock terminal is connected with the output terminal of the partial sum gate XOR2 of the 2nd clock generating unit 320, lead-out terminal is connected with the input end of read-out processor 120, and the data that above-mentioned FIFO storer SRAM 140 is transmitted postpone.
Describe stored condition judegment part 370 in detail with reference to Fig. 4.
Describe the 1st and the 2nd affirmation event signal generating unit 380,390 in detail with reference to Fig. 5 a and Fig. 5 b.
Below describe the action of the control circuit of asynchronous first in first out system of the present invention in detail with above-mentioned structure.
After 310 inputs of the 1st clock generating unit receive the request event signal ireq that writes processor 11O transmission and produce clock, by writing address pointer generating unit 330, selection portion 353 and phase inverter 351, this clock is delivered to writes and read enable signal generating unit 354 and the 1st and confirm event signal generating unit 380.After 320 inputs of the 2nd clock generating unit receive the request event signal oreq of read-out processor 120 transmission and produce clock, by reading address pointer generating unit 340, latching portion 360 and phase inverter 352, this clock is delivered to the 2nd confirms event signal generating unit 390.
Write the clock that address pointer generating unit 330 utilizes the 1st clock generating unit 310 to transmit, produce and write address pointer signal wptr, again this is write address pointer signal wptr and be delivered to selection portion 353 and stored condition judegment part 370.Read 340 inputs of address pointer generating unit and receive the clock that the 2nd clock generating unit 320 transmits, produce and read the address pointer signal, again it is delivered to selection portion 353 and stored condition judegment part 370.
The clock that selection portion 353 transmits according to the 1st clock generating unit 310 is delivered to above-mentioned FIFO storer SRAM 140 selectively to the address pointer signal rptr that reads that writes address pointer signal wptr and read 340 transmission of address pointer generating unit that writes that address pointer generating unit 330 transmits.That is to say that if the 1st clock generating unit 310 transmits the clock of high state, then selection portion 353 is delivered to above-mentioned FIFO storer SRAM 140 to the address pointer signal wptr that writes that writes 330 transmission of address pointer generating unit; If the 1st clock generating unit 310 transmits the clock of low state, then selection portion 353 is delivered to above-mentioned FIFO storer SRAM 140 to the address pointer signal rptr that reads that reads 340 transmission of address pointer generating unit.Here, the output signal of selection portion 353 is exactly the signal of specifying the address of above-mentioned FIFO storer SRAM 140.
Stored condition judegment part 370 utilization writes that address pointer generating unit 330 transmits writes address pointer signal wptr, whether the address that judgement can be stored data is the address that can store data in above-mentioned FIFO storer SRAM140, its judged result is delivered to the 1st and the 2nd confirms event signal generating unit 380,390.In addition, stored condition judegment part 370 input receive read that address pointer generating unit 340 transmits read address pointer signal rptr, judge whether it is the data that above-mentioned FIFO storer SRAM 140 stores, its judged result is delivered to the 1st and the 2nd confirms event signal generating unit 380,390.
Write and read enable signal generating unit 354 according to the clock that transmits by phase inverter 351, generation be used for to above-mentioned FIFO storer SRAM 140 write the write-enable signal web of data and be used for from above-mentioned FIFO storer SRAM 140 read store data read enable signal reb, and this write-enable signal web with read enable signal reb and be delivered to above-mentioned FIFO storer SRAM 140.
Like this, if transmitted write-enable signal web from writing and read enable signal generating unit 354, then above-mentioned FIFO storer SRAM 140 arrives read-out processor 120 to the data transfer of storing in the address of the address signal appointment that transmits in selection portion 353 by the portion of latching 360; If transmitted and read enable signal reb from writing and read enable signal generating unit 354, then above-mentioned FIFO storer SRAM 140 stores in the address of the address signal appointment that selection portion 353 transmits and writes the data that processor 110 transmits.
The 1st confirms that event signal generating unit 380 is according to the clock wiclk of the 1st clock generating unit 310 transmission and the output signal full of stored condition judegment part 370, utilization writes the request event signal ireq that processor 110 transmits, produce to confirm event signal iack, and should confirm that event signal iack is delivered to and write processor 110.The 2nd confirms that event signal generating unit 390 is according to the clock riclk of the 2nd clock generating unit 320 transmission and the output signal e mpty of stored condition judegment part 370, the request event signal oreq that utilizes read-out processor 120 to transmit, after producing affirmation event signal oack, and should confirm that event signal oack was delivered to read-out processor 120.
Fig. 4 is the pie graph of an embodiment of above-mentioned stored condition judegment part shown in Figure 3.
As shown in Figure 4, the stored condition judegment part of above-mentioned Fig. 3 has: the 1st comparing section 410 writes address pointer signal wptr and reads the size of reading address pointer signal rptr that address pointer generating unit 340 transmits and compare what write that address pointer generating unit 330 transmits; Signed magnitude arithmetic(al) portion 420, deduct the address pointer signal wptr from writing of writing that address pointer generating unit 330 transmits and to read address pointer generating unit 340 transmits read address pointer signal rptr and export the 1st subtraction value wptr-rptr, to from the address maximal value SRAM_depth of above-mentioned FIFO storer 140, deduct the 2nd subtraction value SRAM_depth_rptr that address pointer signal rptr obtains that reads that reads 340 transmission of address pointer generating unit, with write that address pointer generating unit 330 transmits write address pointer signal wptr addition, and export this additive value SRAM_depth-rptr+wptr; Selection portion 430 according to the output signal of the 1st comparing section 410, is transmitted output signal wptr-rptr, the SRAM_depth-rptr+wptr of signed magnitude arithmetic(al) portion 420 selectively; The 2nd comparing section 440, relatively the output signal of selection portion 430 and the size of stipulated standard value are delivered to the 2nd affirmation event signal generating unit 390 to expression according to the 1st stored condition signal empty that this comparative result is judged to the data storage state of other SRAM 140; The 3rd comparing section 450, relatively the size of the address maximal value SRAM_depth of the output signal of selection portion 430 and predefined above-mentioned FIFO storer 140 is delivered to the 1st affirmation event signal generating unit 380 to expression according to the 2nd stored condition signal full that this comparative result is judged to the data storage state of other above-mentioned FIFO storer 140.
Here, the stipulated standard value of setting at an input end of the 2nd comparing section 440 is 10 systems ' 0 '.
Describe the action of Fig. 3 stored condition judegment part below in detail with above-mentioned structure.
410 pairs of the 1st comparing sections write that address pointer generating unit 330 transmits writes address pointer signal wptr and reads the size of reading address pointer signal rptr that address pointer generating unit 340 transmits and compare, this comparative result outputs to selection portion 430, as the selection signal of selection portion 430.That is to say that if write address pointer signal wptr greater than reading address pointer signal rptr, then the 1st comparing section 410 is to selection portion 430 outputs ' 1 '; If write address pointer signal wptr less than reading address pointer signal rptr, then the 1st comparing section 410 is to selection portion 430 outputs ' 0 '.
Signed magnitude arithmetic(al) portion 420 usefulness write that address pointer generating unit 330 transmits write address pointer signal wptr deduct read that address pointer generating unit 340 transmits read address pointer signal rptr, and the 1st subtraction value wptr-rptr after will subtracting each other outputs to selection portion 420.In addition, signed magnitude arithmetic(al) portion 420 from the address maximal value SRAM depth of above-mentioned FIFO storer 140, deduct read that address pointer generating unit 340 transmits read address pointer signal rptr after, the 2nd subtraction value SRAM_depth-rptr that subtraction is thus obtained with write that address pointer generating unit 330 transmits write address pointer signal wptr addition, and this additive value SRAM_depth-rptr+wptr is outputed to selection portion 430.
Selection portion 430 is delivered to the 2nd and the 3rd comparing section 440,450 to two output signal wptr_rptr, SRAM_depth-rptr+wptr of signed magnitude arithmetic(al) portion 420 selectively according to the output signal of the 1st comparing section 410.At this moment, if the 1st comparing section 410 transmits ' 0 ', then selection portion 430 is delivered to the 2nd and the 3rd comparing section 440,450 to the subtraction value wptr-rptr of signed magnitude arithmetic(al) portion 420 outputs, if the 1st comparing section 410 transmits ' 1 ', then selection portion 430 is delivered to the 2nd and the 3rd comparing section 440,450 to the additive value SRAM_depth-rptr+wptr of signed magnitude arithmetic(al) portion 420 outputs.
Then, the output signal of 440 pairs of selection portions 430 of the 2nd comparing section and the size of specified reference value compare, expression is outputed to the 2nd affirmation event signal generating unit 390 according to the 1st stored condition signal empty that this comparative result is judged to the data storage state of other above-mentioned FIFO storer 140, in addition, the size of the output signal of 450 pairs of selection portions 430 of the 3rd comparing section and the address maximal value SRAM_depth of predefined above-mentioned FIFO storer 140 compares, and expression is outputed to the 1st affirmation event signal generating unit 380 according to the 2nd stored condition signal full that this comparative result is judged to the data storage state of other above-mentioned FIFO storer 140.
Below, to being sent to the situation of the 2nd and the 3rd comparing section 440,450 from the subtraction value wptr-rptr of signed magnitude arithmetic(al) portion 420 output by selection portion 430 and being described in detail by the situation that selection portion 430 is sent to the 2nd and the 3rd comparing section 440,450 from the additive value SRAM_depth-rptr+wptr of signed magnitude arithmetic(al) portion 420 outputs.
At first, the situation that the subtraction value wptr-rptr from signed magnitude arithmetic(al) portion 420 output is sent to the 2nd and the 3rd comparing section 440,450 is illustrated.
The size of 440 pairs of specified reference value of the 2nd comparing section and the subtraction value wptr-rptr that transmits by selection portion 430 compares, and expression is outputed to the 2nd affirmation event signal generating unit 390 according to the 1st stored condition signal empty that this comparative result is judged to the data storage state of other SRAM 140.That is to say that greater than subtraction value wptr-rptr, then the 2nd comparing section 440 outputs to the 2nd affirmation event signal generating unit 390 to the 1st stored condition signal empty of low state as if specified reference value; If specified reference value 0 is identical with subtraction value wptr-rptr, then the 2nd comparing section 440 outputs to the 2nd affirmation event signal generating unit 390 to the 1st stored condition signal empty of high state.
In addition, the size of the address maximal value SRAM_depth of 450 pairs of predefined above-mentioned FIFO storeies 140 of the 3rd comparing section and the subtraction value wptr-rptr that transmits by selection portion 430 compares, and expression is outputed to the 1st affirmation event signal generating unit 380 according to the 2nd stored condition signal full that this comparative result is judged to the data storage state of other above-mentioned FIFO storer 140.That is to say that if the address maximal value SRAM depth of predefined above-mentioned FIFO storer 140 is less than subtraction value wptr-rptr, then the 3rd comparing section 450 outputs to the 2nd affirmation event signal generating unit 390 to the 2nd stored condition signal full of low state; If the address maximal value SRAM_depth of predefined above-mentioned FIFO storer 140 is identical with subtraction value wptr-rptr, then the 3rd comparing section 450 outputs to the 1st affirmation event signal generating unit 380 to the 2nd stored condition signal full of high state.
Next, the situation that the additive value SRAM_depth-rptr+wptr from 420 outputs of signed magnitude arithmetic(al) portion is sent to the 2nd and the 3rd comparing section 440,450 is described in detail.
The size of 440 pairs of specified reference value of the 2nd comparing section and the additive value SRAM_depth-rptr+wptr that transmits by selection portion 430 compares, and expression is outputed to the 2nd affirmation event signal generating unit 390 according to the 1st stored condition signal empty that this comparative result is judged to the data storage state of other above-mentioned FIFO storer 140.That is to say that greater than additive value SRAM_depth-rptr+wptr, then the 2nd comparing section 440 outputs to the 2nd affirmation event signal generating unit 390 to the 1st stored condition signal empty of low state as if specified reference value; If specified reference value is identical with additive value SRAM_depth-rptr+wptr, then the 2nd comparing section 440 outputs to the 2nd affirmation event signal generating unit 390 to the 1st stored condition signal empty of high state.
In addition, the size of the address maximal value SRAM_depth of 450 couples of predefined SRAM 140 of the 3rd comparing section and the additive value SRAM_depth-rptr+wptr that transmits by selection portion 430 compares, and expression is outputed to the 1st affirmation event signal generating unit 380 according to the 2nd stored condition signal full that this comparative result is judged to the data storage state of other above-mentioned FIFO storer 140.That is to say, if the address maximal value SRAM_depth of predefined above-mentioned FIFO storer 140 is less than additive value SRAM_depth-rptr+wptr, then the 3rd comparing section 450 outputs to the 2nd affirmation event signal generating unit 390 to the 2nd stored condition signal full of low state; If the address maximal value SRAM_depth of predefined above-mentioned FIFO storer 140 is identical with additive value SRAM_depth-rptr+wptr, then the 3rd comparing section 450 outputs to the 1st affirmation event signal generating unit 380 to the 2nd stored condition signal full of high state.
Fig. 5 a is the pie graph of an embodiment of above-mentioned the 1st affirmation event signal generating unit shown in Figure 3.
Shown in Fig. 5 a, the 1st of above-mentioned Fig. 3 confirms that the event signal generating unit has: selection portion 510, according to the 2nd stored condition signal full that the 3rd comparing section 450 transmits, transmit request event signal that writes processor 110 transmission and the output signal of confirming event signal efferent 520 selectively; Affirmation event signal efferent 520, according to the clock wiclk that transmits by phase inverter 351 paraphase, input receives the output signal of selection portion 510, the 1st affirmation event signal is outputed to write processor 110.
Confirm that event signal efferent 520 is made of d type flip flop 521, receive the initializing signal that applies from the outside by the reseting terminal input, its input terminal is connected with the output terminal of selection portion 510, clock terminal is connected with the output terminal of phase inverter 351, and lead-out terminal is connected jointly with the input end of the input end that writes processor 110 with selection portion 510.
Describe the action of the 1st affirmation event signal generating unit of the Fig. 3 with above-mentioned structure below in detail.
If transmitted low state the 2nd stored condition signal full from the 3rd comparing section 450, then selection portion 510 is selected to write the request event signal ireq that processor 110 transmits, and is delivered to the input terminal of the d type flip flop 521 of confirming event signal efferent 520.As if the 2nd stored condition signal full that has transmitted low state from the 3rd comparing section 450, then select to confirm the output signal iack of event signal efferent 520, and be delivered to the input terminal of the d type flip flop 521 of confirming event signal efferent 520.
Then, the d type flip flop 521 of confirming event signal efferent 520 latchs the signal of selection portion 510 outputs according to the clock that transmits by phase inverter 351, and the signal that this is latched outputed to writes processor 110 or selection portion 510.At this moment, if the 2nd stored condition signal full that imports as the selection signal of selection portion 510 is low state, confirm that then event signal efferent 520 writes processor 110 confirming that event signal iack outputs to; If the 2nd stored condition signal full that imports as the selection signal of selection portion 510 is a high state, confirm that then the d type flip flop 521 of event signal efferent 520 latchs behind the signal of selection portion 510 inputs, feed back to the input end of selection portion 510.
Fig. 5 b is the pie graph of an embodiment of the 2nd affirmation event signal generating unit shown in Figure 3.
Shown in Fig. 5 b, the 2nd of Fig. 3 confirms that the event signal generating unit has: selection portion 610, according to the 1st stored condition signal empty that the 2nd comparing section 440 transmits, transmit the request event signal oreq of read-out processor 120 transmission and the output signal oack of affirmation event signal efferent 620 selectively; Confirm event signal efferent 620, according to the clock riclk that transmits by phase inverter 352 paraphase, input receives the output signal of selection portion 610, and confirms that event signal oack outputs to read-out processor 120 to the 2nd.
Confirm that event signal efferent 620 is made of d type flip flop 621, receive the initializing signal init that applies from the outside by the reseting terminal input, its input terminal is connected with the output terminal of selection portion 610, clock terminal is connected with the output terminal of phase inverter 352, and lead-out terminal is connected jointly with the input end of read-out processor 120 and the input end of selection portion 610.
Describe the action of the 2nd affirmation event signal generating unit of the Fig. 3 with above-mentioned formation below in detail.
As if the 1st stored condition signal empty that has transmitted low state from the 2nd comparing section 440, then selection portion 610 is selected the request event signal oreq that read-out processors 120 transmit, and is delivered to the input terminal of the d type flip flop 621 of confirming event signal efferent 620.As if the 1st stored condition signal empty that has transmitted low state from the 2nd comparing section 440, then select to confirm the output signal of event signal efferent 620, and be delivered to the input terminal of the d type flip flop 621 of confirming event signal efferent 620.
Then, the d type flip flop 621 of confirming event signal efferent 620 latchs the signal of selection portion 610 outputs according to the clock that transmits by phase inverter 352, and latched signal is outputed to read-out processor 120 or selection portion 610.At this moment, if the 1st stored condition signal empty that imports as the selection signal of selection portion 610 is low state, confirm that then event signal efferent 620 is confirming that event signal oack outputs to read-out processor 120; If the 1st stored condition signal empty that imports as the selection signal of selection portion 610 is a high state, confirm that then the d type flip flop 621 of event signal efferent 620 latchs behind the signal of selection portion 610 inputs, feed back to the input end of selection portion 610.
Fig. 6 is the action timing diagram of asynchronous first in first out system control circuit shown in Figure 3, FIFO IN is from writing the data that processor 110 is input to above-mentioned FIFO storer 140, init is the initializing signal that applies from the outside, ireq is from writing the request event signal that processor 110 is input to control device 130, direq is the request event signal by delay portion 311 delays of the 1st clock generating unit 310, cclk is the clock of the 1st clock generating unit 310 outputs, wptr be write that address pointer generating unit 330 produces write the address pointer signal, rptr be read that address pointer generating unit 340 produces read the address pointer signal, addr is the address signal of selection portion 353 outputs, and web is the clock that postpones by delay portion 354.
Although technological thought of the present invention is recorded and narrated by above-mentioned most preferred embodiment is concrete, should notice that the foregoing description only is its explanation, rather than its restriction.The normal expert in the technology of the present invention field can realize various embodiments in the technology of the present invention thought range.
The present invention according to above explanation, not only available than existing synchronous mode pushup storage device storer realization FIFO memory devices still less, and with the autonomous local clock that generates, only make necessary part action, control system effectively, thereby prevent unnecessary power consumption, when the image of realizing portable radio terminal machine, multimedia terminal machine with ASIC and sound processing system, can solve complicated clock distribution problem effectively.
Claims (25)
1. the control circuit of an asynchronous first in first out system, be used for the control of asynchronous type ground be installed in write and read-out processor between the circuit of pushup storage, comprise:
Clock generation part, input receive above-mentioned writing and the request event signal of read-out processor, and produce clock;
Write and read the address pointer generation part, input receives the clock of above-mentioned clock generation part, and produce be used to specify the address of storing data write the address pointer signal and be used to specify sense data the storage address read the address pointer signal;
The 1st alternative pack, the clock that transmits according to above-mentioned clock generation part writes and read above-mentioned that the address pointer generation part transmits writes the address pointer signal and read the address pointer signal and be delivered to above-mentioned storer selectively;
Write and read the enable signal generation part, input receives the clock of above-mentioned clock generation part, generation is used for writing the write-enable signal of data and being used for reading the enable signal of reading of data that above-mentioned storer stores at above-mentioned storer, and it is delivered to above-mentioned storer;
The stored condition judgement part utilizes above-mentioned the writing the address pointer signal and reading the address pointer signal of address pointer generation part transmission that write and read, and differentiates data storage state in the above-mentioned storer;
Confirm the event signal generation part, according to the clock of above-mentioned clock generation part transmission and the output signal of above-mentioned stored condition judgement part, input receives above-mentioned writing and the request event signal of read-out processor, produces and confirms that event signal also is delivered to above-mentioned writing and read-out processor.
2. the control circuit of asynchronous first in first out system as claimed in claim 1 also comprises:
Inverter unit, the clock paraphase that above-mentioned clock generation part is transmitted;
Latching sections, the clock according to above-mentioned clock generation part transmits latchs the output data of above-mentioned storer and is delivered to above-mentioned read-out processor.
3. the control circuit of asynchronous first in first out system as claimed in claim 1 or 2, wherein above-mentioned clock generation part comprises:
The 1st clock generating unit, input receives the above-mentioned request event signal that writes processor, and produces clock;
The 2nd clock generating unit, input receives the request event signal of above-mentioned read-out processor, and produces clock.
4. the control circuit of asynchronous first in first out system as claimed in claim 3, wherein above-mentioned the 1st clock generating unit comprises:
Delay portion postpones the above-mentioned request event signal that processor transmits that writes;
Clock generator, input receive the above-mentioned request event signal that writes request event signal that processor directly transmits and postpone by above-mentioned delay portion, and the generation clock.
5. the control circuit of asynchronous first in first out system as claimed in claim 4, wherein above-mentioned clock generator comprises:
The nonequivalence operation parts, the 1st input end is connected with the above-mentioned output terminal that writes processor, the 2nd input end is connected with the output terminal of above-mentioned delay portion, to by above-mentioned the 1st input end from above-mentioned write processor directly input the request event signal and carry out nonequivalence operation by the request event signal that above-mentioned delay portion postpones to be input to above-mentioned the 2nd input end.
6. the control circuit of asynchronous first in first out system as claimed in claim 3, wherein above-mentioned the 2nd clock generating unit comprises:
Delay portion postpones the request event signal that above-mentioned read-out processor transmits;
Clock generator, request event signal that the above-mentioned read-out processor of input reception directly transmits and the request event signal that postpones by above-mentioned delay unit, and produce clock.
7. the control circuit of asynchronous first in first out system as claimed in claim 6, wherein above-mentioned clock generator comprises:
The nonequivalence operation parts, the 1st input end is connected with the output terminal of above-mentioned read-out processor, the 2nd input end is connected with the output terminal of above-mentioned delay portion, to by above-mentioned the 1st input end from above-mentioned read-out processor directly input the request event signal and carry out nonequivalence operation by the request event signal that above-mentioned delay portion postpones to be input to above-mentioned the 2nd input end.
8. the control circuit of asynchronous first in first out system as claimed in claim 3 wherein above-mentionedly writes and reads the address pointer generation part and comprise:
Write the address pointer generation part, input receives the clock that above-mentioned the 1st clock generating unit transmits, produce be used to specify the address of storing data write the address pointer signal, and be delivered to above-mentioned the 1st alternative pack and stored condition judgement part;
Read the address pointer generation part, input receives the clock that above-mentioned the 2nd clock generating unit transmits, produce be used to specify that sense data stores the address read the address pointer signal, and be delivered to above-mentioned the 1st alternative pack and stored condition judgement part.
9. the control circuit of asynchronous first in first out system as claimed in claim 8, the wherein above-mentioned address pointer generation part that writes comprises:
The 1st counter block, input receives the initializing signal that applies from the outside by reseting terminal, input terminal is connected with the output terminal of above-mentioned the 1st clock generating unit, lead-out terminal is connected with the 1st input end of above-mentioned the 1st alternative pack and the 1st input end of above-mentioned stored condition judgement part, the clock that above-mentioned the 1st clock generating unit transmits is counted, and be sent to the 1st input end of above-mentioned the 1st alternative pack and the 1st input end of stored condition judgement part.
10. the control circuit of asynchronous first in first out system as claimed in claim 9, the wherein above-mentioned address pointer generation part of reading comprises:
The 2nd counter block, input receives the initializing signal that applies from the outside by reseting terminal, input terminal is connected with the output terminal of above-mentioned the 2nd clock generating unit, lead-out terminal is connected with the 2nd input end of above-mentioned the 1st alternative pack and the 2nd input end of above-mentioned stored condition judgement part, the clock that above-mentioned the 2nd clock generating unit transmits is counted, and be delivered to the 2nd input end of above-mentioned the 1st alternative pack and the 2nd input end of above-mentioned stored condition judgement part.
11. the control circuit of asynchronous first in first out system as claimed in claim 3, wherein above-mentioned inverter unit comprises:
The 1st paraphase portion, input end is connected with the output terminal of above-mentioned the 1st clock generating unit, output terminal is connected with the above-mentioned input end that writes and read the enable signal generation part, the clock paraphase that above-mentioned the 1st clock generating unit is transmitted, and be delivered to the above-mentioned enable signal generation part that writes and read;
The 2nd paraphase portion, input end is connected with the output terminal of above-mentioned the 2nd clock generating unit, output terminal is connected with the input end of above-mentioned affirmation event signal generation part, the clock paraphase that above-mentioned the 2nd clock generating unit is transmitted, and be delivered to above-mentioned affirmation event signal generation part.
12. the control circuit of asynchronous first in first out system as claimed in claim 11 wherein above-mentionedly writes and reads the enable signal generation part and comprise:
Delayer, input end is connected with the output terminal of above-mentioned the 1st paraphase portion, and output terminal is connected with above-mentioned SRAM, and the clock that above-mentioned the 1st paraphase portion is transmitted postpones, and is delivered to above-mentioned SRAM.
13. the control circuit of asynchronous first in first out system as claimed in claim 3, wherein above-mentioned latching sections comprises:
D type flip flop, input receives the initializing signal that applies from the outside by reseting terminal, clock terminal is connected with the output terminal of above-mentioned the 2nd clock generating unit, lead-out terminal is connected with the input end of above-mentioned read-out processor, the data that above-mentioned storer is transmitted postpone, and output to above-mentioned read-out processor.
14. the control circuit of asynchronous first in first out system as claimed in claim 3, wherein above-mentioned stored condition judgement part comprises:
The 1st comparing unit is to above-mentioned write that the address pointer generation part transmits write the address pointer signal and above-mentionedly read the size of reading the address pointer signal that the address pointer generation part transmits and compare;
The signed magnitude arithmetic(al) parts, deduct and above-mentionedly read the address pointer signal and export the 1st subtraction value from the above-mentioned address pointer signal that writes, to deduct from the address maximal value of above-mentioned storer above-mentioned read the 2nd subtraction value that the address pointer signal obtains, with the above-mentioned address pointer signal plus that writes, and output additive value;
The 2nd alternative pack according to the output signal of above-mentioned the 1st comparing unit, transmits the output signal of above-mentioned signed magnitude arithmetic(al) parts selectively;
The 2nd comparing unit, whether the output signal of more above-mentioned the 2nd alternative pack is identical with specified reference value, and expression is delivered to above-mentioned affirmation event signal generation part according to the 1st stored condition signal that this comparative result is judged to the data storage state of other above-mentioned storer;
The 3rd comparing unit, whether the address maximal value of the output signal of more above-mentioned the 2nd alternative pack and predefined above-mentioned storer is identical, and expression is delivered to above-mentioned affirmation event signal generation part according to the 2nd stored condition signal that this comparative result is judged to the data storage state of other above-mentioned storer.
15. the control circuit of asynchronous first in first out system as claimed in claim 14 is characterized in that:
When the output signal of above-mentioned the 2nd alternative pack was identical with specified reference value, above-mentioned the 1st stored condition signal that above-mentioned the 2nd comparing unit is not stored the high state of data to the above-mentioned storer of expression outputed to above-mentioned affirmation event signal generation part;
When the output signal ratio specified reference value of above-mentioned the 2nd alternative pack is big, above-mentioned the 2nd comparing unit the above-mentioned memory storage of expression above-mentioned the 1st stored condition signal of low state of data output to above-mentioned affirmation event signal generation part.
16. the control circuit of asynchronous first in first out system as claimed in claim 15 is characterized in that:
When the address maximal value of the output signal of above-mentioned the 2nd alternative pack and predefined above-mentioned SRAM was identical, above-mentioned the 3rd comparing unit outputed to above-mentioned affirmation event signal generation part to above-mentioned the 2nd stored condition signal of storing the high state of data in all addresses of the above-mentioned storer of expression;
When the address maximal value of the predefined above-mentioned storer of output signal ratio of above-mentioned the 2nd alternative pack hour, above-mentioned the 3rd comparing unit has the above-mentioned storer of expression above-mentioned the 2nd stored condition signal of low state of the address of the data of not storing to output to above-mentioned affirmation event signal generation part.
17. the control circuit of asynchronous first in first out system as claimed in claim 14, wherein above-mentioned affirmation event signal generation part comprises:
Inverter unit, this inverter unit has: the 1st paraphase portion, input end is connected with the output terminal of above-mentioned the 1st clock generating unit, output terminal is connected with the above-mentioned input end that writes and read the enable signal generation part, the clock paraphase that above-mentioned the 1st clock generating unit is transmitted, and be delivered to the above-mentioned enable signal generation part that writes and read; And the 2nd paraphase portion, input end is connected with the output terminal of above-mentioned the 2nd clock generating unit, output terminal is connected with the input end of above-mentioned affirmation event signal generation part, the clock paraphase that above-mentioned the 2nd clock generating unit is transmitted, and be delivered to above-mentioned affirmation event signal generation part;
The 1st confirms the event signal generating unit, the 2nd stored condition signal according to clock that transmits by the paraphase of above-mentioned the 1st paraphase portion and the transmission of above-mentioned the 3rd comparing unit, input receives the above-mentioned request event signal that writes processor, produce expression data the received the 1st and confirm event signal, and be delivered to the above-mentioned processor that writes;
The 2nd confirms the event signal generating unit, the 1st stored condition signal according to clock that transmits by the paraphase of above-mentioned the 2nd paraphase portion and the transmission of above-mentioned the 2nd comparing unit, input receives the request event signal of above-mentioned read-out processor, produce expression data the received the 2nd and confirm event signal, and be delivered to above-mentioned read-out processor.
18. the control circuit of asynchronous first in first out system as claimed in claim 17, the wherein above-mentioned the 1st confirms that the event signal generating unit comprises:
The 1st selection portion according to the 1st stored condition signal that above-mentioned the 2nd comparing unit transmits, is transmitted the above-mentioned output signal that writes the request event signal of processor transmission and confirm the event signal efferent selectively;
Above-mentioned affirmation event signal efferent, according to the clock that transmits by the paraphase of above-mentioned the 1st paraphase portion, input receives the output signal of above-mentioned the 1st selection portion, and confirms that event signal outputs to the above-mentioned processor that writes to the above-mentioned the 1st.
19. the control circuit of asynchronous first in first out system as claimed in claim 18, wherein above-mentioned affirmation event signal efferent comprises:
Latch portion,, latch the output signal of above-mentioned the 1st selection portion according to the clock that transmits by the paraphase of above-mentioned the 1st paraphase portion.
20. the control circuit of asynchronous first in first out system as claimed in claim 19, the wherein above-mentioned portion of latching comprises:
D type flip flop, input receives the initializing signal that applies from the outside by reseting terminal, input terminal is connected with the output terminal of above-mentioned the 1st selection portion, clock terminal is connected with the output terminal of above-mentioned the 1st paraphase portion, and lead-out terminal writes the input end of processor and the input end of above-mentioned the 1st selection portion is connected jointly with above-mentioned.
21. the control circuit of asynchronous first in first out system as claimed in claim 20 is characterized in that:
As if the 2nd stored condition signal that has transmitted low state from above-mentioned the 3rd comparing unit, then above-mentioned the 1st selection portion is delivered to the above-mentioned input end that latchs portion to the above-mentioned request event signal that writes the processor transmission;
As if the 2nd stored condition signal that has transmitted high state from above-mentioned the 3rd comparing unit, then above-mentioned the 1st selection portion is delivered to the above-mentioned input end that latchs portion to the signal of the above-mentioned portion of latching feedback.
22. the control circuit of asynchronous first in first out system as claimed in claim 17, the wherein above-mentioned the 2nd confirms that the event signal generating unit comprises:
The 2nd selection portion according to the 1st stored condition signal that above-mentioned the 2nd comparing unit transmits, is transmitted the output signal of the request event signal and the affirmation event signal efferent of above-mentioned read-out processor transmission selectively;
Above-mentioned affirmation event signal efferent, according to the clock that transmits by the paraphase of above-mentioned the 2nd paraphase portion, input receives the output signal of above-mentioned the 2nd selection portion, and confirms that event signal outputs to above-mentioned read-out processor to the above-mentioned the 2nd.
23. the control circuit of asynchronous first in first out system as claimed in claim 22, wherein above-mentioned affirmation event signal efferent comprises:
Latch portion,, latch the output signal of above-mentioned the 2nd selection portion according to the clock that transmits by the paraphase of above-mentioned the 2nd paraphase portion.
24. the control circuit of asynchronous first in first out system as claimed in claim 23, the wherein above-mentioned portion of latching comprises:
D type flip flop, input receives the initializing signal that applies from the outside by reseting terminal, input terminal is connected with the output terminal of above-mentioned the 2nd selection portion, clock terminal is connected with the output terminal of above-mentioned the 2nd paraphase portion, and lead-out terminal is connected jointly with the input end of above-mentioned read-out processor and the input end of above-mentioned the 2nd selection portion.
25. the control circuit of asynchronous first in first out system as claimed in claim 24 is characterized in that:
As if the 1st stored condition signal that has transmitted low state from above-mentioned the 2nd comparing unit, then above-mentioned the 2nd selection portion is delivered to the above-mentioned input end that latchs portion to the request event signal that above-mentioned read-out processor transmits;
As if the 1st stored condition signal that has transmitted high state from above-mentioned the 2nd comparing unit, then above-mentioned the 2nd selection portion is delivered to the above-mentioned input end that latchs portion to the signal of the above-mentioned portion of latching feedback.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980019863A KR19990086737A (en) | 1998-05-29 | 1998-05-29 | Control device of asynchronous first-in, first-out system |
| KR19863/98 | 1998-05-29 | ||
| KR19863/1998 | 1998-05-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1238528A CN1238528A (en) | 1999-12-15 |
| CN1143315C true CN1143315C (en) | 2004-03-24 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB991095278A Expired - Fee Related CN1143315C (en) | 1998-05-29 | 1999-05-29 | Control circuit of asynchronous first in first out system |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP3138865B2 (en) |
| KR (1) | KR19990086737A (en) |
| CN (1) | CN1143315C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102931994A (en) * | 2012-09-26 | 2013-02-13 | 成都嘉纳海威科技有限责任公司 | High-speed signal sampling and synchronizing framework and method applied to signal processing chip |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004071103A (en) | 2002-08-08 | 2004-03-04 | Sharp Corp | Self-synchronizing fifo memory device |
| JP2005101771A (en) * | 2003-09-22 | 2005-04-14 | Matsushita Electric Ind Co Ltd | Clock transferring circuit and method thereof |
| CN100536020C (en) * | 2004-07-23 | 2009-09-02 | 华为技术有限公司 | First-in first-out memory and regulating method of read/write address |
| KR100951420B1 (en) | 2005-06-08 | 2010-04-07 | 후지쯔 마이크로일렉트로닉스 가부시키가이샤 | Semiconductor storage apparatus and electronic device |
-
1998
- 1998-05-29 KR KR1019980019863A patent/KR19990086737A/en not_active Application Discontinuation
-
1999
- 1999-05-29 CN CNB991095278A patent/CN1143315C/en not_active Expired - Fee Related
- 1999-05-31 JP JP11151735A patent/JP3138865B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102931994A (en) * | 2012-09-26 | 2013-02-13 | 成都嘉纳海威科技有限责任公司 | High-speed signal sampling and synchronizing framework and method applied to signal processing chip |
| CN102931994B (en) * | 2012-09-26 | 2015-11-25 | 成都嘉纳海威科技有限责任公司 | Be applied to high speed signal sampling and synchronous framework and the method for signal processing chip |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3138865B2 (en) | 2001-02-26 |
| KR19990086737A (en) | 1999-12-15 |
| CN1238528A (en) | 1999-12-15 |
| JP2000011636A (en) | 2000-01-14 |
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