JP2000011636A - Control circuit of asynchronous first-in first-out memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a control circuit for an asynchronous first-in first-out memory device with a less-capacity memory by generating a recognition event signal from a write and read processor by an output signal from means for judging the data store condition in the memory.

SOLUTION: A D-flip flop at a recognition event signal output part latches a signal outputted from a selector by a clock transmitted through an inverter 352 and outputs it to a read processor or selector, in this case if a first store condition signal empty which has been inputted as a select signal at the selector is under a low state, the recognition event signal output part outputs a recognition event signal oark to the read processor, and if the first store condition signal empty is under a high state, the D-flip flop at the recognition event signal output part latches a signal outputted from the selector and then returns it to the input of the selector.

COPYRIGHT: (C)2000,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control circuit for an asynchronous first-in, first-out memory device, and more particularly, to efficiently control an asynchronous first-in, first-out memory device by using a locally generated local clock. To a control circuit.

[0002]

2. Description of the Related Art In recent years, with the rapid development of multimedia service technology and semiconductor technology, demand and development of services via portable terminals or wireless multimedia terminals have been accelerated. Such services are made possible by ultra-small custom-made semiconductor (ASIC) chips, and the price competitiveness of recently developed ASIC chips and the like is determined by the degree of small size, light weight, and low power consumption. Therefore, when designing hardware, the above requirements must be aligned. In recent decades, the design of almost any digital system has been dominated by synchronous designs that synchronize all operations of the system to a system clock that allows for centralized control and is simple to control. However, in the early days when computers were first developed, digital systems were sometimes designed using asynchronous design techniques. However, asynchronous design has to be controlled locally in various places where data is processed, so the disadvantages of complex design and difficulty in realization have made synchronous design the mainstream. .

[0003]

Furthermore, recently, with the development of semiconductor technology, large-scale logic has been included in one chip. However, control of a clock for controlling an enormous system as a whole has been performed by a semiconductor circuit. It is a heavy burden at the time of design, and the actual overhead for the clock
In some cases, (overhead) became so large that up to about one-third of the logic area of the entire system had to be allocated for clock distribution, which only made the design very complex and difficult. Various problems, such as wasting a lot of power.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. Only a part required by a local clock generated independently is operated locally, and other parts are operated. An object of the present invention is to provide a control circuit for an asynchronous first-in, first-out memory device which prevents unnecessary power consumption and easily solves a clock distribution problem which occurs when designing a large-scale system.

[0005]

SUMMARY OF THE INVENTION A circuit for asynchronously controlling a first-in, first-out (FIFO) memory between a write and a read processor receives a request event signal from the write and a read processor. Clock generating means for generating a clock, a write address pointer signal for receiving a clock from the clock generating means and designating an address where data is stored, and a read address pointer for designating an address where data to be read are stored A write / read address pointer generating means for generating a signal; and a write address pointer signal and a read address pointer signal transmitted from the write / read address pointer generating means by a clock transmitted from the clock generating means. First selecting means for selectively transmitting the data to the memory, a write enable signal for receiving a clock from the clock generating means and writing data to the memory, and a read enable signal for reading data stored in the memory A write / read enable signal generating means for generating a signal and transmitting the signal to the memory; and a write address pointer signal and a read address pointer signal transmitted from the write / read address pointer generating means, to store data in the memory. Receiving a request event signal from the write and read processor according to a clock transmitted from the clock generating means and an output signal of the storage state determining means, and confirming the stored state determining means for determining the stored state; Event information The generated and a confirmation event signal generating means for transmitting to said writing and reading processor, thereby achieving the above object.

The control circuit of the asynchronous first-in first-out memory device according to the present invention includes an inverting means for inverting a clock transmitted from the clock generating means, and a clock transmitted from the clock generating means. Latch means for latching the output data and transmitting the latched data to the read processor.

The clock generating means includes a first clock generator for receiving a request event signal from the write processor and generating a clock, and a second clock generator for receiving the request event signal from the read processor and generating a clock. A clock generator may be provided.

[0008] The first clock generating unit is configured to delay a request event signal transmitted from the write processor, and to delay the request event signal transmitted directly from the write processor via the delay unit. And a clock generator for receiving the request event signal and generating a clock.

The clock generator has a first input terminal connected to an output terminal of the write processor, a second input terminal connected to an output terminal of the delay unit, and the clock processor via the first input terminal. Exclusive OR operation means for exclusive ORing the request event signal directly input from the second input terminal and the request event signal input to the second input terminal with a delay via the delay unit. Good.

[0010] The second clock generating unit may delay the request event signal transmitted from the read processor, and may delay the request event signal transmitted directly from the read processor via the delay unit. And a clock generator for receiving the request event signal and generating a clock.

The clock generator has a first input terminal connected to an output terminal of the read processor, a second input terminal connected to an output terminal of the delay unit, and the read processor via the first input terminal. Exclusive OR operation means for exclusive-ORing the request event signal directly input from the controller and the request event signal input to the second input terminal with a delay via the delay unit. .

The write and read address pointer generator receives the clock transmitted from the first clock generator, generates a write address pointer signal for designating an address where data is stored, and generates the first selector. Write address pointer generating means for transmitting to the storage state discriminating means, receiving the clock transmitted from the second clock generating section, and generating a read address pointer signal for designating an address at which data to be read is stored. A read address pointer generating means for transmitting to the first selecting means and the storage state determining means may be provided.

The write address pointer generating means receives an externally applied initialization signal via a reset terminal, has an input terminal connected to an output terminal of the first clock generation section, and has an output terminal connected to the first selection terminal. Means connected to a first input terminal of the first means and a first input terminal of the storage state discriminating means for counting clocks transmitted from the first clock generating unit, and connecting the first input terminal of the first selection means to the storage state. A first counting means for transmitting the signal to the first input terminal of the determination means may be provided.

The read address pointer generating means receives an externally applied initialization signal via a reset terminal, has an input terminal connected to an output terminal of the second clock generation section, and has an output terminal connected to the first selection terminal. Means connected to a second input terminal of the storage means and a second input terminal of the storage state discriminating means for counting clocks transmitted from the second clock generation unit, and connecting the second input terminal of the first selection means to the storage means. A second counting means for transmitting the signal to the second input terminal of the state determination means may be provided.

The inverting means has an input terminal connected to an output terminal of the first clock generation unit, an output terminal connected to an input terminal of the write / read enable signal generation means, and transmits the signal from the first clock generation unit. A first inverting unit for inverting the received clock and transmitting the inverted clock to the write and read enable signal generating means; an input terminal connected to the output terminal of the second clock generating unit; A second inverting unit connected to the input terminal for inverting a clock transmitted from the second clock generating unit and transmitting the inverted clock to the confirmation event signal generating unit.

The write and read enable signal generating means has an input terminal connected to the output terminal of the first inversion unit, an output terminal connected to the memory, and delays a clock transmitted from the first inversion unit. A delay unit for transmitting the data to the memory.

The latch means receives an externally applied initialization signal via a reset terminal, has a clock terminal connected to an output terminal of the second clock generator, and has an output terminal connected to an input terminal of the read processor. Connected
The memory may further include a D-flip-flop that delays data transmitted from the memory and outputs the delayed data to the read processor.

The storage state determination means compares the magnitude of a write address pointer signal transmitted from the write address pointer generation means with the magnitude of a read address pointer signal transmitted from the read address pointer generation means. Subtracting the read address pointer signal from the write address pointer signal to output a first subtraction value, a second subtraction value obtained by subtracting the read address pointer signal from the maximum address of the memory, and the write address pointer signal. Adding and subtracting means for outputting an addition value obtained by adding the following, a second selecting means for selectively transmitting an output signal of the adding and subtracting means according to an output signal of the first comparing means, and an output of the second selecting means. Compare whether the signal and the predetermined reference value are the same, and Second comparing means for transmitting a first storage state signal indicating the separated data storage state of the memory to the acknowledgment event signal generating means, and an output signal of the second selecting means and a preset maximum address of the memory. A third storage state signal indicating a data storage state of the memory determined by the comparison result to the confirmation event signal generating means;
A comparison means may be provided.

The second comparing means, if the output signal of the second selecting means is equal to a predetermined reference value, indicates that there is no data stored in the memory. And outputting a signal to the confirmation event signal generation means. If the output signal of the second selection means is larger than a predetermined reference value, the first storage state signal in a low state indicating that data is stored in the memory. May be output to the confirmation event signal generating means.

If the output signal of the second selecting means is equal to a preset address maximum value of the memory, the third comparing means indicates that data has been stored at any address of the memory. The second in a high state
A storage state signal is output to the confirmation event signal generation means. If the output signal of the second selection means is smaller than a preset address maximum value of the memory, there is an address where data is not stored in the memory. May be output to the confirmation event signal generating means.

The acknowledgment event signal generating means is configured to output a request event from the write processor in response to a clock inverted and transmitted through the first inverting unit and a first storage state signal transmitted from the second comparing means. Receiving a signal, generating a first confirmation event signal indicating that data has been received, transmitting the first confirmation event signal to the write processor, and inverting the first confirmation event signal through the second inverter. Receiving a request event signal from the read processor according to the received clock and the second storage state signal transmitted from the third comparing means,
A second acknowledgment event signal generator for generating a second acknowledgment event signal indicating that data has been received and transmitting the second acknowledgment event signal to the read processor.

The first acknowledgment event signal generating unit may be configured to, based on the first storage state signal transmitted from the second comparing means, convert the request event signal transmitted from the write processor and the output signal of the acknowledgment event signal output unit. A first selector for selectively transmitting the first signal and a clock inverted and transmitted via the first inverter,
A confirmation event signal output unit for receiving an output signal of the selection unit and outputting the first confirmation event signal to the write processor.

The acknowledgment event signal output section is provided with the first
A latch unit may be provided for latching an output signal of the first selecting unit by a clock inverted and transmitted through the inverting unit.

The latch unit receives an externally applied initialization signal via a reset terminal, has an input terminal connected to an output terminal of the first selection unit, and has a clock terminal connected to an output terminal of the first inversion unit. And a D-flip-flop having an output terminal commonly connected to an input terminal of the write processor and an input terminal of the first selection unit.

The first selector transmits the request event signal transmitted from the write processor to the input terminal of the latch when the first storage state signal in the low state is transmitted from the second comparator. When a first storage state signal in a high state is transmitted from the second comparing means, a signal fed back from the latch unit may be transmitted to an input terminal of the latch unit.

The second acknowledgment event signal generator may be configured to, based on the second storage state signal transmitted from the third comparing means, convert the request event signal transmitted from the read processor and the output signal of the acknowledgment event signal output unit. A second selecting unit for selectively transmitting the second inverted signal, and a clock inverted and transmitted through the second inverting unit.
A confirmation event signal output unit for receiving an output signal of the selection unit and outputting the second confirmation event signal to the read processor.

The acknowledgment event signal output unit is configured to output the second
A latch unit may be provided for latching an output signal of the second selection unit in response to a clock inverted and transmitted through the inversion unit.

The latch unit receives an externally applied initialization signal via a reset terminal, has an input terminal connected to an output terminal of the second selection unit, and has a clock terminal connected to an output terminal of the second inversion unit. And a D-flip-flop having an output terminal commonly connected to an input terminal of the read processor and an input terminal of the second selection unit.

The second selector transmits a request event signal transmitted from the read processor to an input terminal of the latch when the second storage state signal in a low state is transmitted from the third comparing means. The signal returned from the latch unit may be transmitted to an input terminal of the latch unit when a second storage state signal in a high state is transmitted from the third comparison unit.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating an asynchronous first-in, first-out memory device to which the present invention is applied. A transmitting processor 110 (hereinafter, referred to as a "write processor") and a receiving processor 120 (hereinafter, referred to as a "write processor"). An SRAM 140 as a first-in, first-out (FIFO) memory for asynchronously exchanging data with a "read processor") and a FIFO control for controlling the same. And a circuit 130.

In general, in the case of an asynchronous circuit, when data is exchanged, a data request signal and a data confirmation signal are simultaneously exchanged in addition to a data signal to confirm the operation between the sender and the sender. Performs communication between and the recipient. This is called "handshaking (hand
That is, when outputting the processed data, the sender 110 simultaneously outputs a predetermined request signal ireq to the FIFO control circuit 130 so that the availability of the data can be known, and the transmitter 110 Confirmation signal i for it
After receiving the acknowledgment, the next data is processed and transmitted. Then, the receiver 120 sends a predetermined request signal oreq to the FIFO control circuit 130 at the time when the receiver 120 desires the data processing, and outputs a confirmation signal together with the FIFO control circuit 130 when the FIFO control circuit completes the data processing and outputs it. After receiving the oack, the next data is processed and received.

Hereinafter, the operation of the asynchronous first-in first-out device having the above-described structure will be described in detail with reference to FIG.

FIG. 2 is a flowchart illustrating the operation of the asynchronous first-in first-out device of FIG.

As shown in FIG. 2, first, the write and read processors 110 and 120, the control circuit 130 and the FIFO
The memory (SRAM) 140 is initialized (Step 201). At this time, the logical voltage level of all events is set to '
It becomes 0 'state. After that, the above FIFO control circuit 130 is used to write the read processor 110 or the read processor 1
It is determined whether the request event signal ireq or oreq from 20 has been input (step 202). Write Processor 110
If the request event signal ireq from the
The FO control circuit 130 generates an address signal addr and a write enable signal web for processing a request event from the write processor 110, and data applied from the write processor 110 is recorded in a FIFO memory (SRAM) 140. In addition, a confirmation signal iack indicating that the request event signal has been safely processed is transmitted to the write processor 110 (steps 203 and 20).
Four).

If the request event signal is the request event signal oreq from the read processor 120, the FIFO control circuit 130 generates an address signal addr to process the request event signal oreq from the read processor 120. Then, the designated data is read from the FIFO memory (SRAM) 140 and the read processor is read.
Signal oack for transmitting to 120 and confirming data output
Is output to the reading processor 120 (steps 203 and 204).

On the other hand, in the input judgment step (206) of the request event signal oreq from the read processor 120, the request event signal ore from the read processor 120 is determined.
If it is not q, the process returns to the step (202) of determining the input of the request event signal ireq from the write processor 110.

FIG. 3 is a block diagram of an embodiment showing a schematic configuration of a control circuit of the asynchronous first-in first-out memory device according to the present invention.

FIG. 3 is a block diagram of a control device of the asynchronous first-in first-out system according to one embodiment of the present invention.

As shown in FIG. 3, the control circuit of the asynchronous first-in first-out memory device of the present invention includes a write processor 11.
A first clock generator 310 for receiving the request event signal ireq from 0 to generate a clock, a second clock generator 320 for receiving the request event signal oreq from the read processor 120 and generating a clock, A write address pointer generator 330 that receives a clock transmitted from the clock generator 310 and generates a write address pointer signal wptr for specifying an address for storing data, and a clock transmitted from the second clock generator 320 A read address pointer generator 340 that generates a read address pointer signal rptr for specifying an address at which data to be received and read is stored.
An input terminal connected to the output terminal of the first clock generation unit 310, an inverter 351 for inverting the clock transmitted from the first clock generation unit 310, and an input terminal connected to the output terminal of the second clock generation unit 320 And an inverter 352 for inverting the clock transmitted from the second clock generator 320, a first input terminal connected to the output terminal of the write address pointer generator 330, and a second input terminal connected to the read address pointer. The selection terminal is connected to the output terminal of the first clock generation unit 310, and the selection terminal is connected to the output terminal of the first clock generation unit 310.
According to the clock transmitted from the clock generator 310,
A selector for selectively transmitting the write address pointer signal wptr transmitted from the write address pointer generator 330 and the read address pointer signal rptr transmitted from the read address pointer generator 340 to the FIFO memory (SRAM) 140. 353, receives a clock from the inverter 351 and generates a write enable signal web for writing data in the FIFO memory (SRAM) 140 and a read enable signal reb for reading data stored in the SRAM 140 to generate the FIFO memory ( The write and read enable signal generation unit 354 transmitted to the SRAM 140 and the clock transmitted from the second clock generation unit 340
A latch unit 360 that latches the data FIFOOUT output from the O memory (SRAM) 140 and transmits it to the read processor 120
Using the write address pointer signal wptr transmitted from the write address pointer generator 330 and the read address pointer signal rptr transmitted from the read address pointer generator 340, the FIFO memory (SRAM) 140
A storage state determination unit 370 for determining a state in which data is stored in the memory, and a request event from the write processor 110 based on the clock wiclk transmitted from the first clock generation unit 310 and the output signal full of the storage state determination unit 370. Signal i
The first confirmation event signal generator 380 which receives the req to generate the confirmation event signal iack, and transmits the confirmation event signal iack to the write processor 110; the clock riclk transmitted from the second clock generator 320; According to the output signal empty of the determination unit 370, the request event signal oreq is received from the read processor 120, and the confirmation event signal oack is generated.
To the read processor 120.

The first clock generator 310 is configured to delay the request event signal ireq transmitted from the write processor 110, and to transmit the request event signal ireq transmitted directly from the write processor 110 and the delay unit 311. A clock generator 312 is provided for receiving the delayed request event signal and generating a clock.

The clock generator 3 of the first clock generator 310
12 is an exclusive OR for exclusive ORing the request event signal ireq directly input from the write processor 110 via one input terminal and the request event signal input to the other input terminal with a delay via the delay unit 311. It is composed of an OR gate XOR1.

The second clock generator 320 is provided with a delay unit 321 for delaying the request event signal oreq transmitted from the read processor 120, and a request event signal oreq transmitted directly from the read processor 120 and the delay unit 321. And a clock generator 322 for receiving the delayed request event signal and generating a clock.

Clock generator 3 of second clock generator 320
Reference numeral 22 denotes an exclusive OR for exclusive ORing the request event signal oreq input directly from the read processor 120 via one input terminal and the request event signal input to the other input terminal with a delay via the delay unit 321. Logical OR gate XOR2.

The write address pointer generator 330
An initialization signal init applied from the outside is received via a reset terminal, an input terminal is connected to an output terminal of an exclusive OR gate 312 of the clock generation unit 310, and an output terminal is connected to a first input terminal of the selection unit 353. A counter 33 that is connected and counts the clock transmitted from the clock generator 310.
With 1.

The read address pointer generating section 340
An initialization signal init applied from the outside is received via a reset terminal, an input terminal is connected to an output terminal of the exclusive OR gate 322 of the clock generation unit 320, and an output terminal is connected to a second input terminal of the selection unit 353. A counter 34 connected to count the clock transmitted from the clock generator 320.
With 1.

The write and read enable signal generator 354 has an input terminal connected to the output terminal of the inverter 351 and an output terminal connected to the FIFO memory (SRAM) 140 to delay the clock wiclk transmitted from the inverter 351. (Not shown).

The latch section 360 receives an externally applied initialization signal init via a reset terminal, and connects the clock terminal to the exclusive OR gate XOR of the second clock generation section 320.
2 and an output terminal connected to the input terminal of the read processor 120 and a D-flip-flop 361 for delaying data transmitted from the FIFO memory (SRAM) 140.

The storage state determining unit 370 will be described in detail with reference to FIG.

First and second confirmation event signal generator 380
And 390 are described in detail with reference to FIGS. 5A and 5B.

The operation of the control circuit of the asynchronous first-in first-out memory device of the present invention having the above-described structure will be described in detail below.

The first clock generator 310 receives the request event signal ireq transmitted from the write processor 110 and generates a clock, and then generates the clock via the write address pointer generator 330, the selector 353, and the inverter 351. The write and read enable signal generator 354 and the first confirmation event signal generator 380 are transmitted. Further, the second clock generator 320 receives the request event signal oreq transmitted from the read processor 120, generates a clock, and then generates the clock via the read address pointer generator 340, the latch 360, and the inverter 352. It is transmitted to the second confirmation event signal generator 390.

The write address pointer generator 330
The write address pointer signal wptr is generated using the clock transmitted from the first clock generator 310, and the write address pointer signal wptr is transmitted to the selector 353 and the storage state determiner 370. In addition, the read address pointer generator 340 receives the clock transmitted from the second clock generator 320, generates a read address pointer signal, and transmits this to the selector 353 and the storage state determiner 370.

The selection unit 353 uses the clock transmitted from the first clock generation unit 310 to generate the write address pointer signal wptr transmitted from the write address pointer generation unit 330 and the read address pointer signal transmitted from the read address pointer generation unit 340. rptr above FIFO
The signal is selectively transmitted to the memory (SRAM) 140. That is, the first
When a clock in a high state is transmitted from the clock generator 310, the selector 353 transmits the write address pointer signal wptr transmitted from the write address pointer generator 330 to the FIFO memory (SRAM) 140, When a low clock is transmitted from the first clock generator 310, the selector 353 transmits the read address pointer signal rptr transmitted from the read address pointer generator 340 to the FIFO memory (SRAM) 140. I do. Here, the output signal of the selection unit 353 is stored in the FIFO memory (SR
AM) 140 is a signal for specifying the address.

Using the write address pointer signal wptr transmitted from the write address pointer generator 330, the storage state determiner 370 determines whether there is an address in the FIFO memory (SRAM) 140 where data can be stored. Then, the determination result is transmitted to the first and second confirmation event signal generators 380 and 390. Further, the storage state determination unit 370 receives the read address pointer signal rptr transmitted from the read address pointer generation unit 340,
It is determined whether there is data stored in the FIFO memory (SRAM) 140, and the result of the determination is transmitted to the first and second confirmation event signal generators 380 and 390.

The write / read enable signal generation unit 354 uses a clock transmitted through the inverter 351 to write a write enable signal web for writing data to the FIFO memory (SRAM) 140 and the FIFO memory (SRAM) 1.
A read enable signal reb for reading data stored in 40 is generated, and the write enable signal web and the read enable signal reb are transmitted to the FIFO memory (SRAM) (140).
To communicate.

As described above, when the read enable signal reb is transmitted from the write / read enable signal generator 354, the FIFO memory (SRAM) 140 turns the selector 353.
When the data stored at the address specified by the address signal transmitted from is transmitted to the read processor 120 via the latch unit 360, and when the write enable signal web is transmitted from the write and read enable signal generation unit 354, The FIFO memory (SRAM) 140 includes a selection unit 353
The data transmitted from the write processor 110 is stored in the address designated by the address signal transmitted from the write processor 110.

The first acknowledgment event signal generator 380 uses the request event signal ireq transmitted from the write processor 110 according to the clock wiclk transmitted from the first clock generator 310 and the output signal full from the storage state discriminator 370. Then, a confirmation event signal iack is generated, and the confirmation event signal iack is transmitted to the write processor 110. Also, the second acknowledgment event signal generation unit 390 is configured to control the clock riclk transmitted from the second clock generation unit 320 and the storage state determination unit.
Readout processor by 370 output signal empty
After generating the confirmation event signal oack using the request event signal oreq transmitted from 120, the confirmation event signal
The oack is transmitted to the read processor 120.

FIG. 4 is a block diagram of an embodiment of the storage state determining unit shown in FIG.

As shown in FIG. 4, the storage state determining unit of FIG. 3 includes a write address pointer signal wptr transmitted from the write address pointer generator 330 and a read address pointer signal rptr transmitted from the read address pointer generator 340. And a first comparison unit 410 for comparing the magnitudes of the read address pointer signal rptr transmitted from the read address pointer generation unit 340 with the write address pointer signal wptr transmitted from the write address pointer generation unit 330. And the first subtraction value wptr-rpt
r, and outputs the maximum address SRAMde of the FIFO memory 140.
A second value obtained by subtracting the read address pointer signal rptr transmitted from the read address pointer generation unit 340 from pth
The subtracted value SRAMdepth-rptr and the write address pointer signal wpt transmitted from the write address pointer generator 330
and an addition / subtraction unit 420 that outputs the added value SRAMdepth-rptr + wptr, and an output signal of the first comparison unit 410.
Output signal wptr-rptr and SRAM depth-rptr + w of addition / subtraction unit 420
a selector 430 for selectively transmitting the ptr, and a selector 430
Is compared with a predetermined reference value, and a first storage state signal empty indicating a data storage state of the esram (SRAM) 140 determined based on the comparison result is transmitted to the second confirmation event signal generator 390. A second comparing unit 440, and a selecting unit 430
Output signal and the previously set FIFO memory 140
A third storage state signal full indicating the data storage state of the FIFO memory 140 determined by the comparison result is transmitted to the first confirmation event signal generation unit 380. A comparison unit 450.

Here, the predetermined reference value set at one input terminal of the second comparing section 440 is a decimal number '0'.

Hereinafter, the operation of the storage state determining unit having the above-described structure shown in FIG. 3 will be described in detail.

The first comparing section 410 compares the magnitude of the write address pointer signal wptr transmitted from the write address pointer generating section 330 with the magnitude of the read address pointer signal rptr transmitted from the read address pointer generating section 340. The result is output to the selection unit 430 so as to be used in the selection signal of the selection unit 430. That is, if the write address pointer signal wptr is larger than the read address pointer signal rptr, the first comparing section 410 outputs '1' to the selecting section 430, and if the write address pointer signal wptr is smaller than the read address pointer signal rptr, 1 comparison section 410 outputs '0' to selection section 430.

The adder / subtractor 420 subtracts the read address pointer signal rptr transmitted from the read address pointer generator 340 from the write address pointer signal wptr transmitted from the write address pointer generator 330, Selector 4 for 1 subtraction value wptr-rptr
Output to 20. The addition / subtraction unit 420 is provided in the FIFO memory 140.
After subtracting the read address pointer signal rptr transmitted from the read address pointer generator 340 from the address maximum value SRAMdepth of the above, a write address pointer generator is added to the second subtraction value SRAMdepth-rptr thus subtracted.
Write address pointer signal wptr transmitted from 330
And the added value SRAMdepth-rptr + wptr is selected by the selection unit 430.
Output to

Then, the selection section 430 outputs two output signals wptr-rptr of the addition / subtraction section 420 according to the output signal of the first comparison section 410.
And SRAMdepth-rptr + wptr are compared with the second and third comparing units 440 and
Communicate selectively to 450. At this time, the first comparison unit 410
When 0 ′ is transmitted, the selection unit 430 compares the subtraction value wptr-rptr output from the addition / subtraction unit 420 with the second and third comparison units 440.
And 450, and when “1” is transmitted from the first comparing unit 410, the selecting unit 430 outputs the added value output from the adding / subtracting unit 420.
SRAMdepth-rptr + wptr is compared with the second and third comparison units 440 and 450
To communicate.

Next, the second comparing unit 440 compares the output signal of the selecting unit 430 with a predetermined reference value, and determines the first storage indicating the data storage state of the FIFO memory 140 determined based on the comparison result. The status signal empty is output to the second confirmation event signal generator 390, and the third comparator 450 compares the magnitude of the output signal of the selector 430 with the preset address maximum value SRAMdepth of the FIFO memory 140. The second storage state signal full indicating the data storage state of the FIFO memory 140 determined based on the comparison result is output to the first confirmation event signal generator 380.

The subtraction value wptr-rp output from the addition / subtraction unit 420
tr is passed through the selection unit 430 to the second and third comparison units 440 and 450
And the addition value S output from the addition / subtraction unit 420.
RAMdepth-rptr + wptr is passed through the selection unit 430 to the second and third
The case where the information is transmitted to the comparison units 440 and 450 will be described in detail.

First, the subtraction value w output from the addition / subtraction unit 420
A case where ptr-rptr is transmitted to the second and third comparing units 440 and 450 will be described.

The second comparing section 440 is provided with a predetermined reference value and the selecting section 4.
The first storage state signal empty indicating the data storage state of the esram 140 determined based on the comparison result is compared with the subtraction value wptr-rptr transmitted through 30 and transmitted to the second confirmation event signal generator 390. Output. That is, if the predetermined reference value is larger than the subtraction value wptr-rptr, the second comparison unit 440
Transmits the low state of the first storage state signal empty to the second state.
Output to the confirmation event signal generation unit 390, the predetermined reference value (0)
And the subtraction value wptr-rptr are the same, the second comparing unit 440 outputs the first storage state signal empty in the high state to the second state.
Output to the confirmation event signal generator 390.

The third comparing section 450 compares the preset maximum address SRAMdepth of the FIFO memory 140 with the magnitude of the subtraction value wptr-rptr transmitted via the selecting section 430, and compares the comparison result. The second storage state signal full indicating the data storage state of the FIFO memory 140 determined by the above is output to the first confirmation event signal generator 380. That is, if the preset address maximum value SRAMdepth of the FIFO memory 140 is smaller than the subtraction value wptr-rptr,
The third comparing unit 450 outputs the second storage state signal full in a low state to the second confirmation event signal generating unit 390, and sets a preset address maximum value SRAM # depth of the FIFO memory 140 and a subtraction value wptr. If -rptr is the same, the third
The comparing unit 450 outputs the second storage state signal f in a high state.
ull is output to the first confirmation event signal generator 380.

Next, the addition value S output from the addition / subtraction unit 420
The case where RAMdepth-rptr + wptr is transmitted to the second and third comparing units 440 and 450 will be described in detail.

The second comparing section 440 determines whether a predetermined reference value is
30 and compares the sum with the magnitude of the SRAMdepth-rptr + wptr transmitted through 30 and the FIFO determined by the comparison result.
A first storage state signal emp indicating a data storage state of the memory 140
ty is output to the second confirmation event signal generator 390. That is, if the predetermined reference value is greater than the sum value SRAMdepth-rptr + wptr, the second comparing unit 440 outputs the low first storage state signal empty to the second confirmation event signal generation unit 390.
And the predetermined reference value and the added value SRAM # depth-rptr + wptr
If the values are the same, the second comparing unit 440 outputs the first storage state signal empty in a high state to the second confirmation event signal generation unit 390.

Further, the third comparing section 450 sets the address maximum value SRAMdepth of the preset esram 140 and the selecting section 43
The second storage state signal full indicating the data storage state of the FIFO memory 140 determined by comparing the sum of the sum value SRAMdepth-rptr + wptr transmitted through 0 and the result of the comparison.
To the first confirmation event signal generation unit 380. In other words, if the preset address maximum value SRAMdepth of the FIFO memory 140 is smaller than the sum value SRAMdepth-rptr + wptr, the third comparing unit 450 sets the second state in the low state.
The storage state signal full is output to the second confirmation event signal generation section 390, and if the preset address maximum value SRAMdepth of the FIFO memory 140 and the addition value SRAMdepth-rptr + wptr are the same, the third comparison section 450 The second storage state signal full in a high state is converted to a first confirmation event signal generation unit.
Output to 380.

FIG. 5A is a block diagram of one embodiment of the first acknowledgment event signal generator shown in FIG.

As shown in FIG. 5A, the first acknowledgment event signal generator of FIG.
A selection unit 510 for selectively transmitting the request event signal transmitted from 110 and the output signal of the confirmation event signal output unit 520, and a selection unit 510 by the clock wiclk inverted and transmitted via the inverter 351. And outputs the first confirmation event signal to the processor 11
And a confirmation event signal output unit 520 for outputting 0.

The confirmation event signal output unit 520 receives an externally applied initialization signal via a reset terminal, and has an input terminal connected to the output terminal of the selection unit 510, and a clock terminal connected to the output terminal of the inverter 351. The D-flip-flop 521 has an output terminal commonly connected to an input terminal of the write processor 110 and an input terminal of the selection unit 510.

The operation of the first acknowledgment event signal generator of FIG. 3 having the above-described structure will be described in detail below.

The selecting section 510 outputs a low (L) signal from the third comparing section 450.
ow) When the second storage state signal full of the state is transmitted, the request event signal ireq transmitted from the write processor 110 is selected and transmitted to the input terminal of the D-flip-flop 521 of the confirmation event signal output unit 520. . Also, when the second storage state signal full in the low state is transmitted from the third comparing unit 450, the output signal iack of the confirmation event signal output unit 520 is selected, and D of the confirmation event signal output unit 520 is selected. -Transmit to the input terminal of flip-flop 521.

Next, the D- of the confirmation event signal output unit 520
The flip-flop 521 latches the signal output from the selection unit 510 according to the clock transmitted through the inverter 351 and writes the latched signal to the write processor 11.
Output to 0 or selection section 510. At this time, if the second storage state signal full input as the selection signal of the selection unit 510 is in a low state, the confirmation event signal output unit 520
Outputs the confirmation event signal iack to the write processor 110, and if the second storage state signal full input as the selection signal of the selection unit 510 is high, the D-flip-flop of the confirmation event signal output unit 520 521 latches the signal input from the selection unit 510, and then selects
Return to the input terminal of 10.

FIG. 5B is a block diagram of an embodiment of the second acknowledgment event signal generator shown in FIG.

As shown in FIG. 5B, the second acknowledgment event signal generator of FIG.
The storage state signal empty causes the read processor 120
The selection unit 610 for selectively transmitting the request event signal oreq transmitted from the ACK and the output signal oack of the confirmation event signal output unit 620, and the clock riclk inverted and transmitted via the inverter 352, the selection unit A confirmation event signal output unit 620 for receiving the output signal of 610 and outputting the second confirmation event signal oack to the read processor 120
And

The confirmation event signal output unit 620 receives an externally applied initialization signal init via a reset terminal, has an input terminal connected to the output terminal of the selection unit 610, and has a clock terminal connected to the output terminal of the inverter 352. A D-flip-flop 621 connected to the input terminal of the read processor 120 and the input terminal of the selection unit 610 is provided.

The operation of the second confirmation event signal generator of FIG. 3 having the above-described structure will be described in detail below.

The selecting section 610 outputs the low (L
ow) When the first storage state signal empty in the state is transmitted, the request event signal oreq transmitted from the read processor 120 is selected and transmitted to the input terminal of the D-flip-flop 621 of the confirmation event signal output unit 620. . Also, when the low state first storage state signal “empty” is transmitted from the second comparing unit 440, the output signal of the confirmation event signal output unit 620 is selected and the D-level of the confirmation event signal output unit 620 is selected. The signal is transmitted to the input terminal of the flip-flop 621.

Next, the D- of the confirmation event signal output unit 620
The flip-flop 621 latches the signal output from the selection unit 610 according to the clock transmitted through the inverter 352, reads the latched signal, and reads the latched signal.
Alternatively, output to selection section 610. At this time, if the first storage state signal empty input as the selection signal of the selection unit 610 is in a low state, the confirmation event signal output unit 620.
Outputs the confirmation event signal oack to the read processor 120, and if the first storage state signal empty inputted as the selection signal of the selection unit 610 is in a high state, the D-flip-flop of the confirmation event signal output unit 620 The 621 latches the signal input from the selection unit 610 and then feeds it back to the input terminal of the selection unit 610.

FIG. 6 is an operation timing chart of the asynchronous first-in first-out memory device control circuit shown in FIG. In the figure, FIFOIN is transmitted from the write processor 110 to the F
Data input to the IFO memory 140, init is an externally applied initialization signal, ireq is a request event signal input from the write processor 110 to the control device 130, and direq is a first clock generation unit. 310 delay part 311
Cclk is a clock output from the first clock generation unit 310, and wptr
Is a write address pointer signal generated from the write address pointer generator 330, rptr is a read address pointer signal generated from the read address pointer generator 340, and addr is an address signal output from the selector 353. , Web are write enable signals generated by the write and read enable signal generator 354.

As described above, the present invention relates to a control circuit for an asynchronous first-in first-out memory device, and more particularly to a control circuit for efficiently controlling an asynchronous first-in-first-out memory device using a local clock generated independently. Circuit. According to the control circuit of the present invention, not only can the first-in-first-out memory device be implemented with a smaller amount of memory than in the case of the conventional synchronous first-in-first-out memory device, By operating only the necessary parts, the system can be efficiently controlled and unnecessary power consumption can be prevented. In addition, it is possible to effectively solve a complicated clock distribution problem when implementing a video and audio processing system of a portable wireless terminal or a multimedia terminal by using an ASIC.

Although the technical idea of the present invention has been specifically described by the above-described preferred embodiments, it should be noted that the above-described embodiment is for the purpose of explanation and is not intended to limit the present invention. Also, those skilled in the art of the present invention can understand that various embodiments are possible within the scope of the technical idea of the present invention.

[0089]

As described above, according to the present invention, not only the conventional synchronous first-in-first-out memory device but also the first-in-first-out memory device can be realized with a smaller amount of memory, and the self-generated first-in-first-out memory device is generated independently. By using the local clock to operate only the necessary parts, the system can be efficiently controlled and unnecessary power consumption can be prevented, and the video and audio processing system for portable wireless terminals and multimedia terminals In realizing such as an ASIC, complicated problems of clock distribution can be effectively solved.

[Brief description of the drawings]

FIG. 1 is a block diagram of an asynchronous first-in first-out device to which the present invention is applied.

FIG. 2 is a flowchart for explaining an operation process of the asynchronous first-in first-out device shown in FIG.

FIG. 3 is a block diagram of an embodiment showing a schematic configuration of a control circuit of the asynchronous first-in first-out memory device according to the present invention;

FIG. 4 is a block diagram illustrating an example of a storage state determination unit illustrated in FIG. 3;

FIG. 5 is a block diagram illustrating an example of first and second event signal generators illustrated in FIG. 3; FIG. 5A shows a first confirmation event signal generator, and FIG. 5B shows a second confirmation event signal generator.

6 is an operation timing diagram of the asynchronous first-in first-out memory device control circuit shown in FIG. 3;

[Explanation of symbols]

 310 First clock generator 320 Second clock generator 330 Write address pointer generator 340 Read address pointer generator 351, 352 Inverter 353 Selector 354 Write / read enable signal generator 360 Latch 370 Storage state discriminator 380 First Confirmation event signal generator 390 Second confirmation event signal generator

Claims (25)

[Claims] 1. A circuit for asynchronously controlling a first-in first-out memory provided between a write and a read processor, comprising: a clock generating means for receiving a request event signal from the write and a read processor and generating a clock. And a write and read address pointer for receiving a clock from the clock generation means and generating a write address pointer signal for specifying an address where data is stored and a read address pointer signal for specifying an address where data to be read are stored. Generating means, and a write address pointer signal and a read address pointer signal transmitted from the write and read address pointer generating means are selectively transmitted to the memory by a clock transmitted from the clock generating means. Receiving the clock from the clock generating means, generating a write enable signal for writing data in the memory, and a read enable signal for reading data stored in the memory; A state in which data is stored in the memory by using a write and read enable signal generating means to be transmitted to the memory; and a write address pointer signal and a read address pointer signal transmitted from the write and read address pointer generating means. A storage state determining unit for determining, and a request event signal from the write and read processor, and a confirmation event signal generated by the clock transmitted from the clock generation unit and the output signal of the storage state determination unit. , The book The control circuit of the asynchronous FIFO memory device and a confirmation event signal generating means for transmitting the write and read processor. 2. An inverting unit for inverting a clock transmitted from the clock generating unit, and latching data output from the memory and transmitting the latched data to the read processor in accordance with the clock transmitted from the clock generating unit. 2. The control circuit according to claim 1, further comprising: latch means for performing the operation. 3. The first clock generator for receiving a request event signal from the write processor and generating a clock, and a clock generator for receiving the request event signal from the read processor and generating a clock. 3. The control circuit according to claim 1, further comprising a second clock generator. 4. The first clock generation unit includes: a delay unit for delaying a request event signal transmitted from the write processor; and a request event signal transmitted directly from the write processor and the delay unit. 4. The control circuit according to claim 3, further comprising: a clock generator for receiving the delayed request event signal and generating a clock. 5. The clock generator, wherein a first input terminal is connected to an output terminal of the write processor, a second input terminal is connected to an output terminal of the delay unit, and the clock generator is connected via the first input terminal. Exclusive OR operation means for exclusive ORing a request event signal directly input from a write processor and a request event signal input to the second input terminal with a delay via the delay unit. Item 5. A control circuit for an asynchronous first-in first-out memory device according to item 4. 6. The delay circuit for delaying a request event signal transmitted from the read processor, the second clock generator, a request event signal transmitted directly from the read processor, and the delay unit. 4. The control circuit according to claim 3, further comprising a clock generator configured to receive the delayed request event signal and generate a clock. 7. The clock generator, wherein a first input terminal is connected to an output terminal of the read processor, a second input terminal is connected to an output terminal of the delay unit, and the clock generator is connected via the first input terminal. An exclusive OR operation means for exclusive ORing a request event signal directly input from a read processor and a request event signal input to the second input terminal with a delay via the delay unit. 7. The control circuit of the asynchronous first-in first-out memory device according to 6. 8. The write and read address pointer generating means receives a clock transmitted from the first clock generating unit, generates a write address pointer signal for designating an address where data is stored, and generates the first and second address pointer signals. A write address pointer generating means for transmitting to the selecting means and the storage state determining means; receiving a clock transmitted from the second clock generating unit, and generating a read address pointer signal for designating an address where data to be read is stored. 4. The control circuit for an asynchronous first-in first-out memory device according to claim 3, further comprising read address pointer generating means for transmitting the read address pointer to said first selecting means and storage state determining means. 9. The write address pointer generating means receives an externally applied initialization signal via a reset terminal, has an input terminal connected to an output terminal of the first clock generation section, and has an output terminal connected to the first clock generation section. A first input terminal of the first selection unit is connected to a first input terminal of the first selection unit and a first input terminal of the storage state determination unit, and counts a clock transmitted from the first clock generation unit. 9. The control circuit according to claim 8, further comprising first counting means for communicating with the first input terminal of the storage state determining means. 10. The read address pointer generating means receives an externally applied initialization signal via a reset terminal, has an input terminal connected to an output terminal of the second clock generation section, and has an output terminal connected to the second terminal. 1 is connected to a second input terminal of the first selection means and a second input terminal of the storage state determination means, counts clocks transmitted from the second clock generation unit, and counts the second input terminal of the first selection means. 10. The control circuit according to claim 9, further comprising second counting means for communicating with the second input terminal of the storage state judging means. 11. The inverting means has an input terminal connected to an output terminal of the first clock generator,
An output terminal connected to an input terminal of the write and read enable signal generating means, a first inverting part for inverting a clock transmitted from the first clock generating part and transmitting the inverted clock to the write and read enable signal generating means; An input terminal is connected to an output terminal of the second clock generator,
3. An output terminal connected to an input terminal of the confirmation event signal generating means, comprising a second inverting section for inverting a clock transmitted from the second clock generating section and transmitting the inverted clock to the confirmation event signal generating means. 3. A control circuit for an asynchronous first-in first-out memory device according to claim 1. 12. The write / read enable signal generating means has an input terminal connected to an output terminal of the first inversion unit, an output terminal connected to the memory, and a clock transmitted from the first inversion unit. 4. The control circuit according to claim 3, further comprising a delay unit for delaying the transmission to the memory. 13. The latch means receives an externally applied initialization signal via a reset terminal, a clock terminal connected to an output terminal of the second clock generator, and an output terminal connected to an input terminal of the read processor. 3. The control circuit according to claim 2, further comprising a D-flip-flop connected to an end and delaying the data transmitted from the memory and outputting the delayed data to the read processor. 14. The storage state determining means compares the magnitude of a write address pointer signal transmitted from the write address pointer generating means with a magnitude of a read address pointer signal transmitted from the read address pointer generating means. Comparing means for subtracting the read address pointer signal from the write address pointer signal to output a first subtraction value, a second subtraction value obtained by subtracting the read address pointer signal from the maximum address of the memory, and the write address Addition / subtraction means for outputting an added value obtained by adding a pointer signal; second selection means for selectively transmitting an output signal of the addition / subtraction means based on an output signal of the first comparison means; and second selection means Compare whether the output signal is the same as the predetermined reference value, and Second comparing means for transmitting a first storage state signal indicating the data storage state of the memory determined to the acknowledgment event signal generating means, an output signal of the second selecting means and a preset address of the memory And a third comparing means for comparing whether or not the maximum value is the same and transmitting a second storage state signal indicating a data storage state of the memory determined by the comparison result to the confirmation event signal generating means. 4. The control circuit of the asynchronous first-in first-out memory device according to 3. 15. The second comparing means, if the output signal of the second selecting means is equal to a predetermined reference value, indicates that there is no data stored in the memory. Outputting a storage state signal to the acknowledgment event signal generating means; if an output signal of the second selecting means is greater than a predetermined reference value, the first storage in a low state indicating that data is stored in the memory; 15. The control circuit according to claim 14, wherein a status signal is output to said confirmation event signal generating means. 16. The third comparing means, if the output signal of the second selecting means is equal to a preset address maximum value of the memory, the data is stored at any address of the memory. And outputting the second storage state signal in a high state to the acknowledgment event signal generating means. If the output signal of the second selecting means is smaller than a preset address maximum value of the memory, data is stored in the memory. 16. The control circuit of claim 15, wherein the second storage state signal in a low state indicating that there is an unstored address is output to the confirmation event signal generating means. . 17. The write event processor according to claim 1, wherein the acknowledgment event signal generating unit is configured to output the acknowledgment signal from the write processor based on a clock inverted and transmitted through the first inverting unit and a first storage state signal transmitted from the second comparing unit. Receiving a request event signal to indicate that data has been received;
A first acknowledgment event signal generating unit for generating a acknowledgment event signal and transmitting the same to the write processor; a clock inverted and transmitted through the second inverting unit; and a second storage transmitted from the third comparing unit. And a second acknowledgment signal generator for receiving a request event signal from the read processor according to a status signal, generating a second acknowledgment event signal indicating that data has been received, and transmitting the second acknowledgment event signal to the read processor. 4. The control circuit of the asynchronous first-in first-out memory device according to 3. 18. The first acknowledgment event signal generating unit may include a request event signal transmitted from the write processor and an output signal of a acknowledgment event signal output unit according to the first storage state signal transmitted from the second comparing unit. And a first selector for selectively transmitting the first acknowledgment signal and receiving the output signal of the first selector in response to a clock inverted and transmitted through the first inverter. The control circuit of an asynchronous first-in first-out memory device according to claim 17, further comprising the acknowledgment event signal output unit for outputting to the write processor. 19. The acknowledgment event signal output unit includes a latch unit for latching an output signal of the first selection unit according to a clock inverted and transmitted through the first inversion unit. 3. A control circuit for an asynchronous first-in first-out memory device according to claim 1. 20. The latch unit receives an externally applied initialization signal via a reset terminal, has an input terminal connected to the output terminal of the first selection unit, and has a clock terminal connected to the first inversion unit. 20. The asynchronous first-in first-out memory device according to claim 19, further comprising a D-flip-flop connected to an output terminal and having an output terminal commonly connected to an input terminal of the write processor and an input terminal of the first selection unit. Control circuit. 21. An input terminal of the latch unit, wherein the first selection unit receives a request event signal transmitted from the write processor when a low storage state signal is transmitted from the second comparison unit. And transmitting a signal fed back from the latch unit to an input terminal of the latch unit when the first storage state signal in a high state is transmitted from the second comparison unit. 21. The control circuit of the asynchronous first-in first-out memory device according to 20. 22. The second acknowledgment event signal generator, comprising: a request event signal transmitted from the read processor and an output signal of a acknowledgment event signal output unit according to the second storage state signal transmitted from the third comparison means. And a second selector for selectively transmitting the second acknowledgment signal and receiving the output signal of the second selector in response to a clock inverted and transmitted through the second inverter. The control circuit of an asynchronous first-in first-out memory device according to claim 17, further comprising the confirmation event signal output unit for outputting to the read processor. 23. The acknowledgment event signal output unit includes a latch unit for latching an output signal of the second selection unit in response to a clock inverted and transmitted through the second inversion unit. A control circuit for the asynchronous first-in first-out memory device as described. 24. The latch section, which receives an externally applied initialization signal via a reset terminal, an input terminal connected to an output terminal of the second selection section, and a clock terminal connected to the second inversion section. 24. The control of the asynchronous first-in first-out memory device according to claim 23, further comprising a D-flip-flop connected to an output terminal and having an output terminal commonly connected to an input terminal of the read processor and an input terminal of the second selection unit. circuit. 25. An input terminal of the latch unit, wherein the second selection unit receives a request event signal transmitted from the read processor when a second storage state signal in a low state is transmitted from the third comparison unit. Transmitting a signal fed back from the latch unit to an input terminal of the latch unit when the second storage state signal in a high state is transmitted from the third comparison unit. 25. The control circuit of the asynchronous first-in first-out memory device according to 24.