CN2502323Y - Buffer for changing data access rate and system using the same - Google Patents
Buffer for changing data access rate and system using the same Download PDFInfo
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- CN2502323Y CN2502323Y CN 01264321 CN01264321U CN2502323Y CN 2502323 Y CN2502323 Y CN 2502323Y CN 01264321 CN01264321 CN 01264321 CN 01264321 U CN01264321 U CN 01264321U CN 2502323 Y CN2502323 Y CN 2502323Y
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Abstract
A buffer for changing data access rate and system using the same can combine with the storage device, for example, twice data speed synchronization random string storage device, to improve the data transmission speed of the transmission system. The buffer is connected with the controlling chip and a plurality of the storage modules, to provide the function of data decompounding and compounding, to satisfy the data transmission interfaces of two sides, to reach the high data transmission function. The buffer simultaneously has the function that obstructs the electricity of two sides. The buffer conversion comes from the single signal interface of the storage module to be the complementary synchronized resource signal, can reach the data transmission speed with high efficiency.
Description
Technical field
The utility model relates to the snubber assembly in a kind of memory access system, and particularly is applied in the mainboard relevant for a kind of, improves the snubber assembly of memory data access speed.
Background technology
In these years, dynamic RAM is gone through repeatedly evolution, from the earliest asynchronous dynamical random access memory, EDO dynamic RAM, the synchronous DRAM that widely uses till now.Change each time all improves the access rate of accumulator system widely.Recently, the synchronous scheme of originating is all advocated in the bus design of most of two-forties, such as AGPBUS, Double Data Rate form dynamic RAM (hereinafter to be referred as DDR DRAM) or RAMBUS.In addition, the data transmission of two-forty needs complementary data strobe (Data Strobe) signal.Therefore, combining source synchronization scenario and the direction that provides complementary signal to design just like current accumulator system.
The market of dynamic randon access system is quite huge.In general, approximately need three just can once significantly change to quinquenniad.Therefore, the speed of accumulator system usefulness raising seems quite slow with respect to the growth amplitude of volume of transmitted data between microprocessor and storage or the graphics device.The particularly application on the internet, the internet requires great amount of data transmission, and relatively poor memory band width can influence user's impression widely to be enjoyed.
Figure 1 shows that a kind of common main board memory system block diagram.Please refer to Fig. 1, control chip group 10 directly is connected with memory module slot 14.This control chip group and memory module slot use the benchmark of same system clock as message transmission rate.Be subject to the access rate of existing dynamic RAM, control chip group must reduce the transfer rate of read write command and data, finishes the data write action with the transfer rate that accumulator system can be supported.
Summary of the invention
The utility model just provides a kind of device that changes data access speed, makes the dynamic RAM system of existing standard can reach the message transmission rate of multiple.A kind of impact damper that changes data access speed among the embodiment of the present utility model connects control chip group and a plurality of memory module slot simultaneously, is responsible for decomposing with the tendency to develop of assembling control chip group and gives reading and writing data of memory module slot.
The utility model also is to provide a kind of device that changes data access speed, and its conversion sends single read-write interface by the storer end, becomes the desired complementation of higher transmission rates and comes source synchronizing signal.
A kind of device that changes data access speed of the present utility model, simultaneously also can intercept being electrically connected between control chip group and the memory module slot, further make the system design modularization with have more elasticity, for example: the consideration during topological design on the sequential is simpler and easy.
A kind of device that changes data access speed of the present utility model, also can keep or increase under the frequency range of message transmission rate, reduce the required pin number of control chip group output, cost is further reduced, or this precious resources in output input pin position is protected reserve for other use.
A kind of impact damper that changes data access speed that the utility model embodiment is provided is summarized as follows:
The impact damper that this changes data access speed comprises: phase-locked loop, control chip group end data input and output interfaces, storer end data input and output interfaces, control chip group end arrive the push-up storage of control chip group end and the control signal generating unit of impact damper to push-up storage, the storer end of storer end.The required various clock signals of this impact damper are responsible for producing in phase-locked loop wherein.This impact damper connects control chip group and a plurality of memory module slot, is responsible for reception by the control chip group end to the push-up storage of storer end and sends from control chip group and write data, decomposes and sends these memory module slots to; The storer end then is responsible for receiving the sense data that sends from these memory module slots to the push-up storage of control chip group end, sends control chip group after the combination again to.The control signal generating unit of impact damper then is responsible for producing suitable read-write control and output input control, makes that the message transmission rate of control chip group end is certain prearranged multiple of storer end data transfer rate.As known to persons of ordinary skill in the art, above-mentioned phase-locked loop can not exist yet, and the clock signal of its generation can directly be provided by system.
Above-mentioned impact damper has been arranged, and we can divide other memory module slot by combination, improve the usefulness of accumulator system, with the message transmission rate of coupling microprocessor or other input and output interfaces.
As benchmark, this mechanism is by proposed (PCT patent application case notification number PCT#/US99/05120 number) by Jazio with a new output input mechanism for the embodiment of this utility model.This impact damper that changes data access speed uses existing memory science and technology, improves the transmission usefulness of common Double Data Rate form dynamic RAM system greatly.
Description of drawings
Fig. 1 is a kind of common accumulator system connection layout;
Fig. 2 is the accumulator system connection layout according to the utility model preferred embodiment;
Fig. 3 is the impact damper synoptic diagram of the utility model preferred embodiment;
Fig. 4 is the in-built synoptic diagram of control chip group end data input and output interfaces in the utility model preferred embodiment;
Fig. 5 is the in-built synoptic diagram of storer end data input and output interfaces in the utility model preferred embodiment;
Fig. 6 writes data time sequence figure for accumulator system in the utility model preferred embodiment;
Fig. 7 is the sense data sequential chart of accumulator system in the utility model preferred embodiment;
Fig. 8 is the accumulator system connection layout according to another embodiment of the utility model;
Fig. 9 is the accumulator system connection layout according to the another embodiment of the utility model;
Figure 10 is according to the utility model accumulator system connection layout of an embodiment again.
100: the general control chipset
140: the normal memory module slot
200: control chip group
220: the impact damper that changes data access speed
240: the high memory module slot
260: the low memory module slot
300: the phase-locked loop
310: control chip group end data input and output interfaces
320: storer end data input and output interfaces
330: control chip group is to the push-up storage of storer
332: the first fifo queues
334: the second fifo queues
336: the three fifo queues
338: the four fifo queues
340: storer is to the push-up storage of control chip group
342: high-order push-up storage
344: the low level push-up storage
350: the control signal generating unit of impact damper
360: phase-delay network
400: storer is to the multiplexer of control chip group
420: the output input control circuit
500: high memory is to the multiplexer of control chip group
520: low memory is to the multiplexer of control chip group
540: delay circuit
560: the output input control circuit
800: control chip group
820: the impact damper that changes data access speed
840: memory module slot
Embodiment
Be illustrated in figure 2 as a kind of impact damper of data access speed and system of its application of changing according to the utility model one preferred embodiment.Impact damper 220 is seated between control chip group 200 and the memory module slot 240,260, provides two side systems needed message transmission rate respectively.High memory module slot 240 and low memory module slot 260 can be used for the multi-form storer of planting, and the dynamic RAM with the Double Data Rate form in the present embodiment is an example, and these storeies are to be used for storage data.When control chip group 200 was desired on the access memories data, control chip group 200 can be sent read-write control command or signal.In the present embodiment, the read-write control signal of being sent also can send control signal to memory module slot 240,260 simultaneously except giving impact damper 220.As known to persons of ordinary skill in the art, in fact other variety of way can be arranged, for example: control chip group 200 is not directly sent this read-write control signal and is given memory module slot 240,260, send control signal to give memory module slot 240,260 by impact damper 220; Or control chip group 200 is sent two groups of different read-write control signal respectively to impact damper 220 and memory module slot 240,260.
As shown in Figure 2, control chip group 200 has the data strobe signal pin position (CDQS of one group of complementation, CDQS#), to support the data transmission of two-forty between control chip group 200 and this impact damper 220, for saving the output input pin position resource of chipset, wherein complementary data gating signal pin position CDQS# can share output input pin position with for example data cover curtain pin position DQM#.As shown in Figure 3, change the impact damper 220 of data access speed, comprise that a phase-locked loop 300, phase-delay network 360, control chip group end data input and output interfaces 310, storer end data input and output interfaces 320, control chip group end arrive the push-up storage 340 of control chip group end and the control signal generating unit 350 of an impact damper to the push-up storage 330 of storer end, a storer end.
As shown in Figure 3, impact damper 220 has pin position CLKIN and CLKIN#, provides this buffering complementary system clock; One group of data strobe signal pin position CDQS, CDQS# from control chip group is arranged; Read write command signal pin WRCMD, RDCMD from control chip group are arranged; And one eight data bus pin position CDQ[7:0], be responsible for the data transmission between control chip group 200 and the impact damper 220.In addition, impact damper 220 also has the data strobe signal pin position DDQSH from the high memory module slot; Data strobe signal pin position DDQSL from the low memory module slot; And two the total stitch of eight bit data position DDQH[7:0], DDQL[7:0], be responsible for the data transmission between impact damper 220 and the two groups of memory module slots 240,260.
As shown in Figure 3, external system clock CLKIN is accepted in phase-locked loop 300, produces the internal system time clock ICLK of a same frequency and the inside frequency doubling system clock that frequency is several times as much as external system clock.To close be the multiple relation of twice for this multiple in this embodiment, so this inner frequency doubling system clock of title is ICLK2X.As known to persons of ordinary skill in the art, above-mentioned phase-locked loop 300 also may be not comprised in this impact damper 220, but directly provides the frequency doubling system clock to impact damper 220 by system.
Control chip group in the impact damper 220 is responsible for receiving by control chip group and is transmitted the data of desiring write store module slot 240,260 to the push-up storage 330 of storer, and this message transmission rate partly is four times of external system clock CLKIN.Storer in the impact damper 220 is responsible for receiving and is transmitted the data that control chip group is desired to read by 240,260 of memory module slots to control chip group push-up storage 340, and this message transmission rate partly is the twice of from outside system clock CLKIN.Push-up storage 340 inside are divided into two push-up storages 342,344, receive respectively from the data of high memory module slot 240 with low memory module slot 260.If longer between the access section of data strobe signal CDQS, then may need the long push-up storage 340 of the degree of depth.The control signal generating unit 350 of impact damper 220 is accepted external signal RDCMD and WRCMD, produces the read-write control signal of timing control signal with inner each push-up storage 330,340 of inner output input control circuit respectively.
As shown in Figure 4, comprise an output input control circuit 420 and three multiplexers 400,440,460 in the chip controls group end data input and output interfaces 310.Multiplexer 400 is controlled by inner frequency doubling clock signal ICLK2X, selects to come from the data of push-up storage 342 or 344 according to the height of clock signal ICLK2X.So this partial data transfer rate is four times of external system clock.Multiplexer 440 and 460 is accepted same clock signal ICLK2X and is controlled, and its function is the difference of injection time between balance CDQ and CDQS, the CDQS#.
As shown in Figure 3, a phase-delay network 360 is arranged in the impact damper 220, accept internal clock signal ICLK, and produce the internal latency clock signal ICLKD of one 1/4 phase delay, so that the time standard of storer end data transmission interface to be provided.
As shown in Figure 5, storer end data input and output interfaces 320 comprise an output road control circuit 560, delay circuit 540, with four multiplexers 500,510,520,530.Multiplexer 500 is accepted the control of internal clock signal ICLK, selects from the data of desiring to write high memory module slot 240 in the fifo queue 332,336.Multiplexer 520 is accepted the control of internal clock signal ICLK, selects from the data of desiring to write low memory module slot 260 in the fifo queue 334,338.Therefore, this partial data transfer rate twice that is external system clock CLKIN.Multiplexer 510 and 530 also is the control of accepting internal clock signal ICLKD, and its function is the difference of injection time between balance DDQH, DDQL and DDQSHH, the DDQSL.When reading the double data rate dynamic RAM, internal latency clock signal ICLKD can provide the sequential control of delay circuit 540; When writing the double data rate dynamic RAM, the internal latency clock signal then as the sequential control of multiplexer 510 and 530 is provided as above-mentioned.
When control chip group 200 is sent an order of reading storer, read command signal RDCMD can be transferred into impact damper 220, and other synchronous DRAM order CS#, SRAS, SCAS, SWE, can be transferred into high memory module slot 240 and low memory module slot 260 simultaneously with address MA.Data strobe signal DDQSH, DDQSL that impact damper 220 receives from memory module slot through after delay circuit delays 1/4 phase place, lock high position data DDQH and low data DDQL respectively in the push-up storage 342,344.Next, impact damper 220 can produce complementary data gating signal CDQS, the CDQS# of four times of speed, and the CDQ of data output simultaneously accepts inner frequency doubling clock signal ICLK2X and selects from the data in the push-up storage 342,344.Voltage and timing reference that the complementary data gating signal CDQS of four times of speed, CDQS# can provide receiving circuit necessity in the control chip group 200.Advise the scheme that receiving circuit will use Jazio to propose here, make the data transmission of two-forty be achieved.
When control chip group is started the order of a write store, write command signal WRCMD can be transferred into impact damper 220, and other synchronous DRAM order CS#, SRAS, SCAS, SWE, can be transferred into high memory module slot 240 and low memory module slot 260 simultaneously with address MA.At this moment, impact damper 220 can receive data strobe signal CDQS, the CDQS# from control chip group, and the data CDQ that control chip group is desired write store locks in the push-up storage 330.The message transmission rate of this moment is four times of external system clock CLKIN.Next, impact damper 220 can produce data strobe signal DDQSH, DDQSL, and with the transmission interface specification that meets the Double Data Rate synchronous DRAM data DDQH, DDQL is sent to respectively in high memory module slot 240 and the low memory module slot 260.
Fig. 6 writes data time sequence figure for accumulator system in the utility model preferred embodiment.Fig. 7 is the sense data sequential chart of accumulator system in the utility model preferred embodiment.Except that the representative of SCMD/MA for order and address signal, all the other signals can be learnt by above-listed narration among the figure.Find out that thus this changes data rate impact damper 220 message transmission rate of existing Double Data Rate synchronous DRAM system is risen to original twice.
Those of ordinary skill, principle when extensible the foregoing description, the data bit number of relevant controlling chipset on the impact damper is reduced, or keep the data bit number but the speed of increase data transmission, and also the data bit of relevant memory module slot aspect on the impact damper can be divided into some groups on the other hand, the number of the data bit of each group memory module slot is not necessarily the same with the data bit number of control chip group.Fig. 8 is the accumulator system connection layout according to another preferred embodiment of the utility model.Please referring to Fig. 8, a kind of system that changes data access speed of this embodiment comprises: j organizes memory module slot 840, control chip group 800 and impact damper 820.
J group memory module slot 840 can be used for the storer of a predetermined form of planting, the storer of this definite form can be the storer of Double Data Rate synchronous DRAM or other standard specification, to reduce the cost of storage data, each group memory module slot has m data bit signal.Control chip group 800 is connected to these memory module slots 840, control chip group 800 has n data bit signal, the i of the data rate of the storer of the predetermined for this reason form of the data access interface of control chip group 800 doubly, when control chip group 800 was desired on the access memories data, control chip group 800 was directly sent a read write command to storer.Impact damper 820 is coupled to these memory module slots 840 and control chip group 800, and impact damper 820 send the data of the data rate of receiving the data access interface that meets control chip group 800, and the data of the storer of the correct above-mentioned predetermined form of access.
Above-mentioned n, m, i, j are positive integer, and i, j＞=2, because the data volume of actual output input is must be the same, thus n, m, i, j must meet i
*N=m
*J.Among first embodiment of the present utility model, the multiple of data rate is 2 times, be i=2, the number of the data bit of relevant memory module slot aspect can be 8, be m=8, and memory module slot is divided into 2 groups, i.e. j=2, then relevant controlling chipset aspect data bit number just 8, i.e. n=8.In addition for instance, the multiple of data rate can be 8 times, i.e. i=8, the number of the data bit of relevant memory module slot aspect is 16, i.e. m=16, and memory module slot is divided into 4 groups, be j=4, then relevant controlling chipset aspect the data bit number just as long as 8, i.e. n=8.
Can be known by inference by a last embodiment, the impact damper 820 that this kind changes data access speed comprises: the storer end data input and output interfaces, the control chip group end data input and output interfaces that is coupled to control chip group 800, first push-up storage that is coupled to control chip group end data input and output interfaces and storer end data input and output interfaces and the control signal generating unit of second push-up storage and impact damper that are coupled to those group memory module slots.
The control signal generating unit of impact damper is coupled to storer end data input and output interfaces, control chip group end data input and output interfaces, first push-up storage, second push-up storage and control chip group, the control signal generating unit of this impact damper is used to understand the read write command that is sent by control chip group 800, and then produce required read-write control signal, wherein the data rate that transmitted of control chip group end data input and output interfaces be the data rate that transmitted of storer end data input and output interfaces i doubly, above-mentioned n, m, i, j is a positive integer, and i, j＞=2, and meet i
*N=m
*J.
First push-up storage and this second push-up storage are as the buffering between different pieces of information speed, above-mentioned read-write control signal is controlled first push-up storage and second push-up storage, first push-up storage is received by what control chip group end data input and output interfaces sent write the transmission data, and then will write the transmission data send storer end data input and output interfaces to, and second push-up storage is received by what storer end data input and output interfaces was sent read the transmission data, and then this is read the transmission data send control chip group end data input and output interfaces to.
Each group memory module slot can receive the memory clock signal of same frequency among this embodiment, and impact damper 820 more can comprise the phase-locked loop, be used to produce impact damper clock signal and multiple impact damper clock signal, the frequency of this memory clock signal of impact damper clock signal is identical, and the frequency of multiple impact damper clock signal be this memory clock signal frequency i doubly, the control signal generating unit reception buffer clock signal of impact damper and multiple impact damper clock signal are to produce correct time sequence control signal.
Fig. 9 and Figure 10 are the accumulator system connection layout according to two other embodiment of the utility model.Among the embodiment of Fig. 8, the read-write control signal that control chip group 800 is sent also can send control signal to these memory module slots 840 simultaneously except giving impact damper 820.Among the embodiment of Fig. 9, control chip group 800 is sent two groups of different read-write control signal respectively and is given impact damper 820 and memory module slot 840.Among the embodiment of Figure 10, control chip group 800 is not directly sent read-write control signal and is given memory module slot 840, and send control signal to give memory module slot 840 by impact damper 820.
Claims (27)
1, a kind of impact damper that changes data access speed, it is coupled to a high memory module slot, a low memory module slot and a control chip group, this high memory module slot and this low memory module slot are accepted a memory clock signal, it is characterized in that this impact damper comprises:
One storer end data input and output interfaces, it is coupled to this high memory module slot and this low memory module slot;
One control chip group end data input and output interfaces, it is coupled to this control chip group;
One first push-up storage, it is coupled to this control chip group end data input and output interfaces and this storer end data input and output interfaces;
One second push-up storage is coupled to this control chip group end data input and output interfaces and this storer end data input and output interfaces; And
The control signal generating unit of one impact damper, it is coupled to this storer end data input and output interfaces, this control chip group end data input and output interfaces, this first push-up storage, this second push-up storage and this control chip group, it accepts an impact damper clock signal and a multiple impact damper clock signal, this impact damper clock signal is identical with the frequency of this memory clock signal, the frequency of this multiple impact damper clock signal is a prearranged multiple of the frequency of this memory clock signal, the control signal generating unit of this impact damper is used to understand a read write command that is sent by this control chip group, and then produces a read-write control signal;
This prearranged multiple of the data rate that transmitted for this storer end data input and output interfaces of the data rate that transmitted of this control chip group end data input and output interfaces wherein, this first push-up storage and this second push-up storage are as the buffering between different pieces of information speed, this read-write control signal is controlled this first push-up storage and this second push-up storage, this first push-up storage is received by what this control chip group end data input and output interfaces sent one write the transmission data, and then with this write the transmission data send this storer end data input and output interfaces to, and this second push-up storage is received by what this storer end data input and output interfaces was sent one read the transmission data, and then this is read the transmission data send this control chip group end data input and output interfaces to.
2, the impact damper of change data access speed as claimed in claim 1 is characterized in that, this second push-up storage comprises:
One the 3rd push-up storage, be coupled to this storer end data input and output interfaces and this control chip group end data input and output interfaces, be used to receive a high position and read the transmission data, this high position is read the transmission data and is read for this and transmit in the data, the data that sent by this high memory module slot; And
One the 4th push-up storage, be coupled to this storer end data input and output interfaces and this control chip group end data input and output interfaces, be used to receive a low level and read the transmission data, this low level is read the transmission data and is read for this and transmit in the data, the data that sent by this low memory module slot.
3, the impact damper of change data access speed as claimed in claim 2, it is characterized in that, this control chip group end data input and output interfaces more comprises a multiplexer, this multiplexer is coupled to the 3rd push-up storage and the 4th push-up storage, this multiplexer receives this multiple impact damper clock signal, and selection is read transmission data and this high position with this low level and read and transmit the data either-or and be sent to this control chip group.
4, the impact damper of change data access speed as claimed in claim 3, it is characterized in that, the control signal generating unit of this impact damper more produces an output input control signal, this output input control signal can send this storer end data input and output interfaces and this control chip group end data input and output interfaces to, with the time reference as data output input control.
5, the impact damper of change data access speed as claimed in claim 1, it is characterized in that, this first push-up storage comprises one first fifo queue, one second fifo queue, one the 3rd fifo queue, and one the 4th fifo queue, this storer end data input and output interfaces comprises:
One high position data multiplexer, this high position data multiplexer is coupled to this first push-up storage, this high position data multiplexer receives this impact damper clock signal, is used to select the data of this first fifo queue and the data alternatively of the 3rd fifo queue are sent to this high memory module slot; And
One low data multiplexer, this low data multiplexer is coupled to this first push-up storage, this low data multiplexer receives this impact damper clock signal, and selection is sent to this low memory module slot with the data of this second fifo queue and the data alternatively of the 4th fifo queue.
6, the impact damper of change data access speed as claimed in claim 1 is characterized in that, this impact damper more comprises:
One phase-locked loop produces this impact damper clock signal and this multiple impact damper clock signal; And
One phase-delay network, it is coupled to this phase-locked loop and this storer end data input and output interfaces, is used to produce a delay buffer clock signal, and this delay buffer clock signal and this impact damper clock signal are same frequency and differ a predetermined phase.
7, the impact damper of change data access speed as claimed in claim 6 is characterized in that, this predetermined phase is 1/4 phase place.
8, the impact damper of change data access speed as claimed in claim 1 is characterized in that, this storer end data input and output interfaces more comprises a delay circuit, produces the data acquisition signal of 1/1st phase delay.
9, a kind of system that changes data access speed is characterized in that, this system comprises:
One high memory module slot, the storer of the predetermined form of can planting is with storage data;
One low memory module slot, the storer of this predetermined form of can planting is with storage data;
One control chip group, its data access interface are the prearranged multiple of data rate of the storer of this predetermined form, when this control chip group desire access should the storer of predetermined form on during data, this control chip group is sent a read write command; And
One impact damper, be coupled to this high memory module slot, low memory module slot and this control chip group, this impact damper send the data of this prearranged multiple data rate of receiving the data access interface that meets this control chip group, and correct access should be scheduled to the data of the storer of form.
10, the system of change data access speed as claimed in claim 9 is characterized in that, this high memory module slot and this low memory module slot are accepted a memory clock signal, and this impact damper comprises:
One storer end data input and output interfaces, it is coupled to this high memory module slot and this low memory module slot;
One control chip group end data input and output interfaces, it is coupled to this control chip group;
One first push-up storage, it is coupled to this control chip group end data input and output interfaces and this storer end data input and output interfaces;
One second push-up storage is coupled to this control chip group end data input and output interfaces and this storer end data input and output interfaces; And
The control signal generating unit of one impact damper, it is coupled to this storer end data input and output interfaces, this control chip group end data input and output interfaces, this first push-up storage, this second push-up storage and this control chip group, it accepts an impact damper clock signal and a multiple impact damper clock signal, this impact damper clock signal is identical with the frequency of this memory clock signal, the frequency of this multiple impact damper clock signal is this prearranged multiple of the frequency of this memory clock signal, the control signal generating unit of this impact damper is used to understand this read write command that is sent by this control chip group, and then produces a read-write control signal;
This prearranged multiple of the data rate that transmitted for this storer end data input and output interfaces of the data rate that transmitted of this control chip group end data input and output interfaces wherein, this first push-up storage and this second push-up storage are as the buffering between different pieces of information speed, this read-write control signal is controlled this first push-up storage and this second push-up storage, this first push-up storage is received by what this control chip group end data input and output interfaces sent one write the transmission data, and then with this write the transmission data send this storer end data input and output interfaces to, and this second push-up storage is received by what this storer end data input and output interfaces was sent one read the transmission data, and then this is read the transmission data send this control chip group end data input and output interfaces to.
11, the system of change data access speed as claimed in claim 10, wherein this first push-up storage comprises:
One the 3rd push-up storage, be coupled to this storer end data input and output interfaces and this control chip group end data input and output interfaces, be used to receive a high position and read the transmission data, this high position is read the transmission data and is read for this and transmit in the data, the data that sent by this high memory module slot; And
One the 4th push-up storage, be coupled to this storer end data input and output interfaces and this control chip group end data input and output interfaces, be used to receive a low level and read the transmission data, this low level is read the transmission data and is read for this and transmit in the data, the data that sent by this low memory module slot.
12, the system of change data access speed as claimed in claim 11, it is characterized in that, this control chip group end data input and output interfaces more comprises a multiplexer, this multiplexer is coupled to the 3rd push-up storage and the 4th push-up storage, this multiplexer receives this multiple impact damper clock signal, is used for selecting that this low level is read transmission data and this high position and reads and transmit the data either-or and be sent to this control chip group.
13, the system of change data access speed as claimed in claim 12, it is characterized in that, the control signal generating unit of this impact damper more produces an output input control signal, this output input control signal can send this storer end data input and output interfaces and this control chip group end data input and output interfaces to, with the time reference as data output input control.
14, the system of change data access speed as claimed in claim 10, it is characterized in that, this first push-up storage comprises one first fifo queue, one second fifo queue, one the 3rd fifo queue, and one the 4th fifo queue, this storer end data input and output interfaces comprises:
One high position data multiplexer, this high position data multiplexer is coupled to this first push-up storage, this high position data multiplexer receives this impact damper clock signal, is used to select the data of this first fifo queue and the data alternatively of the 3rd fifo queue are sent to this high memory module slot; And
One low data multiplexer, this low data multiplexer is coupled to this first push-up storage, this low data multiplexer receives this impact damper clock signal, is used to select the data of this second fifo queue and the data alternatively of the 4th fifo queue are sent to this low memory module slot.
15, the system of change data access speed as claimed in claim 10 is characterized in that, this impact damper more comprises:
One phase-locked loop produces this impact damper clock signal and this multiple impact damper clock signal; And
One phase-delay network, it is coupled to this phase-locked loop and this storer end data input and output interfaces, is used to produce a delay buffer clock signal, and this delay buffer clock signal and this impact damper clock signal are same frequency and differ a predetermined phase.
16, the system of change data access speed as claimed in claim 15 is characterized in that, this predetermined phase is 1/4 phase place.
17, the system of change data access speed as claimed in claim 10 is characterized in that, this storer end data input and output interfaces more comprises a delay circuit, and this circuit produces the data acquisition signal of one 1/4 phase delays.
18, the system of change data access speed as claimed in claim 9 is characterized in that, this control chip group comprises:
One complementary data acquisition signal pin is supported high-frequency data transmission between this control chip group and this impact damper.
19, the system of change data access speed as claimed in claim 18 is characterized in that, output input pin position is shared in this a complementary data acquisition signal pin and a data cover curtain pin position.
20, the system of change data access speed as claimed in claim 9 is characterized in that, the storer of this predetermined form is a double data speed synchronous dynamic RAM.
21, a kind of impact damper that changes data access speed, it is coupled to a j group memory module slot and a control chip group, and each group memory module slot has m data bit signal, and this control chip group has n data bit signal, it is characterized in that this impact damper comprises:
One storer end data input and output interfaces is coupled to those group memory module slots;
One control chip group end data input and output interfaces is coupled to this control chip group;
One first push-up storage is coupled to this control chip group end data input and output interfaces and this storer end data input and output interfaces;
One second push-up storage is coupled to this control chip group end data input and output interfaces and this storer end data input and output interfaces; And
The control signal generating unit of one impact damper, it is coupled to this storer end data input and output interfaces, this control chip group end data input and output interfaces, this first push-up storage, this second push-up storage and this control chip group, the control signal generating unit of this impact damper is used to understand a read write command that is sent by this control chip group, and then produces a read-write control signal;
Wherein the i of the data rate that transmitted for this storer end data input and output interfaces of the data rate that transmitted of this control chip group end data input and output interfaces doubly, above-mentioned n, m, i, j are positive integer, and i, j＞=2, and meet i
*N=m
*J, this first push-up storage and this second push-up storage are as the buffering between different pieces of information speed, this read-write control signal is controlled this first push-up storage and this second push-up storage, this first push-up storage is received by what this control chip group end data input and output interfaces sent one write the transmission data, and then with this write the transmission data send this storer end data input and output interfaces to, and this second push-up storage is received by what this storer end data input and output interfaces was sent one read the transmission data, and then this is read the transmission data send this control chip group end data input and output interfaces to.
22, the impact damper of change data access speed as claimed in claim 21, it is characterized in that, each group memory module slot receives a memory clock signal, and the control signal generating unit of this impact damper is accepted an impact damper clock signal and a multiple impact damper clock signal, this impact damper clock signal is identical with the frequency of this memory clock signal, the frequency of this multiple impact damper clock signal be this memory clock signal frequency i doubly.
23, the impact damper of change data access speed as claimed in claim 22 is characterized in that, more comprises a phase-locked loop, and this loop produces this impact damper clock signal and this multiple impact damper clock signal.
24, a kind of system that changes data access speed is characterized in that, comprising:
J organizes memory module slot, can be used for the storer of a predetermined form of planting, and is used for storage data, and each group memory module slot has m data bit signal;
One control chip group, it has n data bit signal, the data access interface of this control chip group be this predetermined form storer data rate i doubly, when this control chip group desire access should the storer of predetermined form on during data, this control chip group is sent a read write command; And
One impact damper is coupled to this j group memory module slot and this control chip group, and this impact damper send the data of the data rate of receiving the data access interface that meets this control chip group, and correct access should be scheduled to the data of the storer of form;
Above-mentioned n, m, i, j are positive integer, and i, j＞=2,
And meet i
*N=m
*J.
25, the system of change data access speed as claimed in claim 24 is characterized in that, this control chip group is sent this read write command simultaneously and given this impact damper and this j group memory module slot.
26, the system of change data access speed as claimed in claim 24 is characterized in that, this control chip group is sent read write command respectively and given this impact damper and this j group memory module slot.
27, the system of change data access speed as claimed in claim 24 is characterized in that, this control chip group is sent this read write command and given this impact damper, and this impact damper is sent another read-write control signal to this j group memory module slot.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01264321 CN2502323Y (en) | 2001-09-27 | 2001-09-27 | Buffer for changing data access rate and system using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01264321 CN2502323Y (en) | 2001-09-27 | 2001-09-27 | Buffer for changing data access rate and system using the same |
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| Publication Number | Publication Date |
|---|---|
| CN2502323Y true CN2502323Y (en) | 2002-07-24 |
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ID=33671650
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01264321 Expired - Lifetime CN2502323Y (en) | 2001-09-27 | 2001-09-27 | Buffer for changing data access rate and system using the same |
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| Country | Link |
|---|---|
| CN (1) | CN2502323Y (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100407184C (en) * | 2005-03-18 | 2008-07-30 | 威盛电子股份有限公司 | Data rate controller, and method of control thereof |
| CN100444577C (en) * | 2004-09-06 | 2008-12-17 | 中兴通讯股份有限公司 | Data transmission converter of communication system |
| CN105680895A (en) * | 2014-12-05 | 2016-06-15 | 吉林克斯公司 | Delay control for transmitter/receiver buffer |
| CN106559630A (en) * | 2015-09-30 | 2017-04-05 | 中强光电股份有限公司 | Projection arrangement and data access control module |
-
2001
- 2001-09-27 CN CN 01264321 patent/CN2502323Y/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100444577C (en) * | 2004-09-06 | 2008-12-17 | 中兴通讯股份有限公司 | Data transmission converter of communication system |
| CN100407184C (en) * | 2005-03-18 | 2008-07-30 | 威盛电子股份有限公司 | Data rate controller, and method of control thereof |
| CN105680895A (en) * | 2014-12-05 | 2016-06-15 | 吉林克斯公司 | Delay control for transmitter/receiver buffer |
| CN105680895B (en) * | 2014-12-05 | 2019-12-10 | 吉林克斯公司 | Delay control in a buffer of a transmitter/receiver |
| CN106559630A (en) * | 2015-09-30 | 2017-04-05 | 中强光电股份有限公司 | Projection arrangement and data access control module |
| CN106559630B (en) * | 2015-09-30 | 2019-10-01 | 中强光电股份有限公司 | Projection arrangement and data access control module |
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