CN114171534A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN114171534A
CN114171534A CN202110748473.XA CN202110748473A CN114171534A CN 114171534 A CN114171534 A CN 114171534A CN 202110748473 A CN202110748473 A CN 202110748473A CN 114171534 A CN114171534 A CN 114171534A
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layer
epitaxial layer
semiconductor device
substrate
drain
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塩田伦也
大岛康礼
岩崎太一
山际翔太
斋藤广翔
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Kioxia Corp
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Kioxia Corp
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Abstract

本发明的实施方式提供一种能抑制接触电阻的半导体装置及其制造方法。本实施方式的半导体装置具备衬底与晶体管。晶体管具有源极层及漏极层、栅极绝缘膜、栅极电极、接触插塞、及第1外延层。源极层及漏极层设置在衬底的表面区域且包含杂质。栅极绝缘膜设置在源极层与漏极层之间的衬底上。栅极电极设置在栅极绝缘膜上。接触插塞以相对于源极层或漏极层突出到比衬底的表面更下方的方式设置。第1外延层设置在接触插塞与源极层或漏极层之间，包含杂质及碳这两者。

Description

半导体装置及其制造方法
相关申请
本申请享受以日本专利申请2020-152066号(申请日：2020年9月10日)为基础申请的优先权。本申请通过参考所述基础申请而包括基础申请的所有内容。
技术领域
本发明的实施方式涉及一种半导体装置及其制造方法。
背景技术
已开发一种具有三维地配置存储单元而构成的立体型存储单元阵列的NAND型闪存。在这种存储装置中，有存储单元阵列设置在控制它的CMOS(Complementary MetalOxide Semiconductor：互补型金属氧化半导体)电路的上方的情况。所述情况下，在形成存储单元阵列时的热处理步骤中，对CMOS电路或接触插塞施加热负荷，对CMOS的电特性或接触电阻造成不良影响。例如，在P型MOSFET(MOS Field Effect Transistor：MOS场效应晶体管)的扩散层，将硼用作杂质。为了抑制接触电阻，考虑在接触插塞与扩散层的连接部分大量注入硼。但是，所述情况下，硼容易扩散到沟道部，容易产生短沟道效应。
发明内容
本发明所要解决的问题在于提供一种能抑制接触电阻的半导体装置及其制造方法。
本实施方式的半导体装置具备衬底、与晶体管。晶体管具有源极层及漏极层、栅极绝缘膜、栅极电极、接触插塞、及第1外延层。源极层及漏极层设置在衬底的表面区域且包含杂质。栅极绝缘膜设置在源极层与漏极层之间的衬底上。栅极电极设置在栅极绝缘膜上。接触插塞以相对于源极层或漏极层突出到比衬底的表面更下方的方式设置。第1外延层设置在接触插塞与源极层或漏极层之间，包含杂质及碳这两者。
附图说明
图1是表示第1实施方式的半导体装置的存储单元阵列的构成的一例的图。
图2是导电膜贯通多个字线及层间绝缘层的部分的放大剖视图。
图3是表示控制电路的P型MOSFET的构成例的概略剖视图。
图4是表示图3的外延层的周边的一例的放大图。
图5是表示比较例的P型MOSFET的构成例的概略剖视图。
图6是表示比较例的P型MOSFET的构成例的概略剖视图。
图7是表示比较例的P型MOSFET的构成例的概略剖视图。
图8是表示比较例的P型MOSFET的构成例的概略剖视图。
图9是表示第1实施方式的半导体装置的制造方法的一例的剖视图。
图10是接着图9表示半导体装置的制造方法的一例的剖视图。
图11是接着图10表示半导体装置的制造方法的一例的剖视图。
图12是接着图11表示半导体装置的制造方法的一例的剖视图。
图13是接着图12表示半导体装置的制造方法的一例的剖视图。
图14是接着图13表示半导体装置的制造方法的一例的剖视图。
图15是表示第1实施方式的接触孔及孔的形状的一例的示意图。
图16是表示第2实施方式的P型MOSFET的构成例的剖视图。
图17是表示控制电路的N型MOSFET及P型MOSFET的构成例的剖视图。
具体实施方式
以下，参考附图说明本发明的实施方式。本实施方式不限定本发明。在以下的实施方式中，半导体衬底的上下方向表示以设置半导体元件的面为上面时的相对方向，有与依据重力加速度的上下方向不同的情况。附图是示意性或概念性的图，各部分的比例等未必与现实情况相同。在说明书与附图中，对与已出的附图中已描述的内容相同的要件标注相同符号，适当省略详细说明。
(第1实施方式)
图1是表示第1实施方式的半导体装置的存储单元阵列的构成的一例的图。另外，在图1中，为了容易观察图，对形成在存储孔113内的绝缘膜以外的绝缘部分省略图示。此外，在以下的实施方式中，例示硅作为半导体，但也可使用硅以外的半导体。
此外，在本说明书中，为了便于说明，导入XYZ正交坐标系。在所述坐标系中，将相对于半导体衬底10的主面平行的方向且相互正交的2个方向设为X方向及Y方向，将相对于所述X方向及Y方向这两个方向正交的方向设为Z方向。多个字线WL积层在Z方向。
在半导体衬底10的表面区域，设置着控制存储单元阵列MCA的控制电路101。控制电路101例如由CMOS电路构成。CMOS电路也可设置在P型阱或N型阱，所述P型阱或N型阱设置在半导体衬底10的表面区域。在控制电路101的上方，设置着包含多个存储单元的存储单元阵列MCA。
在位于控制电路101上方的多晶硅层102上，形成着多个NAND串NS。具体来说，在多晶硅层102上，形成着作为选择栅极线SGS发挥功能的多个布线层110、作为字线WL发挥功能的多个布线层111(字线WL0～WL7)、及作为选择栅极线SGD发挥功能的多个布线层112。
布线层110由例如4层形成，由多个NAND串NS电连接到共同的选择栅极线SGS，作为2个选择晶体管ST2的栅极电极发挥功能。
布线层111由例如8层形成，在每层电连接到共同的字线WL。
布线层112由例如4层形成，连接到与每个NAND串NS对应的选择栅极线SGD，分别作为1个选择晶体管ST1的栅极电极发挥功能。
存储孔113以贯通布线层110、111、112，到达多晶硅层102的方式形成。在存储孔113的侧面，依序形成着阻挡绝缘层114、电荷累积膜115、及栅极绝缘膜116。在存储孔113内，嵌入着导电膜117。导电膜117作为NAND串NS的电流路径发挥功能。在导电膜117的上端，形成着作为位线BL发挥功能的布线层118。
如以上所述，在多晶硅层102上，依序积层选择晶体管ST2、多个存储单元晶体管MT0～MT7、及选择晶体管ST1，1个存储孔113对应1个NAND串NS。存储单元晶体管MT0～MT7对应导电膜117与字线WL0～WL7的交叉部分设置。
在图1中记载的纸面的深度方向排列着多个以上构成。由此，构成具有三维地排列的存储单元晶体管的存储单元阵列MCA。
图2是导电膜117贯通多个字线WL及层间绝缘层25的部分的放大剖视图。在图2中，将图1中省略的导电层WL间的绝缘层表示为绝缘层25。
在各导电层WL与导电膜117之间，从导电层WL侧起依序设置着阻挡绝缘层114、电荷累积膜115及栅极绝缘膜116。阻挡绝缘层114与导电层WL相接，栅极绝缘膜116与导电膜117相接，在阻挡绝缘层114与栅极绝缘膜116之间设置着电荷累积膜115。
导电膜117作为沟道发挥功能，导电层WL作为控制栅极发挥功能，电荷累积膜115作为累积从导电膜117注入的电荷的数据存储层而发挥功能。也就是说，在导电膜117与各导电层WL的交叉部分，形成着由控制栅极包围沟道周围的构造的存储单元。
本实施方式的半导体装置是能电自由地进行数据的抹除、写入，即使切断电源也能保存存储内容的非易失性半导体存储装置。例如，存储单元是电荷陷阱构造的存储单元。电荷累积膜115具有多个捕获电荷(电子)的陷阱，为例如氮化硅膜。栅极绝缘膜116为例如氧化硅膜，在从导电膜117对电荷累积膜115注入电荷时、或累积在电荷累积膜115的电荷向导电膜117扩散时，成为电位势垒。阻挡绝缘层114为例如氧化硅膜，防止累积在电荷累积膜115的电荷向导电层WL扩散。半导体装置例如可为NAND型闪存。
图3是表示控制电路101的P型MOSFET的构成例的概略剖视图。P型MOSFET(以下也简称为晶体管)具备半导体衬底10、漏极层20、源极层21、栅极绝缘膜30、栅极电极40、GC(Gate Conductor：栅极导体)42、外延层50、接触插塞70、保护膜80、层间绝缘膜90、及衬膜92。晶体管作为构成控制存储单元阵列MCA的控制电路的CMOS的一部分设置。此外，如图1所说明，在控制电路101内的晶体管的上方，设置着存储单元阵列MCA。
半导体衬底10例如为P型硅衬底，在它的表面区域，设置着P型阱或N型阱。P型MOSFET设置在N型阱，N型MOSFET设置在P型阱。在本实施方式中，因为晶体管为P型MOSFET，所以设置在半导体衬底10中的N型阱的表面区域。
漏极层20及源极层21设置在半导体衬底10的N型阱，为包含杂质的扩散层。杂质例如为硼(B)。晶体管为N型MOSFET的情况下，漏极层20及源极层21设置在半导体衬底10的P型阱，杂质例如为磷(P)或砷(As)。
栅极绝缘膜30设置在位于漏极层20与源极层21之间的半导体衬底10上。对于栅极绝缘膜30，例如使用氧化硅膜、或相对介电常数高于氧化硅膜的高介电材料。
栅极电极40设置在栅极绝缘膜30上。对于栅极电极40，例如使用掺杂多晶硅、金属等导电性材料。
GC42设置在栅极电极40上。对于栅极GC42，例如使用钨等导电性材料。
外延层50是设置在接触插塞70与源极层21或漏极层20之间，且掺杂了硼及碳(C)这两个作为杂质的掺杂外延硅层。例如，外延层50的硼浓度为1×1021cm-3以上，碳浓度为2×1020cm-3以上。此外，外延层50是导入硼及碳同时使它们外延生长的单晶硅层。通过包含碳，能抑制硼扩散，而将外延层50内的硼浓度维持得较高。由此，能将外延层50本身的电阻维持得较低，此外，能通过使硼扩散到沟道区域10c而抑制短沟道效应的产生。如果产生短沟道效应，那么晶体管特性会劣化。
接触插塞70设置在外延层50上。此外，接触插塞70以相对于源极层21或漏极层20突出到比半导体衬底10的表面F更下方的方式设置。另外，关于外延层50的形状及接触插塞70的形状的细节，参考图4在下文说明。
接触插塞70具备势垒金属层72、与插塞73。另外，接触插塞70还可以具备设置在势垒金属层72与外延层50之间的硅化物层。硅化物层由势垒金属层72的金属与外延层50的硅反应而形成。
势垒金属层72较薄地设置在外延层50上的接触孔CH的内壁。对于势垒金属层72，例如使用Ti或TiN。所述情况下，硅化物层成为TiSi(硅化钛)。如果硼及碳从外延层50扩散，那么硅化物层成为包含B、C的TiSi。
插塞73填充在接触孔CH内。对于插塞73，例如使用W(钨)。
保护膜80设置在GC42的上表面，保护GC42。对于保护膜80，例如使用氮化硅膜等绝缘性材料。
层间绝缘膜90设置在栅极电极40的侧面及保护膜80的上方。在层间绝缘膜90，可设置接触孔CH，在它的内部设置着接触插塞70。对于层间绝缘膜90，例如使用氧化硅膜等绝缘膜。
接触插塞70电连接到控制电路101的其它元件或存储单元阵列MCA。接触插塞70包含在衬底10与存储单元阵列MCA之间。
衬膜92以被覆半导体衬底10、栅极电极40及保护膜80的方式设置。晶体管为P型MOSFET的情况下，衬膜92能对沟道区域10c施加压缩应力，提高载流子迁移率(空穴的迁移率)。此外，晶体管为N型MOSFET的情况下，衬膜92能对沟道区域10c施加拉伸应力，提高载流子迁移率(电子的迁移率)。对于衬膜92，例如使用氧化硅膜等绝缘性材料。
另外，晶体管为P型MOSFET，但也可为N型MOSFET。其中，因为作为P型杂质的硼比作为N型杂质的磷或砷更容易扩散，所以由热负荷引起的短沟道效应及接触电阻上升等不良影响在P型MOSFET中相对较大。因此，在本实施方式中，将晶体管作为P型MOSFET进行说明。
图4是表示图3的外延层50及它的周边的一例的放大图。
如上所述，接触插塞70以突出到比半导体衬底10的表面F更下方的方式设置。因为接触插塞70为金属，所以电阻相对较低。因此，接触插塞70越长，越能抑制接触电阻。
此外，外延层50以覆盖突出到比半导体衬底10的表面(面F)更下方的接触插塞70的方式配置。因为外延层50包含高浓度的硼，所以电阻比源极层21或漏极层20更低。由此，能利用电阻相对较低的外延层50，使接触插塞70与源极层21或漏极层20电连接。此外，因为外延层50在比面F更下方的位置覆盖接触插塞70的底部，所以能提高与半导体衬底10的接触表面积。其结果，能抑制接触电阻。此外，在接触部分，也能容易使电流更均匀地流动。
此外，外延层50的宽度大于接触插塞70的宽度。宽度为垂直于接触插塞70的方向(图4的横向)的距离。也就是说，从半导体衬底10的上方观察的外延层50的外边缘位于比接触插塞70的外边缘更外侧。这是因为如之后说明，从接触孔CH的底部，在垂直于接触孔CH的方向(平行于面F的方向)蚀刻半导体衬底10(参考图12)。此外，因为上述形状，外延层50以从接触插塞70向沟道区域10c侧延伸的方式设置。因为外延层50的电阻相对较低，所以能抑制从接触插塞70到沟道区域10c的电流通路(电流路径)的寄生电阻。其结果，能进一步抑制接触电阻，同时能提高接通电流。
此处，在图3中，dCS表示接触插塞70的直径。dwidth表示作为接触层的外延层50的宽度。ddepth表示作为接触层的外延层50的深度。drecess表示从接触孔CH的底部向垂直于接触孔CH的方向延伸的外延层50的距离。dCS-GC表示从接触插塞70到GC42的距离。
如上所述，优选为外延层50的宽度大于接触插塞70的宽度。也就是说，优选为dCS＜dwidth。此外，外延层50的宽度根据接触插塞70与栅极的位置关系而调整。包含相对较高浓度的硼的外延层50作为低电阻的电流通路发挥功能。但是，如果外延层50过于接近沟道区域10c，那么容易产生由外延层50内的硼扩散到沟道区域10c引起的短沟道效应。因此，优选drecess例如优选为满足dCS-GC/2＞drecess。
图5～图8是表示比较例的P型MOSFET的构成例的概略剖视图。在下文中，对图3所示的构造中的接触电阻、与图5～图8的构造中的接触电阻的比较进行说明。另外，接触电阻值本身根据接触的剖面积变化。因此，在本实施方式中，接触电阻值由标准的值表示。
图3所示的本实施方式的接触构造的情况下，从接触插塞70到源极层21或漏极层20的接触电阻为约232ohm。此外，接通电流为约115μA/μm。
图5所示的接触构造在源极层21或漏极层20与外延层50之间设置未掺杂外延层52。未掺杂外延层52为未掺杂外延硅层，为未导入杂质而外延生长的单晶硅层。因此，未掺杂外延层52与外延层50相比，杂质浓度较低，电阻较高。未掺杂外延层52是为了提高外延层50的晶体状态、及抑制硼扩散而设置。
未掺杂外延层52设置到比半导体衬底10的表面F高的位置。此外，在未掺杂外延层52上设置着外延层50，在外延层50上设置着接触插塞70。因此，图5所示的接触构造与图3所示的接触构造相比，接触插塞70底部的位置为高于面F的位置。此外，外延层50的宽度及未掺杂外延层52的宽度与接触插塞70的宽度大致相同。此外，因为未掺杂外延层52具有相对较高的电阻(寄生电阻)，所以造成接触电阻增大。图5所示的接触构造的其它构成与图3的构成相同。图5所示的接触构造的情况下，从接触插塞70到漏极层20或源极层21的接触电阻为约880ohm。此外，接通电流为约95μA/μm。
图6所示的接触构造相对于图5的接触构造，未设置未掺杂外延层52。因为未设置电阻相对较高的未掺杂外延层52，所以与图5所示的构造相比，认为能提高接触电阻。图6所示的接触构造的其它构成与图5的构成相同。此外，在图6中，外延层50的宽度与接触插塞70的宽度大致相同。因此，图6所示的外延层50与图3所示的接触构造相比，接触表面积较小，接触电阻较大。图6所示的接触构造的情况下，从接触插塞70到漏极层20或源极层21的接触电阻为约706ohm。此外，接通电流为约90μA/μm。
图7所示的接触构造相对于图5的接触构造，以接触插塞70的底部位于更低位置的方式设置。因为电阻相对较低的接触插塞70及外延层50延伸，接近源极层21或漏极层20，所以与图5所示的构造相比，认为能抑制接触电阻。图7所示的接触构造的其它构成与图5的构成相同。此外，在图7中，外延层50的宽度与接触插塞70的宽度大致相同。因此，图7所示的外延层50与图3所示的接触构造相比，接触表面积较小，接触电阻较大。图7所示的接触构造的情况下，从接触插塞70到源极层21或漏极层20的接触电阻为约800ohm。
图8所示的接触构造相对于图5的接触构造，硼及碳的导入方法不同。在图8中，不利用外延生长进行外延层50的形成，而形成未掺杂外延层52。之后，利用离子注入法将硼及碳向未掺杂外延层52导入。因此，图8所示的硼及碳的分布54与图3及图5～图7不同。这是因为，在离子注入法中，与外延生长相比，更难在空间上控制杂质浓度。例如，如果在期望的位置高浓度地掺杂使用硼，那么也会掺杂到更深的位置，有可能产生泄漏或短沟道效应。此外，在离子注入法中，有可能使未掺杂外延层52的晶体状态恶化。此外，在离子注入法中，也难以进行如图3所示的在接触插塞70的侧面附近导入硼及碳。图8所示的接触构造的其它构成与图5的构成相同。图8所示的接触构造的情况下，从接触插塞70到源极层21或漏极层20的接触电阻为约800ohm。
如此，图3所示的本实施方式的接触构造以接触插塞70突出到比面F更下方的方式设置，以由外延层50覆盖接触插塞70的底部的方式设置。此外，外延层50以从接触插塞70向沟道区域10c延伸的方式设置。由此，图3的接触构造与图5～图8的接触构造相比，能将接触电阻抑制得较低。此外，图3的接触构造能提高接通电流，有助于提高晶体管的开关特性、及使控制电路100的动作高速化。
接下来，说明本实施方式的半导体装置的制造方法。
图9～图14是表示第1实施方式的半导体装置的制造方法的一例的剖视图。在图9～图14中，表示作为晶体管的P型MOSFET的制造方法。
首先，如图9所示，在半导体衬底10上，将硼等杂质导入到半导体衬底10的表面区域，将漏极层20及源极层21形成在半导体衬底10的表面区域。
接下来，如图10所示，在半导体衬底10上形成栅极绝缘膜30。栅极绝缘膜30可为利用热氧化法形成的氧化硅膜，也可为利用堆积法形成的高介电材料。接下来，在栅极绝缘膜30上堆积栅极电极40的材料。接下来，在栅极电极40上形成GC42及保护膜80。使用光刻及RIE(Reactive Ion Etching：反应性离子蚀刻)法等将堆积的多层积层膜进行形状加工，由此获得图10所示的构造。
接下来，在栅极电极40及半导体衬底10上堆积层间绝缘膜90及衬膜92。层间绝缘膜90例如可为使用TEOS(Tetraethoxysilane：四乙氧基硅烷)等的氧化硅膜。接下来，使用光刻技术及RIE法等，如图11所示，在层间绝缘膜90形成接触孔CH。接触孔CH以贯通层间绝缘膜90到达漏极层20及源极层21的方式形成。另外，也可在形成接触孔CH后进行湿法步骤，去除自然氧化膜。
接下来，如图12所示，在源极层21或漏极层20，形成从半导体衬底10的表面F到达低于半导体衬底10的表面F的特定位置P1的孔10h。也就是说，蚀刻半导体衬底10，形成孔10h。更详细来说，流动HCl气体来蚀刻半导体衬底10。由此，如图12所示，不仅在向下方向，在横向(平行于面F的方向)也能蚀刻半导体衬底10，能形成具有比接触孔CH的直径大的直径的孔10h。
图15是表示第1实施方式的接触孔CH及孔10h的形状的一例的示意图。
接触孔CH的形状为大致圆柱状。另一方面，孔10h的形状为大致四角锥状。这是因为，利用使用HCl气体的各向异性蚀刻，容易暴露硅的(111)面。因此，孔10h变为被(111)面覆盖的形状。覆盖孔10h的面为与(111)等效的面即可，以例如(-1-11)、(1-1-1)、(-11-1)、(111)这4个面形成大致四角锥。(111)面为从衬底表面(001)面倾斜53°的表面，但也有出于深度方向的蚀刻速度与横向的蚀刻速度的平衡而在45～60°之间变化的情况。接触孔CH也可为长方体状或狭缝状，根据接触孔CH的形状，覆盖孔10h的面的形状会发生变化。例如，如果接触孔CH为狭缝状，那么孔10h变为大致三角柱状。
接下来，如图13所示，使用外延生长法将外延层50形成在接触孔CH及孔10h内的源极层21或漏极层20的上方。外延层50是掺杂硼及碳这两者同时外延生长的掺杂硅晶体层。例如，硼浓度为1×1021cm-3以上，碳浓度为2×1020cm-3以上。由此，形成含有硼及碳的外延层50。此时，外延层50的上表面例如以具有(001)面的方式外延生长。此外，外延层50形成到作为半导体衬底10的表面的面F附近。另外，在形成接触插塞70时，有外延层50的上表面变低的情况，在图4所示的例中，外延层50的上表面凹陷成扇状。因此，在接触插塞70的底部位于低于面F的位置的范围内，外延层50可形成到略高于面F的位置。
另外，图12及图13的步骤连续执行。也就是说，在外延生长装置投入半导体衬底10后，利用半导体衬底10的HCl各向异性蚀刻形成具有(111)面的孔10h，并在原位(in-situ)成膜外延层50回填孔10h。通过连续执行具有(111)面的孔10h的形成与外延层50的回填，不会在孔10h的界面留下会引起电阻上升的杂质层或损伤层，能形成低电阻且接通电流较大的CMOS元件。通过使半导体装置1在半导体衬底10与外延层50的界面具有硅的(111)面，而获得低电阻且接通电流较大的CMOS元件。
此外，优选为外延层50通过掺杂杂质及碳这两者同时使半导体晶体外延生长而形成。由此，即使施加热负荷，也能高浓度地保持外延层50内的硼，能提高耐热性。
接下来，如图14所示，形成到达GC42的接触孔CHa。此外，通过在接触孔CH、CHa内形成金属材料，外延层50上的接触插塞70及GC42上的接触插塞70a并行形成。接触插塞70以从高于特定位置P1且低于半导体衬底10的表面F的特定位置P2向上方延伸的方式形成。例如，将势垒金属层72较薄地形成在接触孔CH内，进一步在接触孔CH内填充插塞73。对于势垒金属层72，例如使用Ti或TiN。对于插塞73，例如使用钨。由此，形成包含势垒金属层72及插塞73的接触插塞70。由此，获得图3所示的晶体管的构造。之后，也可在晶体管(栅极电极40)的上方，形成图1所示的存储单元阵列MCA。此时，也可利用存储单元阵列MCA的形成步骤中的热负荷，在势垒金属层72与外延层50之间，形成TiSi等硅化物层。
如以上所述，根据第1实施方式，接触插塞70以相对于源极层21或漏极层20突出到比上述衬底的表面更下方的方式设置。此外，外延层50设置在接触插塞70与源极层21或漏极层20之间。由此，能抑制接触电阻。
此外，在晶体管的上方，设置着存储单元阵列MCA。这是因为，与将存储单元阵列MCA设置在晶体管附近的情形相比，能抑制芯片面积，此外，能提高每芯片面积的存储单元阵列MCA的数量(单元密度)。但是，所述情况下，有必要在形成接触插塞70后，形成存储单元阵列MCA。因此，在形成存储单元阵列MCA时的热处理步骤中，对控制电路101及接触插塞70施加热负荷。因所述热负荷，外延层50及扩散层等所包含的杂质硼容易扩散。硼的扩散造成与接触插塞70电连接的外延层50中的硼浓度减少，从而引起接触电阻上升。
通常，作为抑制接触电阻的方法，已知有大量注入硼来提高硼浓度。但是，如果大量注入硼，那么容易产生因硼扩散到沟道区域10c引起的短沟道效应。
与此相对，在第1实施方式中，可不增加硼的注入量，而抑制接触电阻。此外，通过外延层50所包含的碳，能抑制硼从包含相对高浓度的硼的外延层50内扩散。因此，能抑制因热负荷引起的短沟道效应及接触电阻上升。由此，能减少接触电阻同时提高对于硼扩散的耐热性。其结果，能提高控制电路101的特性，此外，能形成更高容量的存储装置。
另外，晶体管未必设置在存储单元阵列MCA的下方。
(第2实施方式)
图16是表示第2实施方式的P型MOSFET的构成例的剖视图。第2实施方式在设置外延层60这点上与第1实施方式不同。
晶体管还具有外延层60。
外延层60设置在源极层21或漏极层20与外延层50之间，使用与外延层50的第1材料不同的第2材料。也就是说，在外延层50的外周设置着外延层60。第1材料例如为Si。第2材料例如为SiGe。SiGe的Ge浓度例如为约1％～约10％。此外，外延层60还包含杂质。杂质例如为硼。
此外，外延层60以由源极层21侧的外延层60及漏极层20侧的外延层60夹着栅极电极40下方的沟道区域10c的方式配置。外延层60的SiGe的晶格常数大于Si。由此，能对沟道区域10c施加压缩应力。其结果，能提高沟道区域10c中的载流子迁移率(空穴的迁移率)。此外，第2材料(SiGe)以对沟道区域10c给予应变的方式选择即可。
此处，dSiGe表示外延层60的膜厚。也就是说，dSiGe也可为从外延层50的底部到外延层60的底部的距离。
外延层60的膜厚例如优选为总膜厚的一半以下。也就是说，优选为ddepth/2＞dSiGe。
另外，晶体管为N型MOSFET的情况下，例如对于外延层60的材料，也可使用SiC或SiN替代SiGe。SiC及SiN的晶格常数小于Si。由此，能对N型MOSFET的沟道区域10c施加拉伸应力，能提高载流子迁移率(电子的迁移率)。此外，外延层60内的杂质例如为磷或砷。
外延层60在图12所示的步骤后形成。也就是说，在形成外延层50之前，使半导体晶体在孔10h内的源极层21或漏极层20的上方外延生长，形成与外延层50的第1材料不同的第2材料的外延层60即可。
因为第2实施方式的半导体装置1的其它构成与第1实施方式的半导体装置1中对应的构成相同，所以省略其详细说明。第2实施方式的半导体装置1能获得与第1实施方式相同的效果。
(第3实施方式)
图17是表示控制电路101的N型MOSFET及P型MOSFET的构成例的剖视图。第3实施方式在设置具有外延层50的N型MOSFET这点上与第1实施方式不同。
在图17所示的例中，在CMOS电路所包含的N型MOSFET及P型MOSFET这两者中，如第1实施方式所说明，设置着接触插塞70及外延层50。此外，在N型MOSFET与P型MOSFET之间，例如设置着绝缘层94。绝缘层94例如为STI(Shallow Trench Isolation：浅沟槽隔离)，将N型MOSFET的P型阱与P型MOSFET的N型阱隔离。
如第1实施方式所说明，在N型MOSFET中，外延层50的杂质例如为磷或砷。此外，在外延层50，与P型MOSFET相同，优选为包含高浓度的杂质，此外，更优选为包含碳，因为它能抑制杂质扩散。
如此，在第3实施方式中，在N型MOSFET及P型MOSFET这两者中，能抑制接触电阻。
因为第3实施方式的半导体装置1的其它构成与第1实施方式的半导体装置1中对应的构成相同，所以省略其详细说明。第3实施方式的半导体装置1能获得与第1实施方式相同的效果。此外，也可将第2实施方式组合到第3实施方式的半导体装置1。也就是说，也可将外延层60设置在N型MOSFET及P型MOSFET这两者。
虽已对本发明的若干个实施方式进行了说明，但所述实施方式是作为例子提示的，并未意图限定发明的范围。所述实施方式可由其它各种方式实施，在不脱离发明主旨的范围内，可进行各种省略、替换、变更。所述实施方式或其变化包含在发明的范围或主旨中，同样地，包含在权利要求书所记载的发明及其均等范围内。
[符号的说明]
10:半导体衬底
10c:沟道区域
10h:孔
20:漏极层
21:源极层
30:栅极绝缘膜
40:栅极电极
50:外延层
60:外延层
70:接触插塞
80:保护膜
90:层间绝缘膜
92:衬膜
CH:接触孔
F:面
MCA:存储单元阵列
P1:特定位置
P2:特定位置。

Claims (15)

1.一种半导体装置，其具备：衬底；及
晶体管，具有：源极层及漏极层，设置在所述衬底的表面区域且包含杂质；栅极绝缘膜，设置在所述源极层与所述漏极层之间的所述衬底上；栅极电极，设置在所述栅极绝缘膜上；接触插塞，以相对于所述源极层或所述漏极层突出到比所述衬底的表面更下方的方式设置；及第1外延层，设置在所述接触插塞与所述源极层或所述漏极层之间，包含所述杂质及碳这两者。
2.根据权利要求1所述的半导体装置，其中所述第1外延层以覆盖突出到比所述衬底的表面更下方的所述接触插塞的方式配置。
3.根据权利要求1所述的半导体装置，其中所述第1外延层的宽度大于所述接触插塞的宽度。
4.根据权利要求1所述的半导体装置，其中所述晶体管为P型MOSFET(Metal OxideSemiconductor Field Effect Transistor：金属氧化半导体场效应晶体管)，
所述杂质为硼。
5.根据权利要求1所述的半导体装置，其中所述第1外延层的杂质浓度为1×1021cm-3以上，碳浓度为2×1020cm-3以上。
6.根据权利要求1所述的半导体装置，其中所述晶体管还具有第2外延层，设置在所述源极层或所述漏极层与所述第1外延层之间，且为与所述第1外延层的第1材料不同的第2材料。
7.根据权利要求6所述的半导体装置，其中所述第2外延层以由所述源极层侧的所述第2外延层及所述漏极层侧的所述第2外延层夹着所述栅极电极下方的沟道区域的方式配置。
8.根据权利要求6所述的半导体装置，其中所述第1材料为Si，
所述第2材料为SiGe。
9.根据权利要求6所述的半导体装置，其中所述第2外延层还包含所述杂质。
10.根据权利要求1所述的半导体装置，其还具备设置在所述晶体管上方的存储单元阵列。
11.根据权利要求10所述的半导体装置，其中所述晶体管为控制所述存储单元阵列的控制电路的一部分。
12.一种半导体装置的制造方法，其具备下述步骤：
在衬底的表面区域导入杂质形成源极层及漏极层，同时形成所述衬底上的栅极绝缘膜及所述栅极绝缘膜上的栅极电极；
在所述源极层或所述漏极层，形成从所述衬底的表面到达低于所述衬底的表面的第1特定位置的第1孔；
使半导体晶体在所述第1孔内的所述源极层或所述漏极层的上方外延生长，形成掺杂了所述杂质及碳这两者的第1外延层；及
在所述第1外延层上，形成从高于所述第1特定位置且低于所述衬底的表面的第2特定位置向上方延伸的接触插塞。
13.根据权利要求12所述的半导体装置的制造方法，其还具备下述步骤：在形成所述第1孔之前，在所述源极层或所述漏极层的所述衬底上形成绝缘层，同时形成贯通所述绝缘层到达所述源极层或所述漏极层的第2孔；及
在所述源极层或所述漏极层，形成到达所述第1特定位置且具有比所述第2孔的直径更大的直径的所述第1孔。
14.根据权利要求12所述的半导体装置的制造方法，其还具备下述步骤：在形成所述第1外延层之前，使半导体晶体在所述第1孔内的所述源极层或所述漏极层的上方外延生长，形成与所述第1外延层的第1材料不同的第2材料的第2外延层。
15.根据权利要求12所述的半导体装置的制造方法，其中所述第1外延层通过掺杂所述杂质及碳这两者同时使半导体晶体外延生长而形成。
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