CN1141507A - 在基片上形成凸起的方法 - Google Patents

在基片上形成凸起的方法 Download PDF

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CN1141507A
CN1141507A CN96108189A CN96108189A CN1141507A CN 1141507 A CN1141507 A CN 1141507A CN 96108189 A CN96108189 A CN 96108189A CN 96108189 A CN96108189 A CN 96108189A CN 1141507 A CN1141507 A CN 1141507A
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masterplate
many
solder
opening
solder flux
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埃里克·M·胡巴什尔
卡尔·G·霍伯纳尔
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Motorola Solutions Inc
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Motorola Inc
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Abstract

在诸如半导体管芯或圆片的基片上，利用筛选成型和回流操作，形成了焊点凸起。焊剂筛进模版的开口。在模版中焊剂回流产生预成型焊点。接着模版和预成型焊点与要形成导电凸起的基片对准，使得预成型焊点与基片上的金属压焊块对准。再次回流焊剂，模版开口内的焊剂被拉到金属压焊块上。为了便于从模版向金属压焊块转移焊剂，可以使用第二块模版在预成型焊点上形成突起。在转移回流操作中，突起接触金属压焊块以便容易从模版中移出焊剂。

Description

在基片上形成凸起的方法
本发明涉及用于在基片上形成导电凸起的方法，例如用于在半导体基片或者印刷电路板上形成焊剂凸起的方法。
倒装片接合法正在成为替代传统引线接合法和条带自动接合(TAB)工艺的一种流行封装。在倒装片接合法中，半导体管芯或芯片和用户基片(例如印刷电路板)的输入输出(I/O)端口之间的互连是通过在半导体管芯的有效表面上形成的导电凸起而实现的。与其他互连方法相比，使用倒装片接合法的优势包括：增加了输入输出端口的密度，从而导致了更小的器件“脚印”；由于短的互连，提高了信号的传输速度；减小了垂直剖面；降低了器件的负载。
用于为倒装片器件形成导电凸起的几种不同的方法已经被提出。其中一种最被接受的用于形成凸起的方法是通过使用一个掩膜的汽相淀  积工艺实现的。在这种工艺中，掩膜上制作出了许多开口，这些开口穿过掩膜并且其图案与要形成凸起的器件的输入输出端轮廓相一致。掩膜与半导体器件对准，然后一种或多种金属通过掩膜就地蒸发。在蒸发过程中，金属通过掩膜的开口淀积到半导体管芯上，而其余地方则不被淀积。在典型蒸发工艺中，首先顺序淀积铬、铜和金的薄层，然后分别淀积稍厚的铅和锡。在所有金属充分淀积之后，移去掩膜。然后淀积到端点压焊块上的铅和锡回流，形成最终的焊接凸起的形状和组分。蒸发工艺具有在半导体管芯或其他基片上形成高质量和均匀体积的导电凸起的优点，同时，也存在着一些制造上的不足。一个缺点就是蒸发金属所需的时间较长和实现工艺所必须的大量资本投入大幅度提高了管芯制造的成本。
利用印有凸起图案的筛网或模版，提出了更为简单的形成导电凸起的工艺。这些工艺不是通过掩膜蒸发金属，而是用具有和要形成凸起的金属压焊块图形相一致的开口的掩膜或模版对焊剂(或一种导电聚合物)进行屏蔽。当模版放置好并且与要形成凸起的基片对准后，屏蔽过程开始，目的是将焊剂填充于开口，并同时湿润下面的金属压焊块。填充之后，从器件上移去模版，以希所有的焊剂保留在端口压焊块上。但实际上，由于焊剂的粘性和模版开口的狭小尺寸，相当一些焊剂随模版一起被移走，而没有留在金属压焊块上。这样不仅导致了材料的浪费，而且还很难预计被模版带走的焊剂量。即使优化工艺从而弥补被模版带走的焊剂量，这样的工艺也不能以恒定结果重复执行。而且，被模版带走的焊剂量在整个模版上也不总是均匀的。从而一些形成的焊剂凸起将具有比其它凸起更大或更小的体积。凸起体积的不均匀会造成后续工艺操作的问题，特别是将倒装片管芯加到用户基片(如印刷电路板)上时。当把管芯贴近基片固定时，不是所有的焊点凸起都将与用户基片上的压焊块形成接触，从而使得即使在为固定管芯而进行回流操作之后，一部分焊点凸起与压焊块仍保持断开状态。
鉴于现有的蒸发导电凸起工艺的生产率和成本以及常规模版或屏蔽图案成形工艺中导电凸起体积的不可控制性，希望有一种改进的工艺。更准确地说，特别希望这种改进的形成导电凸起的工艺能够在低成本下实现，具有足够高的生产率并且对最终凸起的形状、尺寸和体积高度可控。
图1-10通过剖面图顺序说明了根据本发明的一个实施方式在半导体器件上形成导电凸起的工艺。
概括地讲，本发明是一种利用模版和屏蔽操作，在诸如半导体管芯或芯片等基片上形成导电凸起的方法。但是与也利用模版和屏蔽的现有技术工艺不同，本发明能够在要形成凸起的基片上获得均匀的导电凸起体积。通过设计模版开口的尺寸和形状，并且当模版定位在要形成凸起的基片上时通过回流填充于模版开口内的焊剂，就可以获得对体积的控制。换句话说，在筛过开口内的焊剂之后，不移走模版。而是将焊剂筛选进模版的开口中。接着将模版定位到要形成凸起的基片上，当模版保持定位在基片上时，回流焊剂。回流之后，移走模版。
在本发明的更特殊的实施方式中，使用两块模版来形成导电凸起。第一块模版做成含有开口的板，这些开口穿通模版并且与要形成凸起的基片上的金属压焊块具有一致的图形。第二块模版做成含有凹槽的板，这些凹槽没有穿通第二块模版，但是也和第一块模版上的开口以及要形成凸起的基片上的金属压焊块具有一致的图形和位置。第一块和第二块模版互相对准使得开口和凹槽相对应。接着焊剂被筛选进入开口和凹槽中。此时，回流在模版中的焊剂以产生预成型焊点。在最佳的实施方式中，预成型焊点具有截去头部的锥体的形状，此锥体在其顶部具有突起。在预成型焊点形成后，从第一块模版上移去第二块模版以露出各预成型焊点的突起。接着将第一块模版对准要形成凸起的基片使得每个预成型焊点的突起与基片上的一个金属压焊块接触。此时，预成型焊点再次回流。当回流时，与金属压焊块相接触的预成型焊点突起湿润金属压焊块并且将第一块模版的开口中保留的焊剂吸到压焊块上，从而形成导电凸起。
因为本发明工艺依靠回流操作将所有焊剂从精确设定的模版开口中吸出来，所以最终形成导电凸起的焊剂体积能够很好得以控制并且可以以恒定结果重复生产。而且，因为模版上的开口能够制作得很均匀，所以整个其形成有凸起的基片上形成的凸起同样具有均匀的体积。此外通过设计模版上开口尺寸和结构或者通过设计模版可以便利地对可控量的焊剂进行保留和释放。
下面结合附图对本发明作详细的说明，从中可以更加清楚地看到本发明的上述及其他特性和优点。需要指出的是图解没有必要按比例画出而且也可能存在着对于本发明的其他实施方式没有专门作出图解说明。另外出现在不同图中同样的标号，用于表示相同或者相对应的部分。这一点很重要。
图1-10是根据本发明的一个实施方式的如何使用模版在基片上形成导电凸起的剖面图解说明。在本发明所介绍的一个最佳实施方式中，焊剂是形成导电凸起的材料。图1中示出的是第一块模版10和第二块模版12的一部分。第一和第二块模版都是由不可被焊剂或其他任何可用于形成导电凸起的材料所湿润的材料制成。可用于形成导电凸起的合适的模版材料包括钼，某些不锈钢和玻璃。另外，其他含有外部氧化层从而提供了非湿润表面的材料也可以制作模版。在第一块模版10上形成一个开口14，第二块模版12上形成一个凹槽16。虽然在图1和其后的图中只示出了一个开口和一个凹槽，实际上每一块模版都有许多这样的开口和凹槽。每一开口及其相关的凹槽将与要形成凸起的基片上形成的金属压焊块图形及位置对应。因为在大部分场合要形成凸起的基片上将有大量的金属压焊块，所以在模版上需要大量的开口和凹槽。但是为了简化图解和描述，在图1-10中只示出了一个这样的开口。
根据传统工艺在模版上形成开口14和凹槽16。例如，其后将进行适合于模版材料的刻蚀的光刻掩膜工艺能够用于形成开口廷和凹槽。在一个最佳实施方式中，如图1所示，开口14和凹槽16具有锥形或倾斜的侧壁。换句话说也就是在模版一个表面的开口的宽度比模版相对表面的开口的宽度大。锥形的侧壁能够在按照传统方法形成开口和/或凹槽时获得。例如能够使用各向同性刻蚀，同时在不只一个方向上刻蚀模版材料。侧壁的斜面用于帮助将开口内的焊剂移去，随后的描述将使这一点更明显。但是注意锥形侧壁不是必需的特征。垂直侧壁或者与图示相反方向的锥形侧壁，在本发明的实际应用中也可使用，并具有自己制作上的优势。
虽然图1-10图解了一种使用两块模版的工艺，但需要注意的是，在本发明的实际应用中，可能只需要一块模版。本描述的自始至终，都将指出使用两块模版的工艺和使用一块模版工艺的不同之处，以及在导电凸起形成工艺的不同阶段各工序的优劣。就图1而论，第二块模版12是两块模版中非必需的那块。换句话说，在本发明的只使用一块模版的实际应用中，那块模版应该具有许多完全穿通模版的开口而不是具有只是部分穿过模版而形成的凹槽。
如图1所示，第一块模版10和第二块模版12对准使得各个开口14与相对应的凹槽16对准。在模版对准之后，如图2所示，用医用刀片或者刮板20将焊剂18筛入模版。如图所示，当焊剂移过每一个开口和凹槽时，焊剂填充进开口和凹槽。如果只使用一块模版(模版10)，开口14的底部必须盖上以使焊剂留在开口中。例如，可以将一块平板放于模版10下(代替如图2所示的模版12)来保存焊剂。根据本发明，传统的用于形成高温焊剂(97％Pb，3％Sn)，或者低温、易熔焊剂(37Pb，63％Sn)的焊剂都可使用。模版开口和凹槽内的焊剂将在要形成凸起的基片上形成焊点凸起，所以使用高温焊剂还是低温焊剂将取决于所希望的最终凸起的成分。一般来说，高温焊剂通常应用于倒装片固定于陶瓷或者其他高温载体时，而低温焊剂通常应用于倒装片固定于有机体或其他低温载体时。
用焊剂填充开口和凹槽之后，如图3所示，焊剂和模版接着进行热回流操作。回流温度取决于焊剂的成分。在此回流操作中，焊剂中的铅和锡颗粒在助熔剂和粘合剂材料中扩散，合金后形成焊剂材料。焊剂的助熔剂和粘合剂在回流时到达表面。回流之后冷却时，在模版的开口和凹槽中形成了预成形焊点22。在回流时，焊剂中的助熔剂和粘合剂上升到预成型焊点之上，在开口内留下硬的残渣24。如果愿意，可以采用传统的助熔剂清理操作去除残渣层，但是在工艺的本阶段这样的清理并不需要。再有，如果只使用一块模版，需要采用一些回流过程中将焊剂保留于开口中的办法(例如在下部加一块不可湿润的平板)。
因为回流操作涉及到温升，所以希望两块模版(如果使用两块模版)的材料具有相同或相近匹配的热膨胀系数(CTE)以使形成的预成型焊点的形状能够严格控制。理想情况下，两块模版由相同材料制造使得相同的CTE得以保证。虽然CTE失配时保留在开口内配制的焊剂体积不会发生变化，但当冷却和固化焊剂时，预成型焊点形状发生变形或改变也是可能的。
在模版内的焊剂回流之后，移去第二块模版。从图3所示的结构看，模版12可以很简单地从模版10下面移走。但是当移走下面的模版时，预成型焊点将悬在第一块模版的开口14处。如果由于某种原因第一块模版被翻转，预成型焊点可能会从开口中掉落，因为预成型焊点既没有受到模版10的顶部也没有受到模版10底部的支托。(请注意图3所示的方向，预成型焊点可悬在开口内而没有外部支撑，靠内部开口侧壁的坡度或斜面得以支托。)所以为了防止预成型焊点无意中从开口掉落，如图4所示，一块平板26放到了第一块模版10之上。平板26的特殊材料并不特别重要因为提供这块平板仅仅为第一块模版口内的预成型焊点建立了物理安全性。在提供平板26之后，可以移去第二块模版12。再有，第二块模版可以从模版10的下部拉掉。另一种方法，如图5所示，可以翻转第一块模版10，第二块模版12和平板26组成的堆迭结构，再如图6所示从堆迭结构中提走第二块模版12。
无论采用何种方式移去模版12，结果都是露出预成型焊点的突起27。突起27是由第二块模版的凹槽产生的，所以如果只使用一块模版，预成型焊点将没有这样的突起。尽管其他形状，包括完全的锥形，也可使用，但如图所示，突起的形状又会成为截去头部的锥形。使用锥体形状的一个优点(其中凹槽16的侧壁是锥形的)是在形成预成型焊点后便于移去模版。
在形成预成形焊点和移去第二块模版后，如果使用第二块模版的话，在第一块模版内的预成型焊点接着与要形成凸起的基片上的金属压焊块对准。图7所示是一个半导体管芯28的一部分。管芯28包括一个金属压焊块30，它可以是一个输入、输出端压焊块或者是一个作为再分布金属层的一部分的压焊块，用来从输入输出压焊块结构转换为适于形成导电凸起的结构。在半导体管芯28上还包括一个最终的钝化层32。钝化层32覆盖了上述压焊块所处位置之外的管芯28。在金属压焊块30和钝化层32之下，可以是任意数量的层，这些层典型使用于半导体管芯制造中，例如多晶硅层，金属层，钨填料，级间绝缘层，氮化硅层，硅化物，氧化层等等。为了理解本发明，这些下面的层并不重要。因此不再作进一步的讨论。这些下面层，金属压焊块30和钝化层32可能全部在半导体衬底材料上形成，例如硅或其他半导体圆片。总之，这些层和基片衬底材料由图7中的基片34代表。
根据传统工艺金属压焊块30在基片34上形成。在一个实施方式中，其中导电凸起在半导体基片上形成，金属压焊块30由铅形成，具有一个覆盖层或几个阻挡金属层。适当的阻挡金属层包括铬、铜、金和/或钛铜合金。通过在基片上限定出光刻胶，阻挡金属优先电镀到铝层上面，来保护或掩蔽基片上不电镀的地方。在印刷电路板上形成导电凸起时，金属压焊块30下面的金属可以是铜，在其上具有一镀金阻挡层。钝化层32最好是聚酰亚胺，但是也可由氮化硅或二氧化硅层替代，它们被淀积到基片上，形成图形露出金属压焊块。
应该注意到如图7-10所示，模版10内形成的预成形焊点被用于在半导体管芯上形成导电凸起。半导体管芯很可能是一片单独半导体基片上几个管芯中的一个。但是本发明并不只局限于在半导体管芯或圆片上形成导电凸起，理解这一点很重要。本发明对于在其他基片如印刷电路板上形成导电凸起同样有用。正如下面所描述的，本发明将预成型焊点转移到半导体管芯的金属压焊块上的方法同样可以应用于将预成型焊点转移到其他基片的金属压焊块上。换句话说，在其他类型衬底上形成导电凸起，不用增加修改下面所述步骤。
在有了要形成导电凸起的半导体管芯，圆片或者其他基片后，如图8所示，模版10定位于基片之上并与之对准使得预成型焊点位置与金属压焊块30的位置相对应。图8还示出了垫片36。垫片36用于在模版10和半导体管芯28之间建立一个隔离。把模版10放向半导体管芯28直到它放到垫片36上。因此，模版10和半导体管芯分开的距离等于垫片的厚度或高度。更加可取的是垫片的高度最好比突起27的高度略小。垫片建立的隔离是有好处的，因为它允许突起27与金属压焊块30发生物理接触，同时在不保留模版开口的后续回流过程中为焊剂从模版干净地转移到金属压焊块上提供了间隙(见下面参考图9的进一步讨论)。
如图8所示，垫片36包括一个开口区域以容纳突起27和金属压焊块30接触。但是更好的形式是垫片36为环状结构环绕要形成导电凸起的整个基片的周边。例如在形成导电凸起的半导体圆片的范围内，垫片36接近圆片周边，具有圆环形状，并且包围于圆片上的所有管芯。如图8所建议的，垫片没有必要连续而开口只为每个要形成的导电凸起提供。一个简单的圆周垫片形状足以提供所需的隔离，并且具有垫片对准不是关键和垫片制造成本很低的优点。因为仅用于隔离作用，所以垫片36的材料选取并不关键。但是正如下面将要讨论的，垫片将经受温升操作。因此，在垂直方向上(也就是建立隔离的高度方向)垫片所用材料的热膨胀应该在使用优化工艺确保突起27和金属焊块37接触时加以考虑。适合垫片36的材料包括钼，钛，不锈钢或其他在“Z”方向具有相当低的热膨胀系数的材料。
如果仅仅使用一块模版，突起27将不存在，容纳突起和提供隔离的垫片也就没有必要了。代之以将模版和其内形成的预成型焊点直接放到要形成导电凸起的基片之上。预成型焊点最好还是能够与基片金属压焊块形成物理接触。但是表面分布状况(可能不是非常平坦)可能使得在缺少突起的情况下在预成型焊点和金属压焊块之间形成接触的能力复杂化，至少在所有预成型焊点和所有金属压焊块之间是这样的。从这方面看，使用两块模版产生突起比只使用一块模版有优势。
在半导体管芯或者其他要形成导电凸起的基片上将模版和预成形焊点对准后，对整个结构(例如半导体管芯28，垫片36，第一块模版10，预成型焊点22和平板26)进行另一步回流操作。此时，回流操作不是将焊剂中的铅颗粒和锡颗粒进行合金形成预成型焊点，而是将焊剂从预成型焊点转移到金属压焊块上。因为在回流操作之前，突起27已与金属压焊块物理接触，当加热时，焊剂将湿润金属压焊块。当焊剂熔化或回流时，表面张力和重力将如图9所示把焊剂从模版10的开口14中拉下来落到金属压焊块30上。因为此时的焊剂处于熔化或液体状态，因而焊剂呈现出圆形。任何可能是预成型焊点一部分的残渣材料也会转移到半导体管芯上(虽然没有在图中示出)。当转移的焊剂硬化时，可在管芯或圆片上进行传统的助熔或残渣清理操作以从基片上去除不需要的残渣。
如图9所示，垫片36提供的隔离足够允许移去第一块模版10的开口14内的所有焊剂。换句话说，在要形成导电凸起的基片和模版之间有足够的间隙允许焊剂从模版开口拉到金属压焊块之上而不沿模版开口的侧壁遗留焊剂。焊剂转移工序的结果是在金属压焊块30上形成了焊点凸起38。如图所示，还注意到焊点凸起38具有比开口14最窄部分的直径还小的直径或宽度。这样使得焊剂转移操作之后能够从半导体管芯28提起模版10而不破坏形成的焊点凸起。为了保证形成的焊点凸起的尺寸比开口14最窄部分还小，应该控制开口14中的焊剂体积。当选择所需的最终焊点凸起体积时，根据用于填充模版开口的焊剂的体积组成，决定了开口14的恰当尺寸。对于每一个焊点凸起的给定体积，这些凸起的直经可以以同样方式决定，并且模版的开口和垫片的厚度能够设计以容纳凸起的直径。
一旦焊剂从模版10的开口14内转移到金属压焊块30上，模版10，平板26和垫片36便从半导体管芯28上移去，工艺完成。最后结构是一个有焊点凸起的管芯，如图10所示。
如果只使用一块模版(模版10)转移焊剂到金属压灶块上，就不用使用垫片了。代之以将模版直接放到要形成导电凸起的基片上，最好使得预成型焊点与金属压焊块形成物理接触。然后模版中的焊剂回流。没有垫片，也就不会发生从模版开口到金属压焊块的焊剂的“下拉”。而是回流时模版中的焊剂将简单地湿润金属压焊块，留下焊剂束缚在模版开口内。当冷却时，焊剂和金属压焊块之间形成冶金结，但是焊剂(硬化预成型焊点形式)仍在模版开口内。这时模版从基片上提起，将焊剂留在金属压焊块上。为了提起模版又不移走焊剂，第一块模版10上开口14的侧壁必须是直的(垂直的)或者外向锥形的(与所示方向相反)。否则，当焊剂与金属压焊块冶金接合时，焊剂将塞进模版，以致无法移去模版。模版开口内的焊剂的表面张力使得不带走焊剂而移走模版受到阻碍。因此，两块模版工艺的应用，或者其他在预成型焊点上获得突起，并且在焊剂转移时使用隔离间隙以便允许地从模版开口下拉焊剂的工艺是实现本发明的推荐办法。当移去模版时进行附加的回流操作使金属压焊块上的导电凸起变形为自由形态的圆球形状，如图10所示。没有这一附加回流操作，金属压焊块上的导电凸起将具有模版开口的形状，并且包含移走模版引起的的任何表面损坏。紧接着的回流操作将减弱引起的任何焊点凸起损坏的效应。
实现本发明，在半导体管芯或其他基片上形成焊点凸起有几个优点。一个优点是避免了昂贵的蒸发、设备和材料(用于焊剂淀积)。另外，根据本发明获得了简单的筛选成形操作，它比用蒸发技术淀积铅和锡形成焊点凸起快很多。同时，从高度体积控制和均匀性上看，本发明具有与蒸发技术同样的优点。为实现本发明，所用到的模版能够精确设计以产生给定体积的焊点凸起。此外，可以保证模版开口内的所有焊剂转移到要形成导电凸起的基片的金属压焊块上。当模版正好在基片上时，通过回流模版开口内的焊剂，保证了开口内所有焊剂完全转移到金属压焊块上。通过提供与金属压焊块物理接触的焊剂突起，帮助从模版下拉焊剂，使得从模版向金属压焊块转移焊剂更容易。
因此，很显然根据本发明提出了一种完全满足前面提到的要求和优点的在基片上形成导电凸起的方法。虽然本发明是参照特定实施方式进行的描述和图解，但是本发明并不是局限于这些示意的实施方式。本领域熟练人员可对其作修改和变更但仍不脱离本发明的精神。例如，本发明没有限制所示预成型焊点的精确形状。本发明也不需要使用预成型焊点上的突起。另外，本发明也不局限于在此所述的特定模版，垫片或平板材料。此外，除了焊剂之外其他材料也能形成导电凸起，例如导电热塑聚合物。本发明也不局限于在任何特定类型基片上形成导电凸起。所以，在此指出本发明包括所有属于后附的权利要求范围内的修改和变化。

Claims (9)

1.一种在基片上形成凸起的方法，其特征在于：它包括以下步骤，
提供具有许多金属压焊块(30)的半导体基片(28)；
提供具有许多与所述许多金属压焊块图形一致的开口(14)的模版(10)；
用焊剂(18)填充所述模版的所述许多开口；
在所述半导体基片上定位所述模版，将所述许多开口对准所述许多金属压焊块；以及
回流所述许多开口内的所述焊剂在所述许多金属压焊块的每一个上形成焊点凸起(38)。
2.如权利要求1所述的方法，其特征在于：它还包括以下步骤，在所述定位步骤之前，回流所述许多开口中的焊剂，以形成许多预成型焊点(22)。
3.如权利要求1，2或3所述的方法，其特征在于：它还包括以下步骤，在回流所述许多开口中的焊剂以便于所述许多金属压焊块的每一个上形成焊点凸起的步骤之前，在所述模版和所述半导体基片之间放一个垫片(36)。
4.如权利要求1，2或3所述的方法，其特征在于：在提供模版的步骤中，对所提供的模版，其上所述许多开口中的每一个完全穿通一个模版的厚度并且具有向内倾斜的倾斜侧壁。
5.一种在半导体圆片上形成凸起的方法，其特征在于：它包括以下步骤，
提供在其表面形成的具有许多凸起压焊块(30)的半导体圆片(28)；
提供一块不能被焊剂(18)湿润的模版(10)，所述模版具有许多开口(14)，每个开口具有均匀的，可控制的体积；
将焊剂分散到所述模版的所述许多开口中；
第一次回流所述模版中的所述焊剂形成许多预成型焊点(22)，每个预成型焊点与相应的开口的尺寸和形状相一致。
邻近所述半导体圆片定位所述模版使得所述许多预成型焊点与所术许多凸起压焊块对准并接触；以及
当所述模版还邻近所述半导体圆片时，第二次回流所述许多预成型焊点在所述许多凸起压焊块的每一个上形成焊点凸起(38)。
6.如权利要求5所述的方法，其特征在于：在提供模版的步骤中，对所提供的模版，其中在定位步骤中邻近所述半导体基片的所述模版表面上，所述许多开口中的每一个开口都有一个开口宽度，当回流所述许多开口中的所述焊剂在所述许多金属压焊块的每一个上形成焊点凸起时，每一个焊点凸起都有一个凸起宽度，每个开口的所述开口宽度比它所对应的焊点凸起的所述宽度要大。
7.如权利要求5所述的方法，其特征在于：在提供模版的步骤中，对所提供的模版，其中所述许多开口中的每一个开口完全穿通所述模版的厚度，其中每一开口在具有第一宽度所述的模版的第一表面上具有第一终止面和在具有比第一宽度小的第二宽度的所述模版的第二表面上具有第二终止面，其中所述定位步骤的特征在于在所述半导体圆片上定位所述模版，使得所述模版的第二表面邻近所述半导体圆片。
8.一种在基片上形成凸起的方法，其特征在于：它包括以下步骤，
提供具有许多端口压焊块(30)的基片(28)；
提供具有许多开口(14)的第一模版(10)，所述许多开口穿通所述第一模版并且在位置上与所述许多端口压焊块相一致；
提供具有许多凹槽(16)的第二模版(12)，所述许多凹槽在位置上与所述许多开口相一致；
对准所述第一模版与第二模版使得所述许多凹槽与所述许多开口对准；
将焊剂(18)分散进入所述许多开口和所述许多凹槽中；
回流所述第一模版和所述第二模版里的所述焊剂以形成许多预成形焊点(22)；
移去所述第二模版，将所述许多预成形焊点留在所述第一模版中；
所述第一模版与所述基片对准使得所述许多预成形焊点在位置上与所述许多端口压焊块相一致；以及
回流所述许多预成型焊点，在所述基片的许多端口压焊块上形成许多焊点凸起(38)。
9.如权利要求8所述的方法，其中，作为移去所述第二模版的结果，所述许多预成型焊点的许多突起露出，其中，所述许多突起是由所述第二模版的所述许多凹槽形成的。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100388449C (zh) * 2002-06-03 2008-05-14 株式会社电装 在基片上形成凸块的方法
CN103681360A (zh) * 2012-09-20 2014-03-26 台湾积体电路制造股份有限公司 封装器件及方法
CN104425294A (zh) * 2013-08-23 2015-03-18 南茂科技股份有限公司 一种植球装置及其植球方法

Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5806753A (en) * 1995-12-22 1998-09-15 International Business Machines Corporation Application of low temperature metallurgical paste to form a bond structure to attach an electronic component to a carrier
JP3385872B2 (ja) * 1995-12-25 2003-03-10 三菱電機株式会社 はんだ供給法およびはんだ供給装置
DE19634646A1 (de) * 1996-08-27 1998-03-05 Pac Tech Gmbh Verfahren zur selektiven Belotung
FR2762714A1 (fr) * 1997-04-28 1998-10-30 Novatec Procede de realisation et de brasage de billes de connexion electrique sur des composants electroniques et materiel a cet effet
FR2762715B1 (fr) * 1997-04-28 2000-07-21 Novatec Procede de realisation et de brasage de billes de connexion electrique sur des plages d'accueil de raccordement electrique de circuits ou de composants electroniques et dispositif de mise en oeuvre
US6162661A (en) * 1997-05-30 2000-12-19 Tessera, Inc. Spacer plate solder ball placement fixture and methods therefor
KR100278219B1 (ko) * 1997-06-18 2001-01-15 클라크 3세 존 엠. 플립칩과볼그리드어레이(bga)를상호접속시키는방법
US5961032A (en) * 1997-06-30 1999-10-05 International Business Machines Corporation Method of fabrication of a multi-component solder column by blocking a portion of a through hole in a mold
US6337522B1 (en) * 1997-07-10 2002-01-08 International Business Machines Corporation Structure employing electrically conductive adhesives
US6297559B1 (en) 1997-07-10 2001-10-02 International Business Machines Corporation Structure, materials, and applications of ball grid array interconnections
US6120885A (en) 1997-07-10 2000-09-19 International Business Machines Corporation Structure, materials, and methods for socketable ball grid
US5984164A (en) 1997-10-31 1999-11-16 Micron Technology, Inc. Method of using an electrically conductive elevation shaping tool
US6225205B1 (en) * 1998-01-22 2001-05-01 Ricoh Microelectronics Company, Ltd. Method of forming bump electrodes
US6321438B1 (en) 1998-05-01 2001-11-27 Scimed Life Systems, Inc. Method of applying a matching layer to a transducer
US6193143B1 (en) * 1998-08-05 2001-02-27 Matsushita Electric Industrial Co., Ltd. Solder bump forming method and mounting apparatus and mounting method of solder ball
US6136689A (en) * 1998-08-14 2000-10-24 Micron Technology, Inc. Method of forming a micro solder ball for use in C4 bonding process
US6998711B1 (en) 1998-08-14 2006-02-14 Micron Technology, Inc. Method of forming a micro solder ball for use in C4 bonding process
US6139972A (en) * 1998-10-26 2000-10-31 Agilent Technologies Inc. Solder paste containment device
US6592943B2 (en) * 1998-12-01 2003-07-15 Fujitsu Limited Stencil and method for depositing solder
US6085968A (en) * 1999-01-22 2000-07-11 Hewlett-Packard Company Solder retention ring for improved solder bump formation
US6451127B1 (en) 1999-06-01 2002-09-17 Motorola, Inc. Conductive paste and semiconductor component having conductive bumps made from the conductive paste
US6047637A (en) * 1999-06-17 2000-04-11 Fujitsu Limited Method of paste printing using stencil and masking layer
JP3403677B2 (ja) * 1999-09-06 2003-05-06 マイクロ・テック株式会社 半田ボール形成方法
US6555398B1 (en) * 1999-10-22 2003-04-29 Magic Corporation Software programmable multiple function integrated circuit module
US6878396B2 (en) * 2000-04-10 2005-04-12 Micron Technology, Inc. Micro C-4 semiconductor die and method for depositing connection sites thereon
US6499215B1 (en) * 2000-06-29 2002-12-31 International Business Machines Corporation Processing of circuit boards with protective, adhesive-less covers on area array bonding sites
US6378759B1 (en) * 2000-07-18 2002-04-30 Chartered Semiconductor Manufacturing Ltd. Method of application of conductive cap-layer in flip-chip, COB, and micro metal bonding
US6853087B2 (en) 2000-09-19 2005-02-08 Nanopierce Technologies, Inc. Component and antennae assembly in radio frequency identification devices
TW556232B (en) * 2000-10-24 2003-10-01 Nanopierce Technologies Inc Method and materials for printing particle-enhanced electrical contacts
US7093746B2 (en) 2002-05-17 2006-08-22 Fry's Metals, Inc. Coated stencil with reduced surface tension
US6988652B2 (en) 2002-05-17 2006-01-24 Fry's Metals, Inc. Solder printing using a stencil having a reverse-tapered aperture
US6998334B2 (en) * 2002-07-08 2006-02-14 Micron Technology, Inc. Semiconductor devices with permanent polymer stencil and method for manufacturing the same
US20040140591A1 (en) * 2003-01-17 2004-07-22 Zaher Faraj Heat applied melted-on faceted beads
US7043830B2 (en) * 2003-02-20 2006-05-16 Micron Technology, Inc. Method of forming conductive bumps
US7449780B2 (en) * 2003-03-31 2008-11-11 Intel Corporation Apparatus to minimize thermal impedance using copper on die backside
US20040198082A1 (en) * 2003-04-07 2004-10-07 Victor Zaderej Method of making an electrical connector
DE10332573B4 (de) * 2003-07-14 2007-08-16 Siemens Ag Verfahren zum Erzeugen von Lotkontakten auf Bauelementen
US7353983B2 (en) * 2003-10-28 2008-04-08 Temic Automotive Of North America, Inc. Vertical removal of excess solder from a circuit substrate
WO2006126361A1 (ja) * 2005-05-24 2006-11-30 Matsushita Electric Industrial Co., Ltd. ハンダバンプ形成方法および半導体素子の実装方法
JP4586745B2 (ja) * 2006-02-27 2010-11-24 住友電装株式会社 基板への端子取付構造
KR100790447B1 (ko) * 2006-06-30 2008-01-02 주식회사 하이닉스반도체 플립 칩 본딩 패키지의 범프 형성방법
TWI337386B (en) * 2007-02-16 2011-02-11 Chipmos Technologies Inc Semiconductor device and method for forming packaging conductive structure of the semiconductor device
FR2913145B1 (fr) * 2007-02-22 2009-05-15 Stmicroelectronics Crolles Sas Assemblage de deux parties de circuit electronique integre
DE102007028811A1 (de) * 2007-06-20 2008-12-24 Phoenix Contact Gmbh & Co. Kg Zwangsführung eines Verbindungsmaterials
GB0716716D0 (en) * 2007-08-29 2007-10-10 Cambridge Silicon Radio Ltd Chip mounting
WO2017066930A1 (en) * 2015-10-21 2017-04-27 GM Global Technology Operations LLC Systems and methods for reinforced adhesive bonding using textured solder elements
US9661794B1 (en) * 2016-07-13 2017-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing package structure
EP3809807B1 (en) * 2019-10-18 2024-07-24 Heraeus Materials Singapore Pte. Ltd. Manufacturing and tape transfer method for a patterned preform
US11476128B2 (en) * 2020-08-25 2022-10-18 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US11935777B2 (en) * 2021-12-01 2024-03-19 STATS ChipPAC Pte Ltd. Semiconductor manufacturing equipment and method of providing support base with filling material disposed into openings in semiconductor wafer for support

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4865654A (en) * 1986-10-03 1989-09-12 Texas Instruments Incorporated Delayed reflow alloy mix solder paste
JPH026030A (ja) * 1988-06-24 1990-01-10 Sumitomo Metal Ind Ltd Ｐｃ鋼棒のディンプル加工装置
US5048747A (en) * 1989-06-27 1991-09-17 At&T Bell Laboratories Solder assembly of components
JP2931011B2 (ja) * 1990-01-31 1999-08-09 株式会社東芝 バンプの形成方法
JP3021508B2 (ja) * 1990-02-13 2000-03-15 住友金属工業株式会社 導電突起の形成方法
JPH0590271A (ja) * 1991-09-27 1993-04-09 Oki Electric Ind Co Ltd バンプ電極形成方法
US5219117A (en) * 1991-11-01 1993-06-15 Motorola, Inc. Method of transferring solder balls onto a semiconductor device
US5244143A (en) * 1992-04-16 1993-09-14 International Business Machines Corporation Apparatus and method for injection molding solder and applications thereof
US5281684A (en) * 1992-04-30 1994-01-25 Motorola, Inc. Solder bumping of integrated circuit die
JP2809952B2 (ja) * 1992-11-27 1998-10-15 ローム株式会社 ハンダバンプ形成方法
JPH06232134A (ja) * 1993-02-02 1994-08-19 Rohm Co Ltd 電子部品におけるバンプ電極の形成方法
US5346118A (en) * 1993-09-28 1994-09-13 At&T Bell Laboratories Surface mount solder assembly of leadless integrated circuit packages to substrates
US5492266A (en) * 1994-08-31 1996-02-20 International Business Machines Corporation Fine pitch solder deposits on printed circuit board process and product

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100388449C (zh) * 2002-06-03 2008-05-14 株式会社电装 在基片上形成凸块的方法
CN103681360A (zh) * 2012-09-20 2014-03-26 台湾积体电路制造股份有限公司 封装器件及方法
CN104425294A (zh) * 2013-08-23 2015-03-18 南茂科技股份有限公司 一种植球装置及其植球方法

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EP0753988A2 (en) 1997-01-15
KR970008441A (ko) 1997-02-24
EP0753988A3 (en) 1997-01-22
US5762259A (en) 1998-06-09
JPH09102499A (ja) 1997-04-15

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