CN105810603A - 形成用于芯片堆叠的体积减少的互连的方法及其互连 - Google Patents

形成用于芯片堆叠的体积减少的互连的方法及其互连 Download PDF

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CN105810603A
CN105810603A CN201610031246.4A CN201610031246A CN105810603A CN 105810603 A CN105810603 A CN 105810603A CN 201610031246 A CN201610031246 A CN 201610031246A CN 105810603 A CN105810603 A CN 105810603A
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conductive structure
interconnection
volume
pad
electrical contact
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CN105810603B (zh
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P·A·格鲁伯
佐久间克幸
D－Y·史
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International Business Machines Corp
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International Business Machines Corp
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Abstract

一种形成用于包括多个硅层的芯片堆叠的体积减少的互连的方法，该方法包括：形成多个导电结构，导电结构的至少一个子集中的每个导电结构具有针对导电结构被转移到其上的对应凸块下冶金焊盘的导电材料的体积，该体积被配置为使得导电结构的未回流直径与对应焊盘的直径的比率为约三分之一比一或更小；将导电结构转移到硅层；在基本上竖直的维度上堆叠硅层，使得给定硅层上的导电结构中的每个导电结构与邻近硅层的下侧上的对应电接触位置对准；以及加热互连，以便以冶金方式键合邻近硅层的多个电接触位置。

Description

形成用于芯片堆叠的体积减少的互连的方法及其互连
技术领域
本发明总体涉及电气、电子和计算机领域，并且更具体地涉及集成电路(IC)互连。
背景技术
三维(3D)芯片堆叠依靠硅层之间的金属化互连结构来实现相应芯片之间的电连通。顾名思义，芯片堆叠指的是其中完整的计算机芯片(例如动态随机存取存储器(DRAM))被放置在另一芯片(例如中央处理单元(CPU))的顶部上的IC封装方法。作为结果，传统上在电路板上相距数厘米的两个芯片现在相距不到一毫米。这减少了功率消耗，并且还大量改善了带宽。
虽然存在用于制造3D互连结构的若干选项，但是焊接仍然是最普及的一种。然而，镀敷、蒸发或者其它焊料沉积方法通常是昂贵和复杂的，并限制了可以使用的合金。附加地，常规焊料沉积方法在邻近芯片之间产生间隔(在本文中称为相隔高度)，这显著增加了芯片堆叠的整体封装高度并且此外不足以用于高频信号。较短的互连接线将会降低平均寄生负载电容和电阻这两者。在移动应用行业市场上，还存在使总堆叠封装高度尽可能低的需求。
发明内容
依照本发明的实施例，本发明的原理提供用于减少3D芯片堆叠中的互连高度的技术。在一个方面中，形成用于包括多个硅层的芯片堆叠的体积减少的互连的方法包括：形成多个导电结构，导电结构的至少一个子集中的每个导电结构具有针对导电结构被转移到其上的对应凸块下冶金焊盘的导电材料的体积，该体积被配置为使得导电结构的未回流直径与对应焊盘的直径的比率为约三分之一比一或更小；将导电结构转移到硅层；在基本上竖直的维度上堆叠硅层，使得给定硅层上的导电结构中的每个导电结构与邻近硅层的下侧上的对应电接触位置对准；以及加热互连，以便以冶金方式键合邻近硅层的多个电接触位置，使得对应邻近硅层上的对准的电接触位置之间的导电结构中的至少给定导电结构塌陷以减少对应邻近硅层之间的互连间隙。
依照本公开的另一实施例，形成用于包括多个硅层的芯片堆叠的体积减少的电互连的方法包括：形成多个导电结构；将导电结构转移到硅层；在基本上竖直的维度上堆叠硅层，使得给定硅层上的导电结构中的每个导电结构与邻近硅层的下侧上的对应电接触位置对准；以及加热互连，以便以冶金方式键合邻近硅层的多个电接触位置，使得对应邻近硅层上的对准的电接触位置之间的导电结构中的至少给定导电结构塌陷以减少对应邻近硅层之间的互连间隙。导电结构的至少一个子集中的每个导电结构被形成为具有如下的导电材料的体积，该体积被配置为使得导电结构和形成在邻近硅层的对应相对表面上的对应对准的凸块下冶金(UBM)焊盘之间的结中的金属间化合物的百分比为导电材料的总体积的约40％或更多。
根据本公开的一个方面，用于3D芯片堆叠的体积减少的电互连包括：具有形成在其表面上的多个电接触位置的多个硅层；多个UBM焊盘，UBM焊盘中的每个UBM焊盘被形成在硅层中的对应硅层和电接触位置中的对应电接触位置之间；以及多个导电结构，导电结构中的每个导电结构与电接触位置中的对应电接触位置对准，并且具有针对UBM焊盘中的对应UBM焊盘的导电材料的体积，该体积被配置为使得导电结构的未回流直径与对应焊盘的直径的比率为约三分之一比一或更小。互连被配置为使多个硅层在基本上竖直的维度上堆叠，使得给定硅层上的导电结构中的每个导电结构与邻近硅层的下侧上的对应电接触位置对准。当导电结构被加热至规定温度时，导电结构以冶金方式键合邻近硅层的电接触位置，使得对应邻近硅层上的对准的电接触位置之间的导电结构中的至少一个给定导电结构塌陷，以由此减少对应邻近硅层之间的互连间隙。
依照本公开的另一方面，用于3D芯片堆叠的体积减少的电互连包括：具有形成在其表面上的多个电接触位置的多个硅层；多个UBM焊盘，UBM焊盘中的每个UBM焊盘形成在硅层中的对应硅层和电接触位置中的对应电接触位置之间；以及多个导电结构。导电结构中的每个导电结构与电接触位置中的对应电接触位置对准，并且具有针对UBM焊盘中的对应UBM焊盘的导电材料的体积，该体积被配置为使得导电结构的未回流直径与对应焊盘的直径的比率为约三分之一比一或更小。导电结构的至少一个子集中的每个导电结构被形成为具有如下的导电材料的体积，该体积被配置为使得导电结构和形成在邻近硅层的对应相对表面上的对应对准的UBM焊盘之间的结中的金属间化合物的百分比为导电材料的总体积的约40％或更多。
如本文中使用的，“便于”动作包括执行动作、使动作更容易、有助于执行动作、或者使得动作被执行。因此，通过示例而非限制的方式，通过发送适当的数据或命令以使得或帮助动作被执行，一个处理器上执行的指令可以便于由远程处理器上执行的指令所执行的动作。为了避免疑惑，在行动者通过除了执行动作之外的其它方式来便于动作的情况下，动作仍由一些实体或实体的组合来执行。
本发明的技术可以提供显著的有益技术效果。例如，一个或多个实施例可以提供减少的相隔高度，这减少了互连的整体高度/尺寸并且减少了堆叠封装高度，提高了功率效率，增加了带宽和/或减少了成本。
这些和其它特征以及本发明的优点将从要结合附图来阅读的其说明性实施例的以下详细描述中变得显而易见。
附图说明
以下附图仅通过示例的方式并且非限制性地给出，其中相同的附图标记(当使用时)贯穿若干视图指示对应元件，并且其中：
图1A和1B是描绘其中可以采用根据本发明的一个或多个实施例的技术的示例性3D芯片堆叠的至少一部分的剖视图；
图2是概念性地描绘用于3D芯片堆叠的示例性受控塌陷芯片连接(C4)和示例性低体积互连之间的比较的剖视图；
图3A至3E是描绘用于形成在硅层之间的标准(即，全)高度的互连结构的说明性受控塌陷芯片连接新工艺(C4NP)的焊料转移工艺的至少一部分的剖视图；
图4A至4E是描绘根据本发明的实施例的用于形成三维芯片堆叠的体积减少的互连的示例性工艺的至少一部分的剖视图；
图5A和5B是概念性地描绘在凸块下冶金(UBM)焊盘之上的分别使用单个中心预制体(perform)和多个间隔预制体的焊料回流工艺的剖视图；以及
图6A至6E是描绘根据本发明的实施例的用于形成包括体积减少的互连的三维芯片堆叠的示例性工艺的至少一部分的剖视图。
要理解的是，图中的元件为了简单和清楚而被图示。可能在商业上可行的实施例中有用或必要的常用但公知的元件可能未示出，以便于图示实施例的较少受阻视图。
具体实施方式
本文中将在用于3D芯片堆叠的说明性互连结构及其制造方法的情形中描绘本发明的实施例。然而，要理解的是，本发明并不限于本文中说明性地示出和描述的具体装置和/或方法。更确切地说，本发明的实施例涉及用于降低芯片堆叠的邻近硅层之间的互连高度的体积减少的互连。而且，对于向其给出本文中的教导的本领域技术人员将变得显而易见的是，可以对所示实施例做出在所要求保护的发明的范围内的众多修改。因此不旨在或不应推断关于本文中示出和描述的实施例的限制。
如前所述，3D芯片堆叠依靠形成在邻近硅层之间的金属化互连结构以用于提供在它们之间的电连通；焊料仍然是用于制造这些互连结构的优选选项。不幸的是，镀敷、蒸发或其它焊料沉积方法往往是昂贵、复杂的，并且限制了可以使用的合金。受控塌陷芯片连接新工艺(C4NP)半导体封装技术(作为电镀处理的替代)克服了这些限制中的一些限制。然而，C4NP技术产生了大幅增加芯片堆叠的整体高度并且通常不能良好地适用于高频信号传输的相隔高度。
图1A和图1B是描绘其中可以采用根据本发明的一个或多个实施例的技术的示例性3D芯片堆叠的至少一部分的剖视图。芯片堆叠模块100包括电连接到中介体108的基板102，中介体108通过第一多个导电结构110(例如C4焊料球)的方式竖直堆叠在基板的至少一部分上方。诸如例如硅、玻璃或有机中介体之类的中介体108可以包括例如使用第一多个导电结构110(例如C4焊料球)竖直定位在基板的至少一部分上方的微处理器或其它电路部件。如图所示，中介体108与一个或多个其它裸片112电连接，一个或多个其它裸片112中的每个裸片可以例如包括使用对应多个导电结构114竖直堆叠在中介体的至少一部分上方的存储器。
用于将中介体108和各种堆叠裸片112电互连的一种技术(其可能是最复杂的)是通过使用诸如例如穿硅过孔(TSV)或穿玻璃过孔(TGV)之类的导电过孔。在TSV的情况下，竖直导电通道(例如铜、钨)被构建到每个裸片中，使得当它们被放置在彼此的顶部上时，TSV将芯片连接在一起。具体参照图1B，其图示图1A中描绘的示例性芯片堆叠模块100的一部分，第一多个过孔118(例如TSV或TGV)被形成为穿过中介体108，以用于连接第一多个导电结构110与形成在中介体的上表面上的接线层120。被形成为穿过相应裸片112的第二多个过孔(例如TSV)122用于将对应导电结构114彼此连接。在这一实施例中，使用倒装芯片技术来实现3D芯片堆叠模块100，并且底部填充材料116被用于在芯片之间(例如在芯片112之间或者在中介体108和芯片112之间)以及在芯片和基板之间(例如在中介体108和基板102之间)的空间中，主要用于增加芯片堆叠模块的结构完整性。
图2是概念性地描绘用于3D芯片堆叠的示例性受控塌陷芯片连接(C4)和示例性低体积互连之间的比较的剖视图。两种类型的互连被示出为形成在共同基板202上。在C4互连的情况下，芯片204经由一个或多个C4焊料球206与基板202上的对应电路电连接。每个焊料球206优选接触分别形成在基板202和芯片204的表面上的对应润湿焊盘208和210，润湿焊盘彼此对准。在焊料206和润湿焊盘208、210之间的结处，在键合或焊料回流工艺期间，特别是当使用C4焊料球时，形成金属间化合物(IMC)212；在这一图示中，使用80微米的C4焊料球。
在低体积焊料互连的情况下，芯片214经由一个或多个低体积无铅焊料结构与基板202上的对应电路电连接。低体积焊料结构优选附接至分别在基板202和芯片214的表面上的对应润湿焊盘218和220。不像标准100微米C4焊料球，非常小的焊料体积(例如，如在所示示例中，高度小于约十微米)在键合或回流工艺期间形成在焊料结构223和相应润湿焊盘218、220之间的结中的IMC222。至少部分由于用于形成互连的导电材料(例如焊料)的减少的体积，相比于标准C4工艺中的润湿焊盘208和210之间的IMC212的百分比(例如通常为约10％或更少)，针对根据本发明的一个或多个实施例的低体积焊料结构的在润湿焊盘218和220之间的结中的IMC222的百分比将显著更高(例如约40％或更多)。
C4焊料互连要求比低体积焊料互连更大的球间间隔和更高的接合间隙。诸如例如锡(Sn)或铟(In)或者包括锡、银和/或铜、锡/银/铜(Sn/Ag/Cu)、锡/银(Sn/Ag)等的合金之类的无铅焊料互连可以在相对低的温度下接合，并且形成具有比低键合温度高得多的熔融温度的金属间相。例如，铟的熔点为156摄氏度(℃)，并且所得的Cu/InIMC的熔点预期大于约400℃；高于后续键合中的标准焊料回流温度(260℃)。这对于3D芯片堆叠工艺来说是期望的特征，因为需要高的热稳定性以允许针对后续芯片堆叠组件或者针对其它后续裸片堆叠或模块级组件重复相同键合工艺步骤。另外，低温键合工艺有潜力克服诸如合金化期间的晶片或芯片翘曲之类的问题。
低体积焊料互连的一些益处包括但不限于：(i)在3D裸片堆叠内增加的竖直传热；(ii)向细节距互连设计规则的延伸；和(iii)用于低温键合而且还支持具有比C4互连更少的重熔的后续工艺步骤的温度分级。温度分级支持测试和成品裸片(KGD)堆叠的创建，而无裸片堆叠互连在针对模块级组件或向板的表面安装组件的回流期间再次熔融的风险。一旦创建，IMC键合具有良好的热稳定性。
图3A至3E是描绘用于形成在硅层之间的标准(即，全)高度的互连结构的说明性C4NP焊料转移工艺的剖视图。参照图3A，模具302包括在模具的上表面305中的多个洼部或腔304。在这一实施例中，腔304中的每个腔具有梯形截面，并且未完全延伸穿过模具302。依照一个或多个实施例，这样的梯形形状通过聚酰亚胺中的激光烧蚀而产生。通常聚酰亚胺(PI)层被激光烧蚀并且形成渐窄侧壁。C4NP模具通常是玻璃，并且在这一实施例中，腔304的截面形成平头半球。
如将由本领域技术人员理解的，腔304适于接收其可以经由注射模塑工艺等以熔融形式被引入到腔中的焊料或替代导电材料。合金灵活性包括多组分无铅合金。腔304中的每个腔的宽度和深度将限定所得到的互连结构的体积。
在本发明的一个实施例中，模具302可以使用诸如例如硼硅酸盐玻璃之类的半导体材料来形成，但是本发明不限于玻璃模具。如上所述，当使用硼硅酸盐玻璃时，在一个或多个实施例中，腔304将通过刻蚀形成为具有形状为平头半球的截面。玻璃模具是可重复使用的，从而保持低成本。
如图3B所示，模具302中的腔304中的每个腔填充有导电材料306，导电材料306优选为熔融焊料，并且基本上与模具的上表面305在同一平面上。如图3C所示，一旦允许腔304中的熔融焊料材料306固化，模具302被反转(即，上下颠倒)并且被放置在对应工件308的上表面307上的凸块下冶金(UBM)焊盘309之上，工件308可以是形成3D芯片堆叠的多个芯片之一。在这一实施例中，UBM焊盘309的至少一个子集中的每个UBM焊盘309的宽度E略微大于腔304中的对应腔304的宽度。在图3D中，固体导电结构310(例如固体焊料结构)从模具302转移到工件308的上表面。在导电材料转移的处理中，模具中的所有焊料再次熔融，并且被转移到硅晶片的UBM结构中，并且然后固化。邻近导电结构310之间的间隔或节距被设置为规定距离A。虽然本发明不限于任何特定节距A，但是邻近导电结构310之间的间隔应该被选择为使得即使在后续工艺之后，也不会发生电短路。
在标准C4NP处理中，导电结构310中的每个导电结构310的体积将被选择为使得导电结构的直径基本上等于节距A的二分之一。参照图3E，当竖直堆叠在彼此之上时，对应工件(芯片)308上的导电结构将形成邻近工件之间的互连312。互连312具有与其相关联的相隔高度，其限定邻近芯片308之间的、在本文中称为标准界面间隙的最小间隔B。互连312的形状将主要归因于形成互连的焊料(或者在其它实施例中的其它材料)的表面张力。
利用标准体积焊料凸块，最小间隔B阻止堆叠芯片太近地定位在一起，由此增加3D堆叠芯片的整体高度。而且，标准体积互连312的相隔高度未良好地适于用在高频信号应用中，其中期望硅层之间的减少的最小间隔。包括含有设置尺寸的填料颗粒的填料含量的底部填充材料被用于填充硅层之间的间隙。但是典型的底部填充材料的热导率值是0.3至0.5W/m-K，其差于硅的热导率值(149W/m-K)。从热的角度而言，也期望硅层之间的减少的最小间隔。
依照本发明的一个方面，提供体积减少的互连，其能够实现与标准3D芯片堆叠互连相比的若干重要益处，包括但不限于互连的减少的整体高度/尺寸、提高的功率效率、增加的带宽、和/或减少的成本。图4A至4E是描绘根据本发明的实施例的用于形成3D芯片堆叠的体积减少的互连的示例性工艺的至少一部分的剖视图。
参照图4A，模具402包括模具的上表面405中的多个洼部或腔404。在这一实施例中，腔404中的每个腔具有梯形截面，并且未完全延伸穿过模具402。腔404可以以与图3A所示和上面描述的腔304一致的方式来形成。虽然要理解的是本发明未限制腔404的形状和/或深度，但是模具402中的腔的体积被配置为与图3A所示的腔304相比更小。如将由本领域技术人员理解的，腔404优选与芯片或基板上的对应电接触位置对准，并且适于接收焊料或替代导电材料(其优选地例如经由注射模塑工艺等以熔融形式被引入到腔中)。(参见例如Ference等人的美国专利No.5,244,143，其描述了用于注射模塑焊料的装置和方法，其公开内容通过引用整体并入于此。)腔404中的每个腔的宽度和深度将限定对应互连结构中的每个互连结构的体积。
如图4B所示，模具402中的腔404中的每个腔填充有优选为熔融焊料的导电材料406。在示例性注射模塑工艺中，模具402被加热到等于或高于导电材料406的熔点的温度，并且熔融导电材料被迫进入腔404。然后注射板或相似机构被推进以在模具402的上表面405之上滑动，从而擦去模具的上表面上方的过量导电材料406，以由此使得腔404中的导电材料基本上与模具的上表面在同一平面上。
如图4C所示，一旦允许腔404中的熔融导电材料406固化，则模具402被反转并且被放置在对应工件408的上表面407上的UBM焊盘409之上。工件408可以是例如半导体芯片(多个半导体芯片可以形成3D芯片堆叠)、诸如例如硅之类的基板(例如半导体封装基板)、或者注射模塑的导电材料粘附到其上的伪基板(例如，形成载体基板的聚合物层)。在一个或多个实施例中，工件408是硅层。如图4D所示，固体导电结构410(例如固体焊料凸块)从模具402转移到工件408的上表面上的UBM焊盘409。在导电材料转移的工艺中，模具中的所有焊料再次熔融，并且被转移到硅晶片的UBM结构中，并且然后固化。不像在焊膏接合部中，从沉积到最后凸块没有体积改变。邻近导电结构410之间的间隔或节距被设置为规定距离A，以便与工件408上的对应电接触位置对准。虽然本发明不限于任何特定节距A，但是邻近导电结构410之间的间隔应该被选择为使得即使在后续工艺(例如润湿)之后，也不会发生电短路。在图4C所示的体积减少的互连结构的说明性情况下，UBM焊盘409的至少一个子集中的每个UBM焊盘409的宽度F显著大于腔404中的对应腔404的宽度(例如，约五倍或以上)。
在键合工艺之前，或者在键合工艺期间，转移的焊料可以例如在氮环境中回流，以使其径向散布，从而覆盖整个焊盘表面。相比于利用在键合工艺之前执行的回流的样本，如果在键合工艺期间执行焊料回流，金属间化合物的总厚度减少。
现在参照图4E，当在基本上竖直(Z轴)维度上堆叠在彼此之上时，对应工件(例如硅层)408上的导电结构将形成邻近工件之间的互连412。互连412具有与其相关联的相隔高度，其限定邻近硅层408之间的在本文中称为界面或芯片堆叠间隙的最小间隔D。
关于图4A所示的腔404的至少一个子集中的每个腔404的所选宽度，体积减少的互连结构(参见图4A)的腔宽度被大大地降低为节距A的约五分之一或更少(例如约200微米)，而图3A所示的模具302的标准腔宽度通常为节距A的二分之一。因此，得到的互连结构比对应硅层408下侧上的润湿焊盘409窄得多。在一个或多个实施例中，润湿区域直径C被配置为对应导电结构的直径的约两倍大。仅通过示例且非限制性的方式，导电结构410中的每个导电结构410的直径被选择为约40微米并且润湿区域直径C被选择为约100微米，但是本发明的实施例不限于这些具体尺寸。
作为当来自熔融导电材料(例如焊料)的热量使形成对应润湿焊盘的材料(例如铜)熔融由此形成将两种材料混合在一起的新合金时发生的润湿(或湿焊接)的结果，硅层408上的导电结构410将在润湿焊盘之上湿透，并且因而在竖直(z)维度上塌陷为非常小的相隔高度D。依赖于用于形成润湿焊盘的材料(例如铜)的类型，为了便于导电材料向润湿焊盘的润湿，根据一个或多个实施例，润湿焊盘首先经受诸如例如助熔手段(包括气体/蒸汽助熔或液体助熔)之类的氧化物还原环境。在其它一些实施例中，润湿焊盘可以由其抑制氧化物生长的诸如例如金之类的材料形成，在这种情况下，焊料润湿通过最小的氧化物还原来实现。这使得硅层408能够非常接近在一起，从而减少芯片堆叠的整体高度。
再次参照图4A和图4D，依照一个或多个实施例，腔404的至少一个子集中的每个腔404的深度与宽度的纵横比被选择为在约二分之一至三分之一之间。腔仍然在比腔尺寸大得多的节距中心上。因此这些腔适于保持与图3A中所描绘的腔304相比更小分数的导电材料406。当这些腔404被填充时(图4B)，这一体积减少的导电材料正好足以润湿每个对应硅焊盘的整个润湿区域。然而，这一焊料层的竖直高度显著小于标准焊料凸块的竖直高度。当移置在两个邻近硅层408之间时，这使得层以冶金方式键合在多个润湿焊盘之上，但是相比于标准互连方法通过层之间的最小间隔D实现。这在3D芯片堆叠中是高度有利的，以实现最小竖直占用(footprint)。而且，这一设置提供在硅层408之间的改善的热导率，这有助于热管理。而且，最小相隔高度产生有益于高频信号应用的改善的电特性。
图5A和图5B是概念性地描绘在UBM焊盘之上的分别使用单个中心预制体或多个间隔预制体的说明性焊料回流工艺的剖视图。参照图5A，芯片或其它工件502包括被配置为便于熔融导电材料在工件上表面上的流动的UBM焊盘504。在图5A的实施例中，使用基本上在焊盘504中心的单个预制体506。预制体506优选为例如依照已知工艺(其可以与本文中上面描述的焊料转移工艺一致)从模具(未明确示出但隐含的)转移的小体积的焊料预制体。如前所述，在键合工艺之前或者在键合工艺期间，使转移的焊料预制体506例如在氮或氢环境中回流，以使其径向散布，从而覆盖整个焊盘表面。在这一实施例中，氮环境在减少回流期间焊盘上氧化物的形成方面是有益的，但是其并不必然去除焊盘上的原生氧化物；如先前解释的，这可以通过使焊盘经受氧化物还原环境以去除原生氧化物来实现。
替代地，不是使用如图5A中描绘的单个中心预制体，如图5B所示，可以在焊盘504的上表面上形成多个间隔预制体508。参照图5B，预制体508优选为小体积的焊料预制体，预制体中的每个预制体的体积小于图5A所示的单个预制体506的体积。优选在用于防止在键合期间邻近预制体之间形成空隙的真空环境中，使预制体508回流，使得形成预制体的导电材料(例如焊料)径向散布以覆盖焊盘504的整个表面。特别是在多个小预制体的情况下，真空回流有益于防止回流期间的氧化物形成，但通常不会去除原生焊料氧化物；暴露于氧化物还原环境(例如助熔手段)可以用于去除原生氧化物。
图6A至6E是描绘根据本发明的实施例的用于形成包括体积减少的互连的3D芯片堆叠的示例性工艺的至少一部分的剖视图。参照图6A，模具602包括在模具的上表面605中的多个洼部或腔604。透视图603描绘模具602中的腔604的说明性设置。在这一实施例中，腔604中的每个腔604具有梯形截面，并且不会完全延伸穿过模具602，但是要理解的是，本发明不限制腔604的形状和/或深度。在一个或多个实施例中，可以以与图3A所示的腔304形成一致的方式，使用聚酰亚胺中的激光烧蚀来形成腔604。在一个或多个实施例中，模具602中的腔的体积被配置为与图3A所示的腔304相比更小。如将由本领域技术人员理解的，腔604优选与芯片或基板上的对应电接触位置对准，并且适于接收其优选例如经由注射模塑工艺等以熔融形式引入到腔中的焊料或替代导电材料。腔604中的每个腔604的宽度和深度将最终限定对应互连结构中的每个对应互连结构的体积。
模具602中的腔604中的每个腔604填充有诸如熔融焊料之类的导电材料。在示例性注射模塑工艺中，模具602被加热至等于或高于导电材料的熔点的温度，并且熔融导电材料被迫进入腔604。然后注射板或相似机构被推进以在模具602的上表面605之上滑动，从而擦去模具的上表面上方的过量导电材料，以由此使得腔604中的导电材料基本上与模具的上表面在同一平面上。
在图6B中，一旦允许腔604中的熔融导电材料固化，模具602被反转并且被放置在对应工件606的上表面上的UBM焊盘608或替代焊盘之上，UBM焊盘608或替代焊盘被配置为便于熔融导电材料的流动。工件606可以是例如半导体芯片(多个半导体芯片可以形成3D芯片堆叠)、诸如例如硅之类的基板(例如半导体封装基板)、或者注射模塑的导电材料粘附到其上的伪基板(例如，形成载体基板的聚合物层)。以此方式，固体导电结构610(例如固体焊料凸块)从模具602转移到焊盘608。
在一个或多个实施例中，相比于常规方法，可以形成具有更大直径的薄凸块。具体地，参照图6C，在其中工件606和导电结构610暴露于至少等于导电材料熔点的升高的温度的回流处理期间，形成多个导电结构610的导电材料变得熔融，并且在焊盘608的上表面之上流动在一起，以由此形成具有更大直径的薄凸块612。凸块612的直径G将与凸块形成在其上的焊盘的直径基本上相同。如前所述，为了便于在焊盘608的整个表面之上的基本上连续的润湿，在回流之前，焊盘首先经受氧化物还原环境(例如诸如蒸汽助熔剂、甲酸等之类的助熔手段)以去除其表面上的原生氧化物。
在一个或多个其它实施例中，相比于常规工艺，低体积导电结构610用于形成具有在硅芯片之间的减少的间隔的3D芯片堆叠。参照图6D，其像工件606那样具有形成在其表面上的UBM焊盘608的第二芯片或工件614被反转并且放置在工件的上表面上方。第二芯片614相对于工件606定位，使得每个芯片的焊盘608基本上彼此对准，并且导电结构610与两个焊盘都接触。
然后如图6E所示，执行真空键合工艺。在一个或多个实施例中，在其可以在真空回流炉/熔炉中执行的键合工艺期间，芯片606和614暴露于热量和/或接合压力。在一个或多个实施例中，在真空回流之前，焊盘608暴露于氧化物还原环境(例如甲酸蒸汽)以去除原生焊料氧化物。根据一个或多个实施例，甲酸蒸汽回流优选在无接合压力的情况下执行，其后为利用接合压力的真空回流。配置应用于芯片606、614的热量和/或压力的量，以便允许在焊盘608之间的导电结构610回流，并且接合形成焊盘608的材料，形成IMC层616，从而将芯片键合在一起。依赖于用于形成焊盘608和导电结构610的材料的类型，IMC层616可以包括不止一种类型的金属间化合物。仅通过示例且非限制性的方式，在一个或多个实施例中，UBM焊盘608包括铜(Cu)，并且导电结构610包括锡(Sn)或锡合金，从而导致基于锡和铜的IMC层616的形成。如图6E所示，IMC层616由至少两种不同类型的化合物构成；即，第一化合物618，其在这一实施例中包括Cu6Sn5，形成在IMC层的中心附近，以及第二化合物620，其在这一实施例中包括Cu3Sn，形成在IMC层和相应焊盘608之间的结附近。IMC层616中的第一和第二化合物618、620的厚度将至少部分地基于形成焊盘608和导电结构610的材料(例如锡和铜)的相应体积。在其中要求薄IMC层616并且焊料需要在键合工艺之后保留的一些情况下，阻挡金属(例如镍)形成在导电结构610和UBM焊盘608之间。导电结构610和阻挡金属之间的IMC以与导电结构和UBM焊盘608之间的IMC的形成相比慢得多的速率形成。
鉴于到目前为止的讨论，将理解的是，一般地说，根据本公开的一个方面，示例性方法包括以下步骤：形成多个导电结构，导电结构的至少一个子集中的每个导电结构具有针对导电结构被转移到其上的对应凸块下冶金(UBM)焊盘的导电材料的体积，该体积被配置为使得导电结构的未回流直径与对应焊盘的直径的比率为约三分之一比一或更小；将导电结构转移到硅层；在基本上竖直的维度上堆叠硅层，使得给定硅层上的导电结构中的每个导电结构与邻近硅层的下侧上的对应电接触位置对准；以及加热互连，以便以冶金方式键合邻近硅层的多个电接触位置，使得对应邻近硅层上的对准的电接触位置之间的导电结构中的至少给定导电结构塌陷以减少它们之间的互连间隙。
根据本公开的另一方面的示例性方法包括以下步骤：形成多个导电结构；将导电结构转移到硅层；在基本上竖直的维度上堆叠硅层，使得给定硅层上的导电结构中的每个导电结构与邻近硅层的下侧上的对应电接触位置对准；以及加热互连，以便以冶金方式键合邻近硅层的多个电接触位置，使得对应邻近硅层上的对准的电接触位置之间的导电结构中的至少给定导电结构塌陷以减少它们之间的互连间隙。导电结构的至少一个子集中的每个导电结构被形成为具有如下导电材料体积，该体积被配置为使得导电结构和形成在邻近硅层的对应相对表面上的对应对准凸块下冶金(UBM)焊盘之间的结中的金属间化合物的百分比为导电材料的总体积的约40％或更多。
根据本公开的一个方面，用于3D芯片堆叠的体积减少的电互连包括：具有形成在其表面上的多个电接触位置的多个硅层；多个UBM焊盘，UBM焊盘中的每个UBM焊盘形成在硅层中的对应硅层和电接触位置中的对应电接触位置之间；以及多个导电结构，导电结构中的每个导电结构与电接触位置中的对应电接触位置对准，并且具有针对UBM焊盘中的对应UBM焊盘的导电材料体积，该体积被配置为使得导电结构的未回流直径与对应焊盘的直径的比率为约三分之一比一或更小。互连被配置为使多个硅层在基本上竖直的维度上堆叠，使得给定硅层上的导电结构中的每个导电结构与邻近硅层的下侧上的对应电接触位置对准。当被加热至规定温度时，导电结构以冶金方式键合邻近硅层的电接触位置，使得对应邻近硅层上的对准的电接触位置之间的导电结构中的至少给定导电结构塌陷，从而减少它们之间的互连间隙。
根据本公开的另一方面，用于3D芯片堆叠的体积减少的电互连包括：具有形成在其表面上的多个电接触位置的多个硅层；多个UBM焊盘，UBM焊盘中的每个UBM焊盘形成在硅层中的对应硅层和电接触位置中的对应电接触位置之间；以及多个导电结构。导电结构中的每个导电结构与电接触位置中的对应电接触位置对准，并且具有针对UBM焊盘中的对应UBM焊盘的导电材料体积，该体积被配置为使得导电结构的未回流直径与对应焊盘的直径的比率为约三分之一比一或更小。导电结构的至少一个子集中的每个导电结构被形成为具有如下导电材料体积，该体积被配置为使得导电结构和形成在邻近硅层的对应相对表面上的对应对准的UBM焊盘之间的结中的金属间化合物的百分比为导电材料的总体积的约40％或更多。
本文中使用的术语仅用于描述特定实施例的目的，并且不旨在于限制本发明。如本文中使用的，单数形式“一”、“一个”和“该”旨在于也包括复数形式，除非上下文清楚地另外指示。将进一步理解的是，术语“包括”和/或“包含”当在本说明书中使用时指定所陈述的特征、整数、步骤、操作、元件和/或部件的存在，但不排除存在或添加一个或多个其它特征、整数、步骤、操作、元件、部件和/或它们的组。
如特别要求保护的，下面权利要求中的所有装置或步骤加功能元件的对应结构、材料、动作和等效物旨在于包括用于与其它要求保护的元件组合执行功能的任何结构、材料或动作。本发明的描述已经出于说明和描述的目的而给出，但并不旨在于是穷举式的或限于所公开形式的发明。对于本领域普通技术人员来说，许多修改和变化将是显而易见的，而不脱离本发明的范围和精神。选择和描述实施例，以最好地解释本发明的原理和实际应用，并且以使得本领域其它普通技术人员能够针对如适合于设想的特定使用的具有各种修改的各种实施例来理解本发明。

Claims (20)

1.一种形成用于包括多个硅层的芯片堆叠的体积减少的互连的方法，所述方法包括：
形成多个导电结构，所述导电结构的至少一个子集中的每个导电结构具有针对所述导电结构被转移到其上的对应凸块下冶金(UBM)焊盘的导电材料的体积，所述体积被配置为使得所述导电结构的未回流直径与对应的所述焊盘的直径的比率为约三分之一比一或更小；
将所述导电结构转移到所述硅层；
在基本上竖直的维度上堆叠所述硅层，使得给定硅层上的所述导电结构中的每个导电结构与邻近硅层的下侧上的对应电接触位置对准；以及
加热所述互连，以便以冶金方式键合邻近硅层的多个电接触位置，使得对应邻近硅层上的对准的电接触位置之间的所述导电结构中的至少给定导电结构塌陷以减少所述对应邻近硅层之间的互连间隙。
2.根据权利要求1所述的方法，其中将所述导电结构转移到所述硅层包括：
将所述导电结构中的每个导电结构与形成在所述硅层中的对应硅层上的所述对应UBM焊盘对准；以及
将所述导电结构中的每个导电结构转移到所述对应UBM焊盘。
3.根据权利要求2所述的方法，其中将所述导电结构转移到所述硅层包括将所述多个导电结构中的至少两个导电结构转移到单个对应UBM焊盘，形成所述至少两个导电结构的导电材料的合计体积基本上等于单个导电结构的体积，所述单个导电结构具有所述单个导电结构的未回流直径与对应的所述焊盘的直径的、为约三分之一比一或更小的比率。
4.根据权利要求1所述的方法，进一步包括：
提供模具，所述模具包括在所述模具的上表面中的多个腔，所述腔中的每个腔的宽度和深度限定对应互连结构中的每个对应互连结构的体积；
用熔融导电材料填充所述多个腔中的每个腔，使得所述熔融导电材料与所述模具的所述上表面基本上在同一平面上，所述多个腔中的每个腔中的所述熔融导电材料形成所述多个导电结构中的对应导电结构。
5.根据权利要求4所述的方法，其中所述多个腔的至少一个子集中的每个腔具有基本上梯形形状的并且从所述模具的所述上表面部分地延伸到所述模具中的截面。
6.根据权利要求1所述的方法，其中所述加热的步骤包括加热所述互连以便允许形成在邻近硅层的对应相对表面上的对应UBM焊盘之间的所述多个导电结构的至少一个子集回流，并且与形成所述UBM焊盘的材料结合，形成将所述邻近硅层键合在一起的金属间化合物(IMC)层。
7.根据权利要求1所述的方法，进一步包括在加热所述互连的同时应用压力，应用温度和压力的规定组合，以便允许形成在邻近硅层的对应相对表面上的对应UBM焊盘之间的所述多个导电结构回流，并且与形成所述UBM焊盘的材料结合，形成将所述邻近硅层键合在一起的金属间化合物(IMC)层。
8.根据权利要求1所述的方法，其中加热所述互连的所述步骤包括在氮环境中加热所述互连，以便允许形成在邻近硅层的对应相对表面上的对应UBM焊盘之间的所述多个导电结构的至少一个子集回流，由此形成所述多个导电结构的所述子集的导电材料径向散布以基本上覆盖所述对应UBM焊盘的上表面。
9.根据权利要求1所述的方法，其中加热所述互连的所述步骤在被配置为减少在多个对应电接触位置的键合期间空隙形成的可能性的真空环境中执行。
10.根据权利要求1所述的方法，其中所述互连的加热被执行为使得所述导电结构中的每个导电结构在所述导电结构和形成在所述硅层中的对应硅层的表面上的对应UBM焊盘之间的结中形成金属间化合物。
11.根据权利要求10所述的方法，其中所述互连的加热包括在键合邻近硅层的所述多个电接触位置的同时使所述导电结构回流，以减少形成在所述导电结构和对应UBM焊盘之间的相应结中的所述金属间化合物的厚度。
12.根据权利要求10所述的方法，其中所述互连的加热包括在键合邻近硅层的所述多个电接触位置之前使所述导电结构回流。
13.根据权利要求1所述的方法，其中形成所述导电结构的至少一个子集中的每个导电结构的导电材料的体积被配置为使得所述导电结构和对应对准的UBM焊盘之间的结中的金属间化合物的百分比为导电材料的总体积的约40％或更多。
14.根据权利要求1所述的方法，进一步包括将所述互连暴露于氧化物还原环境，以去除对应对准的UBM焊盘的表面上的原生氧化物的至少一部分，将所述互连暴露于所述氧化物还原环境的步骤在加热所述互连之前执行。
15.一种形成用于包括多个硅层的芯片堆叠的体积减少的互连的方法，所述方法包括：
形成多个导电结构；
将所述导电结构转移到所述硅层；
在基本上竖直的维度上堆叠所述硅层，使得给定硅层上的所述导电结构中的每个导电结构与邻近硅层的下侧上的对应电接触位置对准；
加热所述互连，以便以冶金方式键合邻近硅层的多个电接触位置，使得对应邻近硅层上的对准的电接触位置之间的所述导电结构中的至少给定导电结构塌陷以减少所述对应邻近硅层之间的互连间隙；
其中所述导电结构的至少一个子集中的每个导电结构被形成为具有如下导电材料的体积，所述体积被配置为使得所述导电结构和形成在邻近硅层的对应相对表面上的对应对准的凸块下冶金(UBM)焊盘之间的结中的金属间化合物的百分比为导电材料的总体积的约40％或更多。
16.一种用于芯片堆叠的体积减少的电互连，所述互连包括：
具有形成在其表面上的多个电接触位置的多个硅层；
多个凸块下冶金(UBM)焊盘，所述UBM焊盘中的每个UBM焊盘被形成在所述硅层中的对应硅层和所述电接触位置中的对应电接触位置之间；以及
多个导电结构，所述导电结构中的每个导电结构与所述电接触位置中的对应电接触位置对准，并且具有针对所述UBM焊盘中的对应UBM焊盘的导电材料的体积，所述体积被配置为使得所述导电结构的未回流直径与对应的所述焊盘的直径的比率为约三分之一比一或更小；
其中所述多个硅层在基本上竖直的维度上堆叠，使得给定硅层上的所述导电结构中的每个导电结构与邻近硅层的下侧上的对应电接触位置对准，所述导电结构当被加热至规定温度时以冶金方式键合邻近硅层的所述电接触位置，使得对应邻近硅层上的对准的电接触位置之间的所述导电结构中的至少给定导电结构塌陷，以由此减少所述对应邻近硅层之间的互连间隙。
17.根据权利要求16所述的电互连，其中所述UBM焊盘中的每个UBM焊盘由如下材料形成，所述材料当与所述多个导电结构中的对应导电结构键合时在所述导电结构和对应UBM焊盘之间的结中形成金属间化合物，所述导电结构中的所述金属间化合物增加所述导电结构的熔融温度，其减少当所述电互连经受后续工艺时所述导电结构的回流。
18.根据权利要求16所述的电互连，其中将所述多个导电结构中的至少两个导电结构转移到单个对应UBM焊盘，形成所述至少两个导电结构的导电材料的合计体积基本上等于单个导电结构的体积，所述单个导电结构具有所述单个导电结构的未回流直径与对应的所述焊盘的直径的、为约三分之一比一或更小的比率。
19.根据权利要求16所述的电互连，其中形成所述导电结构的至少一个子集中的每个导电结构的导电材料的体积被配置为使得所述导电结构和对应对准的UBM焊盘之间的结中的金属间化合物的百分比为导电材料的总体积的约40％或更多。
20.一种用于芯片堆叠的体积减少的电互连，所述互连包括：
具有形成在其表面上的多个电接触位置的多个硅层；
多个凸块下冶金(UBM)焊盘，所述UBM焊盘中的每个UBM焊盘被形成在所述硅层中的对应硅层和所述电接触位置中的对应电接触位置之间；以及
多个导电结构，所述导电结构中的每个导电结构与所述电接触位置中的对应电接触位置对准，并且具有针对所述UBM焊盘中的对应UBM焊盘的导电材料的体积，所述体积被配置为使得所述导电结构的未回流直径与对应的所述焊盘的直径的比率为约三分之一比一或更小；
其中所述导电结构的至少一个子集中的每个导电结构被形成为具有如下导电材料的体积，所述体积被配置为使得所述导电结构和形成在邻近硅层的对应相对表面上的对应对准的UBM焊盘之间的结中的金属间化合物的百分比为导电材料的总体积的约40％或更多。
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