CN114121926A - Nand封装架构的重叠管芯堆叠 - Google Patents
Nand封装架构的重叠管芯堆叠 Download PDFInfo
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- CN114121926A CN114121926A CN202110987696.1A CN202110987696A CN114121926A CN 114121926 A CN114121926 A CN 114121926A CN 202110987696 A CN202110987696 A CN 202110987696A CN 114121926 A CN114121926 A CN 114121926A
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Abstract
本申请涉及NAND封装架构的重叠管芯堆叠。一种半导体装置组件包含:衬底,其具有多个外部连接;半导体管芯的第一堆叠,其直接设置在所述衬底上的第一位置上方且电耦合到所述多个外部连接的第一子集;以及半导体管芯的第二堆叠,其直接设置在所述衬底上的第二位置上方且电耦合到所述多个外部连接的第二子集。所述第二堆叠中的所述半导体管芯的一部分与所述第一堆叠中的所述半导体管芯的一部分重叠。所述半导体装置组件进一步包含至少部分地包封所述衬底、所述第一堆叠以及所述第二堆叠的包封体。
Description
技术领域
本发明技术大体上涉及半导体封装,且更具体地涉及包含具有不对称高度的半导体管芯堆叠的半导体封装。
背景技术
包含存储器芯片、微处理器芯片以及成像器芯片的封装式半导体管芯通常包含安装在衬底上且封入塑料保护盖或由导热封盖覆盖的一或多个半导体管芯。管芯可包含有源电路(例如,提供如存储器单元、处理器电路和/或成像器装置的功能特征)和/或无源电路(例如,电容器、电阻器等)以及电连接到电路的接合衬垫。接合衬垫可电连接到保护盖外部的端子,以允许管芯连接到更高层级电路。
为了减小管芯所占据的体积,但增加所产生的包封组件的容量,管芯制造商面临着越来越大的压力。为了满足这些需求,管芯制造商常常将多个管芯彼此上下堆叠以在安装管芯的电路板或其它元件上的有限表面积内提高装置的容量或性能。
发明内容
本申请的一个方面涉及一种半导体组件,其包括:衬底,其包含外部连接;半导体管芯的第一堆叠,其直接设置在衬底上的第一位置上方且具有第一高度,且第一堆叠电耦合到外部连接的第一子集;半导体管芯的第二堆叠,其直接设置在衬底上的第二位置上方且具有与第一高度不同的第二高度,且第二堆叠电耦合到外部连接的第二子集;以及包封体,其至少部分地包封衬底、第一堆叠以及第二堆叠。
本申请的另一方面涉及一种制造半导体组件的方法,所述方法包括:提供衬底;以具有第一高度的第一堆叠形式将第一多个半导体管芯堆叠在衬底上;以具有与第一高度不同的第二高度的第二堆叠形式将第二多个半导体管芯堆叠在衬底上;在堆叠第一堆叠和第二堆叠之后将第一多个半导体管芯和第二多个半导体管芯引线接合到衬底;以及提供包封体以至少部分地包封衬底、第一堆叠以及第二堆叠。
本申请的又一方面涉及一种制造半导体组件的方法,所述方法包括:提供衬底;以第一堆叠形式将第一多个半导体管芯堆叠在衬底上;以第二堆叠形式将间隔物设置在衬底上;以第二堆叠形式将第二多个半导体管芯堆叠在间隔物上;在堆叠第一堆叠和第二堆叠之后将第一多个半导体管芯和第二多个半导体管芯引线接合到衬底;以及提供包封体以至少部分地包封衬底、第一堆叠以及第二堆叠。
附图说明
参考以下图式可以更好地理解本发明技术的许多方面。图式中的部件未必按比例绘制。实际上,重点是清楚地说明本发明技术的原理。
图1示出包含半导体管芯的叠瓦式堆叠的半导体装置组件。
图2示出包含半导体管芯的叠瓦式堆叠的半导体装置组件。
图3A是根据本发明技术的实施例的包含半导体管芯的重叠堆叠的半导体装置组件的简化横截面视图。
图3B是根据本发明技术的实施例的包含半导体管芯的重叠堆叠的另一半导体装置组件的简化横截面视图。
图3C是根据本发明技术的实施例的包含半导体管芯的重叠堆叠的另一半导体装置组件的简化横截面视图。
图4A是根据本发明技术的实施例的分别包含图3A的半导体管芯的重叠堆叠的半导体装置组件的简化横截面视图。
图4B是根据本发明技术的实施例的分别包含图3B的半导体管芯的重叠堆叠的半导体装置组件的简化横截面视图。
图4C是根据本发明技术的实施例的分别包含图3C的半导体管芯的重叠堆叠的半导体装置组件的简化横截面视图。
图5示出根据本发明技术的实施例的包含半导体管芯的重叠堆叠的半导体装置组件的简化平面图。
图6是包含根据本发明技术的实施例配置的半导体装置或封装的系统的示意图。
具体实施方式
下文描述半导体装置的若干实施例以及相关联系统和方法的具体细节。在一些实施例中,例如,根据本发明技术配置的半导体装置包含衬底、设置在第一位置上方的半导体管芯的第一堆叠以及设置在第二位置上方的半导体管芯的第二堆叠。第二堆叠中的一或多个最上部半导体管芯的一部分可与第一堆叠中的一或多个最上部半导体管芯的一部分叠置(例如,重叠)。第二堆叠可具有与第一堆叠的高度不同的高度。本文中所描述的重叠管芯堆叠可减小衬底上由管芯占据的表面积。本发明技术可提高装置的容量和/或性能。
相关领域的技术人员将认识到,除非上下文另有指示,否则可使用常规半导体制造技术来形成本文中所公开的结构。举例来说,可使用化学气相沉积、物理气相沉积、原子层沉积、电镀、无电式电镀、旋涂和/或其它合适的技术沉积材料。类似地,例如,可使用等离子蚀刻、湿式蚀刻、化学机械平坦化或其它合适的技术来移除材料。
本文中公开许多具体细节以提供本发明技术的实施例的详尽且有用的描述。然而,所属领域的技术人员将理解,所述技术可具有额外实施例,且所述技术可在没有下文参考图3A到6描述的实施例的细节中的若干个的情况下实践。举例来说,已省略所属领域中众所周知的半导体装置和/或封装的一些细节,以免使本发明技术模糊不清。一般来说,应理解,除了本文中所公开的那些具体实施例之外的各种其它装置和系统可在本发明技术的范围内。
如本文中所使用,术语“竖直”、“横向”、“上部”、“下部”、“之上”以及“之下”可以鉴于图中展示的定向而指代半导体装置中的特征的相对方向或位置。举例来说,“上部”或“最上部”可指比另一特征更接近页面顶部定位的特征。然而,这些术语应广泛地理解为包含具有其它定向的半导体装置,所述定向如倒置或倾斜定向,其中顶部/底部、上方/下方、之上/之下、向上/向下,以及左侧/右侧可取决于定向而互换。
如上文所论述,一种包含额外半导体管芯的途径涉及将管芯堆叠在衬底上方。为了促进管芯与衬底的电连接,可将管芯布置成叠瓦式堆叠,其中每个管芯与下方的管芯水平地偏移以留下管芯的可(例如,使用焊线)接合到衬底上的对应接合衬垫的暴露接触衬垫。这种叠瓦式堆叠途径的缺点是对可以这种方式堆叠的管芯的数量的限制,这是由于添加到堆叠的每个额外管芯的悬垂量增加。
为了解决这种限制,管芯的叠瓦式堆叠可包含以叠瓦式方式布置的多组管芯以及在相同方向(例如,如图1中所展示)上或相反方向(如图2中所展示)上的偏移。在此方面,图1示出衬底101上的管芯的叠瓦式堆叠110分别包含各自具有单独管芯104的第一管芯组102和第二管芯组103的半导体装置组件100,所述第一管芯组102和第二管芯组103在相同偏移方向上叠瓦堆叠且通过焊线121电连接到衬底101上的接合衬垫120。第一管芯组102的焊线121位于第二管芯组103的悬垂区111下方,且因此下部焊线121在第二管芯组103中的管芯104堆叠在第一管芯组102上方之前形成。此外,第二管芯组103中的最底部管芯104以充足的距离(例如,由较厚的管芯贴合材料105的层提供)在第一管芯组102中的最顶部管芯104之上间隔开,以形成贴合到第一管芯组102中的最顶部管芯104的焊线121。这种布置的缺点包含需要必须反复执行的多个堆叠和引线接合操作并且在第一管芯组102与第二管芯组103之间需要不同的管芯贴合材料厚度,这增加了制造成本和复杂性。
图2示出具有衬底201上的管芯的分别包含第一管芯组202和第二管芯组203的叠瓦式堆叠210的半导体装置组件200,所述第一管芯组202和第二管芯组203各自包含单独管芯204,在相反偏移方向上叠瓦堆叠且通过焊线221电连接到衬底201上的接合衬垫220。在这种配置中,第一管芯组202的焊线221中的至少一些位于第二管芯组203的悬垂区211下方,且因此下部焊线221在第二管芯组203中的管芯204堆叠在第一管芯组202上方之前形成。这种布置的缺点包含需要必须反复执行的多个堆叠和引线接合操作并且需要衬底中的额外接合衬垫和迹线,这预计会增加制造成本和复杂性。
图3A是根据本发明技术的实施例的包含半导体管芯的重叠堆叠的半导体装置组件(“组件300”)的简化横截面视图。组件300包含衬底301、半导体管芯304(“管芯304”)的第一堆叠302、管芯304的第二堆叠303以及至少部分包住第一堆叠302和第二堆叠303的包封体330。第一堆叠302和第二堆叠303中的每一个可包含八个管芯304。在其它实施例中,第一堆叠302和第二堆叠303中的每一个可包含两个、四个、六个、十个、十二个或任何其它合适数量的管芯304。在其它实施例中,第一堆叠302中的管芯304的数量可与第二堆叠303中的管芯304的数量不同。
每个堆叠302和303中的最底部(例如,最下部)管芯304c和304d分别直接电耦合到衬底301,且每个堆叠302和303中除最底部管芯304c和304d以外的每个管芯304以橫向偏移距离与紧邻的管芯304横向偏移。在一些实施例中,从一个管芯到下一个管芯的偏移距离在整个分离的堆叠302和303中至少大体上相同。在其它实施例中,偏移距离可改变。第一堆叠302中的每个管芯304的偏移方向与第二堆叠303中的每个管芯304的偏移方向相反。
组件300进一步包含将每个堆叠302和303中的管芯304彼此电连接和/或电连接到衬底301的焊线321。更具体地,每个堆叠302和303中的每个管芯304直接或间接电耦合到衬底301上的一或多个接合衬垫320,且接合衬垫320通过通孔322和/或衬底301中的其它电路系统电耦合到组件300的对应外部触点,如焊球323。在此方面,因为堆叠302和303中的管芯304中没有一个位于另一管芯304(例如,不同于图1和2中)的悬垂部下方,所以用于堆叠中的所有管芯的焊线321可在(例如,未经另一堆叠操作间断的)单个操作中形成,且每个接合衬垫320可仅连接到单条焊线321(例如,不同于图1中)。
组件300包含配置成提高组件的容量或性能的重叠管芯堆叠302和303。如上文所论述,元件(例如,衬底)上的安装管芯的表面积可为有限的。因此,堆叠302和303的叠置(例如,重叠)部分可减小衬底301上由堆叠302和303占据的表面积的量。因此,较高密度的管芯304可安装在衬底301上。在所说明的实施例中,例如,第二堆叠303包含与第一堆叠302的高度不同的高度(例如,堆叠302和303具有不对称高度)。第二堆叠303比第一堆叠302更高。第二堆叠303的一部分可叠置在第一堆叠302的一部分之上(例如,与第一堆叠302的一部分重叠)。举例来说,第二堆叠303中的最上部管芯304a的一部分以重叠距离“d”叠置在第一堆叠302中的最上部管芯304b的一部分之上(例如,与第一堆叠302中的最上部管芯304b的一部分重叠)。较大重叠距离d可克服对衬底301上的安装管芯304的表面积空间的限制。
与不具有任何重叠的管芯堆叠相比,重叠管芯堆叠可减小安装在元件(例如,衬底)上的管芯所占据的表面积。如参考图3A可看出,第二堆叠303中的一个管芯304a与第一堆叠302中的一个管芯304b重叠。与每个堆叠中的一个管芯重叠可节约大约270微米。举例来说,重叠距离d约为270微米。在其它实施例中,第二堆叠303中的两个管芯304可与第一堆叠302中的一或多个管芯304重叠,这可节约大约540微米。增加第二堆叠303的总高度可允许第二堆叠303中的更多管芯304与第一堆叠302中的一或多个管芯304重叠。另外,增加第二堆叠303的总高度可允许较大重叠距离d。
可以多种不同方式配置具有不对称高度的重叠管芯堆叠302和303。在所说明的实施例中,组件300进一步包含间隔物340(例如,介电间隔物、控制器管芯、逻辑管芯、存储器管芯或任何其它合适的结构)。间隔物340可设置在第二堆叠303内的任何合适位置处。举例来说,间隔物340设置在第二堆叠303中的最底部管芯304d下方。在其它实施例中,间隔物340可设置在第二堆叠303中的任何合适管芯304之间。间隔物340可具有任何合适高度。举例来说,间隔物340可具有约5、10、20、30、40、50、60、70、80、90或100微米的高度。在一些实施例中,间隔物340可具有不超过5、10、20、30、40、50、60、70、80、90或100微米的高度。在一些实施例中,间隔物340可具有至少5、10、20、30、40、50、60、70、80、90或100微米的高度。
每个管芯304通过管芯贴合膜344与相邻管芯304、衬底301或间隔物340间隔开。举例来说,第二堆叠303中的最底部管芯304d通过管芯贴合膜344与间隔物340间隔开。第一堆叠302中的每个管芯304和第二堆叠303中的每个管芯304分别包含第一管芯厚度T1和第二管芯厚度T2。第一管芯厚度T1和第二管芯厚度T2可至少大约为相等的。第一堆叠302中的每个管芯贴合膜344和第二堆叠303中的每个管芯贴合膜344分别包含第一管芯贴合膜厚度T3和第二管芯贴合膜厚度T4。第一管芯贴合膜厚度T3和第二管芯贴合膜厚度T4可至少大约为相等的。
可以多种不同方式制造组件300。在一些实施例中,例如,通过提供衬底301,将间隔物340设置在衬底301上的第二位置处,将管芯304堆叠在衬底301上以形成第一堆叠302并且将管芯304堆叠在衬底301上的间隔物340上方以形成第二堆叠303来制造组件300。在此方面,第一堆叠302中的管芯304可直接堆叠在衬底301上的第一位置上方,且第二堆叠303中的管芯304可直接堆叠在衬底301上的第二位置处的间隔物340上方。第一堆叠302和第二堆叠303中的管芯304引线接合到衬底301,这可在堆叠第一堆叠302和第二堆叠303之后执行。可在未经任何堆叠间断的单个操作中执行引线接合。管芯304的堆叠302和303接着可受到包封体330保护。
图3B和3C示出具有根据本发明技术的实施例配置的重叠管芯堆叠的各种实例的半导体组件。图3B和3C中所展示的组件可与相对于图3A所描述的组件300大体上类似。因此,相同数字用于标识类似或相同部件,并且对图3B和3C中所展示的组件的论述将限于不同于图3A的组件300的那些特征。
图3B示出根据本发明技术的实施例的包含半导体管芯的重叠堆叠的半导体装置组件300b(“组件300b”)。除了第二堆叠303b中的一或多个管芯304e的厚度T5与第一堆叠302中的管芯304的厚度T1不同之外,半导体管芯304e(“管芯304e”)的第二堆叠303b与图3A的第二堆叠303大体上类似。第二堆叠303b中的任何合适数量的管芯304e可具有与厚度T1不同的厚度T5。在所说明的实施例中,例如,所有管芯304e具有与厚度T1不同的厚度T5。举例来说,厚度T5可大于厚度T1的100%。在一些实施例中,厚度T5可为厚度T1的约110%、120%、130%、140%、150%、160%、170%、180%、190%、200%或300%。在一些实施例中,厚度T5可大于厚度T1的110%、120%、130%、140%、150%、160%、170%、180%、190%、200%或300%。在一些实施例中,第二堆叠303b内的每个管芯304e的厚度T5可约等于彼此。在其它实施例中,第二堆叠303b内的每个管芯304e的厚度T5可改变。
在其它实施例中,并非所有管芯304e都可具有与厚度T1不同的厚度T5。举例来说,第二堆叠303b包含八个管芯304e,且一个、两个、三个、四个、五个、六个或七个管芯304e可具有与厚度T1不同的厚度T5。举例来说,除最底部管芯以外的管芯304e可具有约等于厚度T1的厚度T5,且最底部管芯304e可具有大于厚度T5和厚度T1的厚度。在另一实例中,除两个最底部管芯以外的半导体管芯304e可具有约等于厚度T1的厚度T5,且第二堆叠303b中的两个最底部管芯304e可具有大于厚度T5和厚度T1的厚度。举例来说,最底部管芯304e和/或两个最底部管芯304e的厚度可为厚度T1的约110%、120%、130%、140%、150%、160%、170%、180%、190%、200%或300%。在一些实施例中,最底部管芯304e和/或两个最底部管芯304e的厚度可大于厚度T1的110%、120%、130%、140%、150%、160%、170%、180%、190%、200%或300%。
可以多种不同方式制造组件300b。在一些实施例中,例如,通过提供衬底301,以第一堆叠302形式将管芯304堆叠在衬底301上并且以第二堆叠303b形式将管芯304e堆叠在衬底301上来制造组件300b。在此方面,第一堆叠302中的管芯304可直接堆叠在衬底301上的第一位置上方,且第二堆叠303b中的管芯304e可直接堆叠在衬底301上的第二位置处。第一堆叠302和第二堆叠303b中的管芯304和304e分别引线接合到衬底301,这可在堆叠第一堆叠302和第二堆叠303b之后执行。可在未经任何堆叠间断的单个操作中执行引线接合。堆叠302和303b接着受到包封体330保护。
图3C示出根据本发明技术的实施例的包含半导体管芯的重叠堆叠的半导体装置组件300c(“组件300c”)。除了第二堆叠303c中的管芯贴合膜344c具有与第一堆叠302中的管芯贴合膜344的厚度T3不同的厚度T6之外,管芯304或304e的第二堆叠303c与图3A的第二堆叠303或图3B的第二堆叠303b大体上类似。第二堆叠303c的任何合适数量的管芯贴合膜344c可具有与厚度T3不同的厚度T6。在所说明的实施例中,例如,每个管芯贴合膜344c具有与厚度T3不同的厚度T6。举例来说,厚度T6可大于厚度T3的100%。在一些实施例中,厚度T6可为厚度T3的约110%、120%、130%、140%、150%、160%、170%、180%、190%、200%或300%。在一些实施例中,厚度T6可大于厚度T3的110%、120%、130%、140%、150%、160%、170%、180%、190%、200%或300%。在一些实施例中,第二堆叠303c内的每个管芯贴合膜344c的厚度T6可约为相等的。在其它实施例中,第二堆叠303c内的每个管芯贴合膜344c的厚度T6可改变。
在其它实施例中,并非所有管芯贴合膜344c可具有与厚度T3不同的厚度T6。举例来说,第二堆叠303c包含八个管芯贴合膜344c,且一个、两个、三个、四个、五个、六个或七个管芯贴合膜344c可具有与厚度T3不同的厚度T6。举例来说,除最底部管芯贴合膜以外的管芯贴合膜344c可具有约等于厚度T3的厚度T6,且最底部管芯贴合膜344c可具有大于厚度T6和厚度T3的厚度。在另一实例中,除两个最底部管芯贴合膜344c以外的管芯贴合膜344c可具有约等于厚度T3的厚度T6,且两个最底部管芯贴合膜344c可具有大于厚度T6和厚度T3的厚度。举例来说,最底部管芯贴合膜344c和/或两个最底部管芯贴合膜344c的厚度可为厚度T3的约110%、120%、130%、140%、150%、160%、170%、180%、190%、200%或300%。在一些实施例中,最底部管芯贴合膜344c和/或两个最底部管芯贴合膜344c的厚度可大于厚度T3的110%、120%、130%、140%、150%、160%、170%、180%、190%、200%或300%。
可以多种不同方式制造组件300c。在一些实施例中,例如,通过提供衬底301,在将管芯贴合膜344设置在第一堆叠302中的相邻管芯304和/或衬底301之间的同时以第一堆叠302形式将管芯304堆叠在衬底301上并且在将较厚管芯贴合膜344c设置在第二堆叠303c中的相邻管芯304、304e和/或衬底301之间的同时以第二堆叠303c形式将管芯304、304e堆叠在衬底301上来制造组件300c。在此方面,第一堆叠302中的管芯304可直接堆叠在衬底301上的第一位置上方,且第二堆叠303c中的管芯304、304e可直接堆叠在衬底301上的第二位置处。第一堆叠302和第二堆叠303c中的管芯304、304e分别引线接合到衬底301,这可在堆叠第一堆叠302和第二堆叠303c之后执行。可在未经任何堆叠间断的单个操作中执行引线接合。堆叠302和303c接着受到包封体330保护。
图4A到4C示出根据本发明技术的实施例的分别包含图3A到3C的半导体管芯的重叠堆叠的各种半导体装置组件400、400b以及400c(“组件400、400b以及400c”)。根据本发明技术的一个方面,在半导体装置组件中包含半导体管芯的重叠堆叠的另一优点是在组件的布局中为要包含的额外装置硬件提供的额外灵活性。组件的布局提供第一堆叠302中的最底部半导体管芯与第二堆叠303、303b或303c中的最底部半导体管芯之间的距离。距离可以在30到150微米的范围内。举例来说,距离可以在50到100微米的范围内。在另一实例中,距离可为约30、40、50、60、70、80、90、100、110、120、130、140或150微米。在一些实施例中,距离可大于30、40、50、60、70、80、90、100、110、120、130、140或150微米。在一些实施例中,距离可不超过30、40、50、60、70、80、90、100、110、120、130、140或150微米。
如参考图4A可看出,例如,组件400包含控制器管芯410,所述控制器管芯410可适宜地位于衬底401上的第一堆叠302与第二堆叠303之间。控制器管芯410可经由焊线421电耦合到衬底401。在另一实例中,如在图4B中,组件400b包含控制器管芯410,所述控制器管芯410可适宜地位于第一堆叠302与第二堆叠303b之间。在另一实例中,如在图4C中,组件400c包含控制器管芯410,所述控制器管芯410可适宜地位于第一堆叠302与第二堆叠303c之间。在一些实施例中,其他合适的装置硬件可设置在第一堆叠302与第二堆叠303、303b或303c之间。
图5示出根据本发明技术的实施例的包含半导体管芯的重叠堆叠的半导体装置组件500(“组件500”)的简化平面图。组件500包含衬底501、半导体管芯504(“管芯504”)的第一堆叠502以及管芯504的第二堆叠503。第一堆叠502设置在衬底501上的第一位置中,且第二堆叠503设置在与第一位置偏移的第二位置中。第二堆叠503的一部分在重叠区域“OZ”中与第一堆叠502的一部分重叠。第一堆叠502和第二堆叠503中的每一个包含四个管芯504。在其它实施例中,第一堆叠502和第二堆叠503中的每一个可包含六个、八个或任何其它合适数量的管芯504。在其它实施例中,第一堆叠502中的管芯504的数量可与第二堆叠503中的管芯504的数量不同。每个堆叠502和503中的最底部管芯直接耦合到衬底501,且每个堆叠502和503中的除最底部管芯以外的每个管芯504与紧邻的管芯504横向偏移。第一堆叠502中的每个管芯504的偏移方向与第二堆叠503中的每个管芯504的偏移方向相反。偏移距离在整个堆叠中可约为相等的或可在堆叠内改变。
组件500进一步包含将每个堆叠502和503中的每个管芯504彼此电耦合和/或直接或间接电耦合到衬底501的焊线521。更具体地,焊线521将每个堆叠502和503中的管芯504电耦合到衬底501上的对应接合衬垫520。因为堆叠502和503中的管芯504的边缘部分位于另一管芯504的悬垂部下方(例如,不同于图1和2中),所以可在单个操作(例如,未经另一堆叠操作间断)中形成焊线521,且每个接合衬垫520可仅连接到单条焊线521。
如上文所阐述的,半导体装置组件中的半导体管芯可包含提供多种不同功能(例如,逻辑、存储器、传感器等)的管芯。在存储器管芯的重叠堆叠被包含于半导体装置组件中的实施例中,包含存储器管芯的多个堆叠的预期优点在于存储器管芯的不同堆叠可专用于不同存储器信道(例如,以每个堆叠对应于一个信道的一对一关系或以多个堆叠对应于每个信道或甚至多个信道对应于每个堆叠的n对一或一对n关系)。
根据本发明技术的一个方面,在半导体装置组件中提供管芯的重叠堆叠的另一预期优点在于可减小封装高度,这是由于在相同总数的管芯的情况下可使用每堆叠较少管芯的多个堆叠,代替单个较高堆叠。另一预期优点在于与具有相同数量的总管芯的单个管芯堆叠相比,可在两个管芯堆叠中使用较厚半导体管芯,这是由于对于根据本发明技术的装置,总高度较小。预计这将简化制造,这是因为较厚管芯比极薄管芯更容易处置和加工。
根据本发明技术的一个方面,相较于单个较大堆叠,半导体装置组件中的半导体管芯的重叠堆叠的额外预期优点在于组件的翘曲减少。预计这将减小组件的外部触点上的物理应力。在此方面,管芯的单个堆叠大体上设置在组件中间的组件在大体上位于堆叠的外围下方和堆叠的外围内的区中经历升高的物理应力(例如,由于翘曲和热效应)。这种区域大体上对应于封装衬底的大多数组装焊接点可专用于发信和供电的中心区。此类应力可降低组件与较高层级电路系统(例如,模块板、叠层封装插入件或类似者)之间的焊接点的可靠性。在管芯的重叠堆叠设置在组件的衬底上的不同位置中的组件中,组件中间的物理应力往往较低,其中在封装的更外围区中(例如,在所述外围区中,封装触点可能仅专用于机械稳固性并且组件的成功操作不需要电连接性)出现升高的应力(如果有的话)。
本发明技术的又一预期优点在于在相同数量的总管芯的情况下,半导体管芯的多个重叠堆叠的热阻抗预计会低于单个堆叠的热阻抗。具有更少管芯(例如,具有更少管芯到管芯接口)的堆叠的热阻抗低于具有更多管芯的堆叠,即使对于具有较厚管芯的堆叠也是如此,这是由于在重叠管芯堆叠中存在更少的由硅与底部填充剂、胶带贴合或其它粘合剂的交替层所导致的热障。因此,在热阻抗提高的情况下,与具有更多半导体管芯的单个堆叠的半导体装置组件相比,具有半导体管芯的重叠堆叠的半导体装置组件可在可接受的温度范围内执行的同时用更大的输入电源操作。
尽管在前述实例中,已经将半导体装置组件示出并描述为包含半导体管芯的堆叠,但在本发明技术的其它实施例中,半导体装置组件可包含利用不同拓扑(例如,竖直堆叠等)和互连技术(例如,TSV、光学互连、电感互连等)的半导体管芯的多个堆叠。
上文参考图3A到5所描述的半导体装置组件中的任一个可并入到大量更大和/或更复杂的系统中的任一个中,所述系统的代表性实例是图6中示意性地展示的系统600。系统600可包含半导体装置组件602、电源604、驱动器606、处理器608和/或其它子系统或部件610。半导体装置组件602可包含与上文参考图3A到5所描述的半导体装置的特征大体上类似的特征。所产生的系统600可执行各种功能中的任一种,如存储器存储、数据处理和/或其它合适的功能。因此,代表性系统600可包含但不限于手持式装置(例如,移动电话、平板计算机、数字阅读器和数字音频播放器)、计算机、车辆、电器和其它产品。系统600的部件可容纳于单个单元中或分布在多个互连的单元上方(例如,通过通信网络)。系统600的部件还可包含远程装置和各种计算机可读介质中的任一种。
从前述内容中应理解,出于说明的目的,本文中已经描述了本技术的具体实施例,但是可以在不偏离本公开的情况下进行各种修改。因此,本发明不受所附权利要求书之外的限制。此外,在特定实施例的上下文中所描述的新技术的某些方面还可在其它实施例中组合或去除。此外,尽管已在那些实施例的上下文中描述了与新技术的某些实施例相关联的优点,但其它实施例也可展现此类优点,并且并非所有实施例都必须展现此类优点以落入本技术的范围内。因此,本公开和相关联的技术可涵盖未明确地在本文中展示或描述的其它实施例。
Claims (21)
1.一种半导体组件,其包括:
衬底,其包含外部连接;
半导体管芯的第一堆叠,其直接设置在所述衬底上的第一位置上方且具有第一高度,且所述第一堆叠电耦合到所述外部连接的第一子集;
半导体管芯的第二堆叠,其直接设置在所述衬底上的第二位置上方且具有与所述第一高度不同的第二高度,且所述第二堆叠电耦合到所述外部连接的第二子集;以及
包封体,其至少部分地包封所述衬底、所述第一堆叠以及所述第二堆叠。
2.根据权利要求1所述的半导体组件,其中:
所述第一堆叠包含所述第一堆叠中的最上部半导体管芯;
所述第二堆叠包含所述第二堆叠中的最上部半导体管芯;以及
所述第二堆叠中的所述最上部半导体管芯的至少一部分叠置在所述第一堆叠中的所述最上部半导体管芯的至少一部分之上。
3.根据权利要求1所述的半导体组件,其进一步包括设置在所述第一堆叠或所述第二堆叠中的最下部半导体管芯下方的间隔物。
4.根据权利要求3所述的半导体组件,其中所述间隔物是介电间隔物。
5.根据权利要求3所述的半导体组件,其中所述间隔物是控制器管芯或逻辑管芯。
6.根据权利要求1所述的半导体组件,其中:
所述第一堆叠中的每个半导体管芯包含第一管芯厚度;以及
所述第二堆叠中的每个半导体管芯包含与所述第一管芯厚度不同的第二管芯厚度。
7.根据权利要求1所述的半导体组件,其进一步包括:
第一管芯贴合膜,其设置在所述第一堆叠中的每个半导体管芯之间且具有第一管芯贴合膜厚度;以及
第二管芯贴合膜,其设置在所述第二堆叠中的每个半导体管芯之间且具有与所述第一管芯贴合膜厚度不同的第二管芯贴合膜厚度。
8.根据权利要求1所述的半导体组件,其进一步包括设置在所述衬底上所述第一堆叠与所述第二堆叠之间的控制器管芯。
9.根据权利要求1所述的半导体组件,其中所述第一堆叠和所述第二堆叠包含相同数量的半导体管芯。
10.根据权利要求1所述的半导体组件,其中:
所述第一堆叠包含所述第一堆叠中的最下部半导体管芯和堆叠在所述第一堆叠中的所述最下部半导体管芯上方的至少一个上部半导体管芯;以及
所述第一堆叠中的每个上部半导体管芯在第一方向上以第一偏移与直接位于下方的半导体管芯偏移。
11.根据权利要求10所述的半导体组件,其中:
所述第二堆叠包含所述第二堆叠中的最下部半导体管芯和堆叠在所述第二堆叠中的所述最下部半导体管芯上方的至少一个上部半导体管芯;以及
所述第二堆叠中的每个上部半导体管芯在第二方向上以第二偏移与直接位于下方的半导体管芯偏移。
12.根据权利要求11所述的半导体组件,其中所述第一偏移基本上等于所述第二偏移。
13.根据权利要求11所述的半导体组件,其中所述第一方向基本上与所述第二方向相反。
14.根据权利要求1所述的半导体组件,其中:
半导体管芯的所述第一堆叠通过第一多条焊线电连接到所述外部连接的所述第一子集;以及
半导体管芯的所述第二堆叠通过第二多条焊线电连接到所述外部连接的所述第二子集。
15.根据权利要求14所述的半导体组件,其中:
所述衬底包含对应于所述第一堆叠的第一多个接合衬垫和对应于所述第二堆叠的第二多个接合衬垫;
所述第一多个接合衬垫中的每一个直接耦合到所述第一多条焊线中的仅一条;以及
所述第二多个接合衬垫中的每一个直接耦合到所述第二多条焊线中的仅一条。
16.根据权利要求1所述的半导体组件,其中所述第一堆叠中的最下部半导体管芯与所述第二堆叠的最下部半导体管芯之间的距离在50到100微米的范围内。
17.一种制造半导体组件的方法,所述方法包括:
提供衬底;
以具有第一高度的第一堆叠形式将第一多个半导体管芯堆叠在所述衬底上;
以具有与所述第一高度不同的第二高度的第二堆叠形式将第二多个半导体管芯堆叠在所述衬底上;
在堆叠所述第一堆叠和所述第二堆叠之后将所述第一多个半导体管芯和所述第二多个半导体管芯引线接合到所述衬底;以及
提供包封体以至少部分地包封所述衬底、所述第一堆叠以及所述第二堆叠。
18.根据权利要求17所述的方法,其中在未经任何堆叠中断的单个操作中执行所述引线接合。
19.根据权利要求18所述的方法,其中:
所述第一多个半导体管芯直接堆叠在所述衬底上的第一位置上方;以及
所述第二多个半导体管芯直接堆叠在所述衬底上的第二位置上方。
20.根据权利要求19所述的方法,其进一步包括将间隔物设置在所述衬底上的所述第二位置处。
21.一种制造半导体组件的方法,所述方法包括:
提供衬底;
以第一堆叠形式将第一多个半导体管芯堆叠在所述衬底上;
以第二堆叠形式将间隔物设置在所述衬底上;
以所述第二堆叠形式将第二多个半导体管芯堆叠在所述间隔物上;
在堆叠所述第一堆叠和所述第二堆叠之后将所述第一多个半导体管芯和所述第二多个半导体管芯引线接合到所述衬底;以及
提供包封体以至少部分地包封所述衬底、所述第一堆叠以及所述第二堆叠。
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US11488944B2 (en) * | 2021-01-25 | 2022-11-01 | Google Llc | Integrated circuit package for high bandwidth memory |
US11942430B2 (en) * | 2021-07-12 | 2024-03-26 | Micron Technology, Inc. | Stacked die modules for semiconductor device assemblies and methods of manufacturing stacked die modules |
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US7253511B2 (en) * | 2004-07-13 | 2007-08-07 | Chippac, Inc. | Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package |
US7687921B2 (en) * | 2008-05-05 | 2010-03-30 | Super Talent Electronics, Inc. | High density memory device manufacturing using isolated step pads |
US9735082B2 (en) * | 2013-12-04 | 2017-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC packaging with hot spot thermal management features |
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US10217719B2 (en) * | 2017-04-06 | 2019-02-26 | Micron Technology, Inc. | Semiconductor device assemblies with molded support substrates |
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US10312219B2 (en) * | 2017-11-08 | 2019-06-04 | Micron Technology, Inc. | Semiconductor device assemblies including multiple shingled stacks of semiconductor dies |
US10475771B2 (en) * | 2018-01-24 | 2019-11-12 | Micron Technology, Inc. | Semiconductor device with an electrically-coupled protection mechanism and associated systems, devices, and methods |
JP2020035957A (ja) | 2018-08-31 | 2020-03-05 | キオクシア株式会社 | 半導体装置 |
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