CN114088208A

CN114088208A - Infrared detector based on CMOS (complementary Metal oxide semiconductor) process and preparation method thereof

Info

Publication number: CN114088208A
Application number: CN202110324039.9A
Authority: CN
Inventors: 翟光杰; 武佩; 潘辉; 翟光强
Original assignee: Beijing North Gaoye Technology Co ltd
Current assignee: Beijing North Gaoye Technology Co ltd
Priority date: 2021-03-26
Filing date: 2021-03-26
Publication date: 2022-02-25
Anticipated expiration: 2041-03-26
Also published as: CN114088208B

Abstract

The utility model relates to an infrared detector based on CMOS technology and a preparation method thereof, the infrared detector comprises a CMOS measuring circuit system and a CMOS infrared sensing structure positioned on the CMOS measuring circuit system, and the CMOS measuring circuit system and the CMOS infrared sensing structure are both prepared by the CMOS technology; the absorption plate and the beam structure both comprise a heat-sensitive layer, and the material for forming the heat-sensitive layer comprises at least one of amorphous silicon, amorphous carbon, amorphous germanium or amorphous silicon germanium; the infrared detector pixel still includes reinforced structure, and reinforced structure corresponds the setting of second columnar structure place position, and reinforced structure is used for strengthening the connection steadiness between second columnar structure and the beam structure. Through the technical scheme, the problems of low performance, low pixel scale, low yield and the like of the traditional MEMS process infrared detector are solved, and the structural stability of the infrared detector pixel is enhanced.

Description

Infrared detector based on CMOS (complementary Metal oxide semiconductor) process and preparation method thereof

Technical Field

The disclosure relates to the technical field of infrared detection, in particular to an infrared detector based on a CMOS (complementary metal oxide semiconductor) process and a preparation method thereof.

Background

The fields of monitoring markets, vehicle and auxiliary markets, home markets, intelligent manufacturing markets, mobile phone applications and the like have strong demands on uncooled high-performance chips, certain requirements are provided for the performance of the chips, the performance consistency and the product price, the potential demands of more than one hundred million chips are expected every year, and the current process scheme and architecture cannot meet the market demands.

At present, an infrared detector adopts a mode of combining a measuring circuit and an infrared sensing structure, the measuring circuit is prepared by adopting a Complementary Metal-Oxide-Semiconductor (CMOS) process, and the infrared sensing structure is prepared by adopting a Micro-Electro-Mechanical System (MEMS) process, so that the following problems are caused:

(1) the infrared sensing structure is prepared by adopting an MEMS (micro-electromechanical systems) process, polyimide is used as a sacrificial layer, and the infrared sensing structure is incompatible with a CMOS (complementary metal oxide semiconductor) process.

(2) Polyimide is used as a sacrificial layer, so that the problem that the vacuum degree of a detector chip is influenced due to incomplete release exists, the growth temperature of a subsequent film is limited, and the selection of materials is not facilitated.

(3) Polyimide can cause the height of the resonant cavity to be inconsistent, and the working dominant wavelength is difficult to guarantee.

(4) The control of the MEMS process is far worse than that of the CMOS process, and the performance consistency and the detection performance of the chip are restricted.

(5) MEMS has low productivity, low yield and high cost, and can not realize large-scale batch production.

(6) The existing process capability of the MEMS is not enough to support the preparation of a detector with higher performance, and the MEMS has smaller line width and thinner film thickness, thereby being not beneficial to realizing the miniaturization of a chip.

In addition, in the current infrared detector, the beam structure is easy to fall off from the columnar structure in contact with the beam structure, so that the structural stability of the infrared detector pixel is poor, and further the structural stability of the infrared detector comprising the infrared detector pixel is poor.

Disclosure of Invention

In order to solve the technical problems or at least partially solve the technical problems, the present disclosure provides an infrared detector based on a CMOS process and a method for manufacturing the same, which solve the problems of low performance, low pixel scale, low yield, and the like of the conventional MEMS process infrared detector, and enhance the structural stability of the infrared detector pixel.

In a first aspect, the present disclosure provides an infrared detector based on a CMOS process, including:

the CMOS infrared sensing structure comprises a CMOS measuring circuit system and a CMOS infrared sensing structure, wherein the CMOS measuring circuit system and the CMOS infrared sensing structure are both prepared by using a CMOS process, and the CMOS infrared sensing structure is directly prepared on the CMOS measuring circuit system;

the CMOS measurement circuit system comprises at least one layer of closed release isolation layer above the CMOS measurement circuit system, wherein the closed release isolation layer is used for protecting the CMOS measurement circuit system from being influenced by a process in the etching process of manufacturing the CMOS infrared sensing structure;

the CMOS manufacturing process of the CMOS infrared sensing structure comprises a metal interconnection process, a through hole process and an RDL (remote data link) process, wherein the CMOS infrared sensing structure comprises at least two metal interconnection layers, at least two dielectric layers and a plurality of interconnection through holes;

the CMOS infrared sensing structure comprises a reflecting layer, an infrared conversion structure, a plurality of first columnar structures and a plurality of second columnar structures, wherein the reflecting layer, the infrared conversion structure, the first columnar structures and the second columnar structures are positioned on the CMOS measuring circuit system;

the infrared conversion structure comprises an absorption plate and a plurality of beam structures which are arranged on the same layer, the absorption plate is used for converting infrared signals into electric signals and is electrically connected with the corresponding second columnar structures through the corresponding beam structures, the absorption plate and the beam structures both comprise heat-sensitive layers, and materials forming the heat-sensitive layers comprise at least one of amorphous silicon, amorphous carbon, amorphous germanium or amorphous silicon germanium;

the infrared detector pixel further comprises a reinforced structure, the reinforced structure corresponds to the position where the second columnar structure is located, and the reinforced structure is used for reinforcing the connection stability between the second columnar structure and the beam structure.

Optionally, the reinforcing structure includes a weighted block structure, the weighted block structure is located on a side of the infrared conversion structure far away from the CMOS measurement circuitry, and the weighted block structure is disposed in contact with the infrared conversion structure.

Optionally, the material constituting the weighted bulk structure includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon, silicon carbide, aluminum oxide, aluminum, copper, tungsten, gold, platinum, nickel, chromium, titanium tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, or nickel-silicon alloy.

Optionally, a through hole is formed in the infrared conversion structure at a position corresponding to the second columnar structure, and at least part of the second columnar structure is exposed from the through hole;

the reinforcing structure comprises a weighted block structure, the weighted block structure comprises a first part filling the through hole and a second part located outside the through hole, and the orthographic projection of the second part covers the orthographic projection of the first part.

Optionally, the material constituting the weighted mass structure includes at least one of aluminum, copper, tungsten, gold, platinum, nickel, chromium, titanium tungsten alloy, nickel chromium alloy, nickel platinum alloy, or nickel silicon alloy.

Optionally, the material forming the first columnar structure comprises aluminum, and the material forming the second columnar structure comprises tungsten.

Optionally, the CMOS infrared sensing structure further includes an adhesion layer, and the adhesion layer covers at least a contact surface of the first pillar structure and the second pillar structure.

Optionally, the CMOS infrared sensing structure further includes a first dielectric layer, where the first dielectric layer at least covers a side surface of the first columnar structure;

the CMOS infrared sensing structure further comprises a second dielectric layer, and the second dielectric layer at least covers the side face of the second columnar structure.

Optionally, a sacrificial layer in the infrared detector is used for enabling the CMOS infrared sensing structure to form a hollow structure, the material forming the sacrificial layer is silicon oxide, and the sacrificial layer is etched by a post-CMOS process;

the post-CMOS process etches the sacrificial layer using at least one of gaseous hydrogen fluoride, carbon tetrafluoride, and trifluoromethane.

In a second aspect, the present disclosure provides a method for manufacturing an infrared detector based on a CMOS process, which is used to manufacture the infrared detector based on the CMOS process according to the first aspect, and the method for manufacturing the infrared detector based on the CMOS process includes:

forming the reflective layer on the CMOS measurement circuitry;

forming the first columnar structure on the reflective layer;

forming a sacrificial layer on the reflective layer; wherein a material constituting the sacrificial layer includes silicon oxide;

etching the sacrificial layer to form a first through hole corresponding to the position of the first columnar structure; wherein the first through hole exposes at least a part of the first columnar structure;

forming the second columnar structure in the first through hole;

forming the infrared conversion structure on the sacrificial layer;

forming the reinforcing structure.

Optionally, before forming the first pillar structure on the reflective layer, the method further includes:

forming a whole layer of reflecting layer on the CMOS measuring circuit system;

etching the whole reflecting layer to form the reflecting plate and the supporting base;

forming a fourth dielectric layer on the reflecting layer and processing the fourth dielectric layer by adopting a CMP (chemical mechanical polishing) process; wherein a polishing termination interface of the CMP process for the fourth dielectric layer is flush with a surface of the reflective layer away from the CMOS measurement circuitry.

Optionally, forming the second columnar structure within the first via includes:

forming a second medium layer on the whole surface and etching the second medium layer to form a second through hole corresponding to the position of the first columnar structure; wherein the second via exposes at least a portion of the first columnar structure;

forming a whole adhesive layer;

forming a whole metal layer; wherein the metal layer fills the second via;

processing the metal layer, the adhesion layer and the second dielectric layer by adopting a CMP (chemical mechanical polishing) process; wherein a polish-stop interface of the CMP process for the metal layer, the adhesion layer, and the second dielectric layer is flush with a surface of the sacrificial layer away from the CMOS measurement circuitry; and the metal layer positioned in the second through hole forms the second columnar structure.

Optionally, forming the reinforcing structure comprises:

forming a whole reinforcing layer on the infrared conversion structure;

etching the reinforcing layer to form the reinforcing structure; wherein the reinforcing structure comprises a weighted block structure;

alternatively, forming the reinforcing structure comprises:

forming a through hole at the position of the infrared conversion structure corresponding to the second columnar structure; wherein the through hole exposes at least a portion of the second columnar structure;

forming a whole reinforcing layer on the infrared conversion structure;

etching the reinforcing layer to form the reinforcing structure; wherein the reinforcing structure comprises a weighted block structure, the weighted block structure comprises a first part filling the through hole and a second part located outside the through hole, and the orthographic projection of the second part covers the orthographic projection of the first part.

Optionally, after forming the reinforcing structure, the method further includes:

and releasing the sacrificial layer.

Compared with the prior art, the technical scheme provided by the embodiment of the disclosure has the following advantages:

(1) the CMOS measurement circuit system and the CMOS infrared sensing structure are integrally prepared on the CMOS production line by utilizing the CMOS process, compared with the MEMS process, the CMOS does not have the process compatibility problem, the technical difficulty of the MEMS process is solved, the transportation cost can be reduced by adopting the CMOS process production line process to prepare the infrared detector, and the risk caused by the transportation problem and the like is reduced; the infrared detector takes silicon oxide as a sacrificial layer, the silicon oxide is completely compatible with a CMOS (complementary metal oxide semiconductor) process, the preparation process is simple and easy to control, the CMOS process does not have the problem that the polyimide of the sacrificial layer is not released cleanly to influence the vacuum degree of a detector chip, the subsequent film growth temperature is not limited by the material of the sacrificial layer, the multilayer process design of the sacrificial layer can be realized, the process is not limited, the planarization can be easily realized by using the sacrificial layer, and the process difficulty and the possible risks are reduced; the infrared detector prepared by the integrated CMOS process can realize the aims of high yield, low cost, high yield and large-scale integrated production of chips, and provides a wider application market for the infrared detector; the infrared detector based on the CMOS process can realize smaller size and thinner film thickness of a characteristic structure, so that the infrared detector has larger duty ratio, lower thermal conductivity and smaller thermal capacity, and the infrared detector has higher detection sensitivity, longer detection distance and better detection performance; the infrared detector based on the CMOS process can make the pixel size of the detector smaller, realize smaller chip area under the same array pixel, and is more beneficial to realizing the miniaturization of a chip; the infrared detector based on the CMOS process has the advantages of mature process production line, higher process control precision, better meeting design requirements, better product consistency, more contribution to circuit chip adjustment performance and more contribution to industrialized mass production.

(2) The embodiment of the disclosure further provides a CMOS infrared sensing structure, which comprises a reflecting layer located on the CMOS measuring circuit system, an infrared conversion structure, a plurality of first columnar structures and a plurality of second columnar structures, wherein the first columnar structures and the second columnar structures are located between the reflecting layer and the infrared conversion structure, the first columnar structures are located on one side, close to the CMOS measuring circuit system, of the second columnar structures, the reflecting layer comprises a reflecting plate and a supporting base, the infrared conversion structure passes through the second columnar structures, the first columnar structures and the supporting base are electrically connected with the CMOS measuring circuit system, so that the infrared detector converts infrared signals into electric signals, the CMOS measuring circuit system is utilized to reflect temperature signals corresponding to the infrared signals, and the temperature detection function of effective pixels of the infrared detector is realized. In addition, the absorption plate and the beam structure are arranged to comprise the thermosensitive layer, so that the heat conductivity of the beam structure is reduced, and the infrared response rate of the infrared detector is further improved. In addition, it still includes reinforced structure to set up the infrared detector pixel, and reinforced structure corresponds the setting of second columnar structure place position, and reinforced structure is used for strengthening the connection steadiness between second columnar structure and the beam structure, can effectively strengthen the mechanical stability between second columnar structure and the beam structure to promote the infrared detector pixel and the infrared detector including the infrared detector pixel's structural stability.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.

In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present disclosure, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.

Fig. 1 is a schematic perspective view of an infrared detector according to an embodiment of the present disclosure;

fig. 2 is a schematic cross-sectional structure diagram of an infrared detector provided in an embodiment of the present disclosure;

fig. 3 is a schematic cross-sectional view of another infrared detector provided in the embodiments of the present disclosure;

fig. 4 is a schematic cross-sectional view of another infrared detector provided in the embodiments of the present disclosure;

fig. 5 is a schematic cross-sectional view of another infrared detector provided in the embodiments of the present disclosure;

FIG. 6 is a schematic cross-sectional view of another infrared detector provided in the embodiments of the present disclosure;

fig. 7 is a schematic structural diagram of a CMOS measurement circuitry according to an embodiment of the disclosure;

FIG. 8 is a schematic cross-sectional view of another infrared detector provided in accordance with an embodiment of the present disclosure;

fig. 9 is a schematic perspective view of another infrared detector provided in the embodiments of the present disclosure;

fig. 10 is a schematic flow chart illustrating a method for manufacturing an infrared detector according to an embodiment of the present disclosure;

fig. 11 to 26 are schematic cross-sectional structures corresponding to steps of the manufacturing method shown in fig. 10.

Detailed Description

In order that the above objects, features and advantages of the present disclosure may be more clearly understood, aspects of the present disclosure will be further described below. It should be noted that the embodiments and features of the embodiments of the present disclosure may be combined with each other without conflict.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced in other ways than those described herein; it is to be understood that the embodiments disclosed in the specification are only a few embodiments of the present disclosure, and not all embodiments.

Fig. 1 is a schematic perspective structure diagram of an infrared detector provided in an embodiment of the present disclosure, and fig. 2 is a schematic cross-sectional structure diagram of an infrared detector provided in an embodiment of the present disclosure. With reference to fig. 1 and 2, the CMOS process-based infrared detector includes a CMOS measurement circuit system 1 and a CMOS infrared sensing structure 2, both the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 are manufactured by using a CMOS process, and the CMOS infrared sensing structure 2 is directly manufactured on the CMOS measurement circuit system 1.

Specifically, the CMOS infrared sensing structure 2 is configured to convert an external infrared signal into an electrical signal and transmit the electrical signal to the CMOS measurement circuit system 1, and the CMOS measurement circuit system 1 reflects temperature information corresponding to the infrared signal according to the received electrical signal, thereby implementing a temperature detection function of the infrared detector. The CMOS measuring circuit system 1 and the CMOS infrared sensing structure 2 are both prepared by using a CMOS process, and the CMOS infrared sensing structure 2 is directly prepared on the CMOS measuring circuit system 1, namely, the CMOS measuring circuit system 1 is prepared by using the CMOS process, and then the CMOS infrared sensing structure 2 is continuously prepared by using the CMOS process by using the CMOS production line and parameters of various processes compatible with the production line.

Therefore, the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 are integrally prepared on the CMOS production line by utilizing the CMOS process, compared with the MEMS process, the CMOS process does not have the process compatibility problem, the technical difficulty of the MEMS process is solved, the transportation cost can be reduced by adopting the CMOS production line process to prepare the infrared detector, and the risk caused by the transportation problem and the like is reduced; the infrared detector takes silicon oxide as a sacrificial layer, the silicon oxide is completely compatible with a CMOS (complementary metal oxide semiconductor) process, the preparation process is simple and easy to control, the CMOS process does not have the problem that the polyimide of the sacrificial layer is not released cleanly to influence the vacuum degree of a detector chip, the subsequent film growth temperature is not limited by the material of the sacrificial layer, the multilayer process design of the sacrificial layer can be realized, the process is not limited, the planarization can be easily realized by using the sacrificial layer, and the process difficulty and the possible risks are reduced; the infrared detector prepared by the integrated CMOS process can realize the aims of high yield, low cost, high yield and large-scale integrated production of chips, and provides a wider application market for the infrared detector; the infrared detector based on the CMOS process can realize smaller size and thinner film thickness of a characteristic structure, so that the infrared detector has larger duty ratio, lower thermal conductivity and smaller thermal capacity, and the infrared detector has higher detection sensitivity, longer detection distance and better detection performance; the infrared detector based on the CMOS process can make the pixel size of the detector smaller, realize smaller chip area under the same array pixel, and is more beneficial to realizing the miniaturization of a chip; the infrared detector based on the CMOS process has the advantages of mature process production line, higher process control precision, better meeting design requirements, better product consistency, more contribution to circuit chip adjustment performance and more contribution to industrialized mass production.

Referring to fig. 1 and 2, the CMOS infrared sensor structure 2 includes a reflective layer 3 located on the CMOS measurement circuit system 1, an infrared conversion structure 4, a plurality of first columnar structures 5 and a plurality of second columnar structures 6, the first columnar structures 5 and the second columnar structures 6 are located between the reflective layer 3 and the infrared conversion structure 4, and the first columnar structures 5 are located on one side of the second columnar structures 6 close to the CMOS measurement circuit system 1, the reflective layer 3 includes a reflective plate 7 and a supporting base 8, the infrared conversion structure 4 is connected electrically to the CMOS measurement circuit system 1 through the second columnar structures 6, the first columnar structures 5 and the supporting base 8. Note that the columnar structure shown in fig. 1 includes a first columnar structure and a second columnar structure.

Specifically, the first columnar structure 5 and the second columnar structure 6 are located between the reflective layer 3 and the infrared conversion structure 4 and used for supporting the infrared conversion structure 4 after a sacrificial layer on the CMOS measurement circuit system 1 is released, the first columnar structure 5 and the second columnar structure 6 are metal structures, an electrical signal converted by the infrared conversion structure 4 through an infrared signal is transmitted to the CMOS measurement circuit system 1 through the corresponding first columnar structure 5 and the corresponding second columnar structure 6 and the corresponding supporting base 8, and the CMOS measurement circuit system 1 processes the electrical signal to reflect temperature information, so that non-contact infrared temperature detection of the infrared detector is realized. The infrared conversion structure 4 outputs a positive electric signal and a ground electric signal through different electrode structures, the positive electric signal and the ground electric signal are transmitted to a supporting base 8 electrically connected with the corresponding first columnar structure 5 and the second columnar structure 6 through the different first columnar structure 5 and the different second columnar structure 6, fig. 1 and fig. 2 schematically show the direction parallel to the CMOS measuring circuit system 1, the infrared detector includes two columnar structures, one of the columnar structures can be set for transmitting the positive electric signal, the other columnar structure is set for transmitting the ground electric signal, the infrared detector can also be set to include four columnar structures, two of the columnar structures are a group and respectively transmit the positive electric signal and the ground electric signal, and each columnar structure includes the first columnar structure 5 and the second columnar structure 6.

In addition, the reflecting layer 3 comprises a reflecting plate 7 and a supporting base 8, a part of the reflecting layer 3 is used as a dielectric medium electrically connected with the CMOS measuring circuit system 1 in a columnar structure, namely, the supporting base 8, the reflecting plate 7 is used for reflecting infrared rays to the infrared conversion structure 4, and the secondary absorption of the infrared rays is realized by matching with a resonant cavity formed between the reflecting layer 3 and the infrared conversion structure 4, so that the infrared absorption rate of the infrared detector is improved, and the infrared detection performance of the infrared detector is optimized.

The embodiment of the present disclosure further provides a CMOS infrared sensing structure 2 including a reflection layer 3 located on the CMOS measurement circuit system 1, an infrared conversion structure 4, a plurality of first columnar structures 5 and a plurality of second columnar structures 6, the first columnar structures 5 and the second columnar structures 6 are located between the reflection layer 3 and the infrared conversion structure 4, and the first columnar structures 5 are located on one side of the second columnar structures 6 close to the CMOS measurement circuit system 1, the reflection layer 3 includes a reflection plate 7 and a supporting base 8, the infrared conversion structure 4 passes through the second columnar structures 6, the first columnar structures 5 and the supporting base 8 are electrically connected with the CMOS measurement circuit system 1, so that the infrared detector converts infrared signals into electrical signals, and reflects temperature signals corresponding to the infrared signals by using the CMOS measurement circuit system 1, thereby realizing a temperature detection function of effective pixels of the infrared detector. In addition, two-layer columnar structure of the first columnar structure 5 and the second columnar structure 6 is arranged between the infrared conversion structure 4 and the reflecting layer 3, and the steepness of the columnar structures is favorably optimized.

With reference to fig. 1 and 2, the infrared conversion structure 4 includes an absorption plate 9 and a plurality of beam structures 10 disposed in the same layer, the absorption plate 9 is configured to convert an infrared signal into an electrical signal and is electrically connected to the corresponding second pillar structure 6 through the corresponding beam structure 10, each of the absorption plate 9 and the beam structure 10 includes a thermal sensitive layer 11, and a material constituting the thermal sensitive layer 11 includes at least one of amorphous silicon, amorphous carbon, amorphous germanium, or amorphous silicon germanium.

Specifically, the infrared conversion structure 4 includes an absorption plate 9 and a plurality of beam structures 10 disposed on the same layer, the absorption plate 9 is configured to convert an infrared signal into an electrical signal and is electrically connected to the corresponding second columnar structure 6 through the corresponding beam structure 10, the absorption plate 9 includes a support layer 18, an electrode layer 19, a thermal sensitive layer 11 and a passivation layer 20, the beam structure 10 also includes a support layer 18, an electrode layer 19, a thermal sensitive layer 11 and a passivation layer 20, the thermal sensitive layer 11 covers the beam structure 10, which is beneficial to reducing thermal conductivity of the beam structure 10, the support layer 18 is located on a side of the passivation layer 20 close to the CMOS measurement circuit system 1, the electrode layer 19 and the thermal sensitive layer 11 are located between the support layer 18 and the passivation layer 20, and the passivation layer 20 covers the electrode layer 19 and the thermal sensitive layer 11.

Specifically, the first columnar structure 5 and the second columnar structure 6 are located on the CMOS measurement circuit system 1 and are configured to support the infrared conversion structure 4 after a sacrificial layer on the CMOS measurement circuit system 1 is released, the infrared conversion structure 4 includes an absorption plate 9 and a plurality of beam structures 10, and the second columnar structure 6 is overlapped with the beam structures 10 to further support the infrared conversion structure 4. The supporting layer 18 is used for supporting an upper film layer in the infrared conversion structure 4 after the sacrificial layer is released, the thermosensitive layer 11 is used for converting infrared temperature detection signals into infrared detection electric signals, the electrode layer 19 is used for transmitting the infrared detection electric signals converted by the thermosensitive layer 11 to the CMOS measurement circuit system 1 through the beam structures 10 on the left side and the right side, the two beam structures 10 respectively transmit positive and negative signals of the infrared detection electric signals, a reading circuit in the CMOS measurement circuit system 1 realizes non-contact infrared temperature detection through analysis of the acquired infrared detection electric signals, and the passivation layer 20 is used for protecting the electrode layer 19 and the thermosensitive layer 11 from being oxidized or corroded. The thermosensitive layer 11 may be located above the electrode layer 19, or may be located below the electrode layer 19. The absorption plate 9 can be correspondingly arranged, the thermosensitive layer 11 and the electrode layer 19 are located in a closed space formed by the supporting layer 18 and the passivation layer 20, so that the thermosensitive layer 11 and the electrode layer 19 in the absorption plate 9 are protected, and the thermosensitive layer 11 and the electrode layer 19 are located in a closed space formed by the supporting layer 18 and the passivation layer 20, so that the thermosensitive layer 11 and the electrode layer 19 in the beam structure 10 are protected.

With reference to fig. 1 and 2, the infrared detector pixel further includes a reinforcing structure 12 (not shown in fig. 1), where the reinforcing structure 12 is disposed corresponding to the position of the second columnar structure 6, and the reinforcing structure 12 is used for enhancing the connection stability between the second columnar structure 6 and the beam structure 10. Specifically, set up the infrared detector pixel and still include reinforced structure 12, reinforced structure 12 corresponds the setting of second columnar structure 6 position, and reinforced structure 12 is used for strengthening the connection steadiness between second columnar structure 6 and beam structure 10, can effectively strengthen the mechanical stability between second columnar structure 6 and the beam structure 10 to promote the infrared detector pixel and the infrared detector's that includes the infrared detector pixel structural stability.

Alternatively, in conjunction with fig. 1 and 2, it may be provided that the reinforcing structure 12 comprises a weighted block structure 13, the weighted block structure 13 being located on a side of the infrared conversion structure 4 remote from the CMOS measurement circuitry 1 and the weighted block structure 13 being arranged in contact with the infrared conversion structure 4. Specifically, set up the setting of reinforced structure 12 and correspond the position setting of second column structure 6, aggravate massive structure 13 and be located one side that CMOS measurement circuitry 1 was kept away from to infrared conversion structure 4 and aggravate massive structure 13 and infrared conversion structure 4 contact setting, be equivalent to increase a apron in the position that beam structure 10 corresponds second column structure 6, utilize reinforced structure 12 self weight to push down beam structure 10, thereby strengthen the mechanical strength between beam structure 10 and the second column structure 6, promote infrared detector's structural stability.

Illustratively, the material that may be provided to constitute the weight-up block structure 13 includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon, silicon carbide, alumina, aluminum, copper, tungsten, gold, platinum, nickel, chromium, titanium tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, or nickel-silicon alloy. Specifically, the reinforcing structure 12 may be a single-layer structure formed by deposition of a medium or a metal, or may be a multi-layer structure formed by stacking two, three, or more single-layer structures, and the above-mentioned materials constituting the reinforcing structure 12 are not corroded by VHF (gas phase hydrogen fluoride), so that the reinforcing structure 12 is not affected in the subsequent process of using the VHF to corrode the sacrificial layer to release the sacrificial layer, thereby ensuring that the mechanical strength of the joint position between the beam structure 10 and the second columnar structure 6 can be enhanced by the reinforcing structure 12, preventing the beam structure 10 and the columnar structure from falling off due to the infirm connection, and improving the structural stability of the infrared detector.

Fig. 3 is a schematic cross-sectional structure diagram of another infrared detector pixel provided in the embodiment of the disclosure. With reference to fig. 1 and 3, it may be provided that the infrared conversion structure 4 is formed with a through hole corresponding to the position of the second columnar structure 6, the through hole exposes at least part of the second columnar structure 6, the reinforcing structure 12 includes a weighting block structure 13, the weighting block structure 13 includes a first portion filling the through hole and a second portion located outside the through hole, and an orthographic projection of the second portion covers an orthographic projection of the first portion.

Specifically, the position of the infrared conversion structure 4 corresponding to the second cylindrical structure 6 includes a hollow-out area, i.e., a through hole is formed, the second portion outside the through hole and the first portion inside the through hole are integrally formed, the first portion is filled or embedded into the through hole and is in contact with the second cylindrical structure 6, the orthographic projection of the second portion covers the orthographic projection of the first portion, i.e., the area of the second portion is larger than that of the first portion. In the infrared detector pixel, the reinforcing structure 12 is equivalent to a rivet structure composed of a first part and a second part, the bottom surface of the first part is in contact with the top surface of the second columnar structure 6, the side surface of the first part is also in contact with the side surface of a hollow area formed by the infrared conversion structure 4, and the lower surface of the second part is in contact with the outer surface of the through hole. Therefore, when the gravity of the reinforcing structure 12 is utilized to press the beam structure 10, the contact area between the reinforcing structure 12 and the second columnar structure 6 and the contact area between the reinforcing structure 12 and the beam structure 10 are increased, the mechanical strength between the beam structure 10 and the second columnar structure 6 is further increased, and the structural stability of the infrared detector is improved.

Illustratively, the material that may be provided to constitute the weight block structure 13 includes at least one of aluminum, copper, tungsten, gold, platinum, nickel, chromium, titanium tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, or nickel-silicon alloy. Specifically, the reinforcing structure 12 may be a single-layer structure formed by metal deposition, or a multi-layer structure formed by stacking two, three, or more single-layer metal structures, and the above materials constituting the reinforcing structure 12 are not corroded by VHF (gas phase hydrogen fluoride), so that the reinforcing structure 12 is not affected in the subsequent process of using the VHF to corrode the sacrificial layer to release the sacrificial layer, thereby ensuring that the mechanical strength of the reinforcing structure 12 at the position of the joint between the beam structure 10 and the second columnar structure 6 can be enhanced, preventing the beam structure 10 and the columnar structure from falling off due to the infirm connection, and improving the structural stability of the infrared detector. In addition, the reinforcing structure 12 in the infrared detector having the structure shown in fig. 3 is made of a metal material, and electrical connectivity between the beam structure 10 and the corresponding second columnar structure 6 can be ensured. Illustratively, in conjunction with fig. 1 to 3, it may be provided that the material constituting the first columnar structure 5 includes aluminum and the material constituting the second columnar structure 6 includes tungsten.

Alternatively, in conjunction with fig. 1 to 3, the CMOS infrared sensing structure 2 may further include an adhesion layer 14, and the adhesion layer 14 covers at least the contact surfaces of the first pillar structure 5 and the second pillar structure 6. Illustratively, the material constituting the adhesion layer 14 includes at least one of titanium, titanium nitride, tantalum, or tantalum nitride to optimize the effect of electrical contact between the first pillar structure 5 and the second pillar structure 6.

Optionally, with reference to fig. 1 to 3, the CMOS infrared sensing structure 2 further includes a first dielectric layer 15, and the first dielectric layer 15 covers at least a side surface of the first pillar structure 5. Specifically, the CMOS infrared sensing structure 2 further includes a first dielectric layer 15, the first dielectric layer 15 at least covers the side surface of the first columnar structure 5, the second columnar structure 6 is electrically connected to the first columnar structure 5 through a through hole formed in the first dielectric layer 15, after the first columnar structure 5 is formed, a complete layer of the first dielectric layer 15 is formed on the first columnar structure 5, the material forming the first dielectric layer 15 may be, for example, silicon carbide, a through hole penetrating through the first dielectric layer 15 is formed at a position corresponding to the first columnar structure 5, the second columnar structure 6 is electrically connected to the first columnar structure 5 through a through hole formed in the first dielectric layer 15, so as to realize transmission of an electrical signal obtained through infrared signal conversion, and the first dielectric layer 15 covers the side surface of the first columnar structure 5 and covers the CMOS measurement circuit system 1, so as to realize effective protection of the first columnar structure 5 and the CMOS measurement circuit system 1, the first columnar structure 5 and the CMOS measurement circuitry 1 are not affected by water oxygen in the external environment, nor by the reagent used to release the sacrificial layer.

Optionally, with reference to fig. 1 to 3, the CMOS infrared sensing structure 2 further includes a second dielectric layer 16, the second dielectric layer 16 covers at least a side surface of the second columnar structure 6, the second dielectric layer 16 may be disposed to expose an upper surface of the second columnar structure 6, so as to provide an electrical contact area between the infrared conversion structure 4 and the second columnar structure 6, so as to implement transmission of an electrical signal obtained through conversion of the infrared signal, a material constituting the second dielectric layer 16 may be, for example, amorphous carbon or aluminum oxide, and the second dielectric layer 16 covers at least a side surface of the second columnar structure 6, so as to implement effective protection of the second columnar structure 6, and the second columnar structure 6 is not affected by water and oxygen in an external environment, and is not affected by a reagent for releasing a sacrificial layer.

Optionally, with reference to fig. 1 to fig. 3, the CMOS infrared sensing structure 2 may further include a fourth dielectric layer 21, where the fourth dielectric layer 21 includes a patterned dielectric structure, the patterned dielectric structure is located on the same layer as the reflective plate 7 and the supporting base 8, and a CMP process is adopted to make a surface of the fourth dielectric layer 21 away from the CMOS measurement circuit system 1 flush with a surface of the reflective layer 3 away from the CMOS measurement circuit system 1. Specifically, after the reflecting plate 7 and the supporting base 8 are prepared and formed, the whole fourth dielectric layer 21 is deposited on the reflecting plate 7 and the supporting base, the fourth dielectric layer 21 fills a gap between the reflecting plate 7 and the supporting base 8, and the fourth dielectric layer and the reflecting layer 3 are processed by adopting a CMP (chemical mechanical polishing) process, so that the surface of the fourth dielectric layer departing from the CMOS (complementary metal oxide semiconductor) measuring circuit system 1 is flush with the surface of the reflecting layer 3 departing from the CMOS measuring circuit system 1, the planarization of the surface of the patterned dielectric structure, the reflecting plate 7 and the supporting base 8 is effectively realized, the preparation difficulty of subsequent films can be reduced, and the planarization degree of the whole infrared detector is favorably optimized. In addition, the fourth dielectric layer 21, the reflector 7 and the supporting base 8 are reasonably matched, so that the CMOS measuring circuit system 1 can be well protected. Illustratively, the material constituting the fourth dielectric layer 21 may be configured to include at least one of silicon, germanium, a silicon-germanium alloy, amorphous silicon, amorphous germanium, amorphous silicon-germanium, amorphous carbon, silicon carbide, aluminum oxide, silicon carbon nitride, or silicon nitride, and the thickness of the fourth dielectric layer 21 may be greater than or equal to 1000A and less than or equal to 10000A. In addition, the fourth dielectric layer 21 also plays a role of electrical insulation, which can effectively prevent the first columnar structure 5 and the reflector 7 from being electrically connected, and the fourth dielectric layer 21 also plays a role of isolation, which is used as an etching stop interface of the first columnar structure 5.

Optionally, with reference to fig. 1 to 3, a protective dielectric layer 22 may be further disposed above the reflective layer 3, a through hole is formed at a position where the protective dielectric layer 22 corresponds to the supporting base 8, and the first columnar structure 5 is electrically connected to the corresponding supporting base 8 through the through hole. Illustratively, the material forming the support base 8 may include, for example, aluminum, the material forming the protective dielectric layer 22 may include, for example, one or more of silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride, and the protective dielectric layer 22 may protect the support base 8 from oxidation and corrosion after the sacrificial layer is released.

Illustratively, with reference to fig. 1 to 3, a sacrificial layer to be released is further disposed between the reflective layer 3 and the absorption plate 9, the sacrificial layer is used for forming the CMOS infrared sensing structure 2 into a hollow structure, the material constituting the sacrificial layer is silicon oxide, and the sacrificial layer is etched by a post-CMOS process, which may be, for example, etching the sacrificial layer by at least one of gaseous hydrogen fluoride, carbon tetrafluoride and trifluoromethane, and the material constituting the sacrificial layer is silicon oxide so as to be compatible with the CMOS process, and may be etched by a post-CMOS process, that is, the post-CMOS process is used to release the sacrificial layer in the final infrared detection chip product.

Referring to fig. 1 to 3, the infrared conversion structure 4 transmits the electrical signal converted from the infrared signal to the CMOS measurement circuit system 1 through the corresponding first and second

columnar structures

5 and 6 and the corresponding support base 8, and the CMOS measurement circuit system 1 processes the electrical signal to reflect temperature information, thereby implementing non-contact infrared temperature detection of the infrared detector. The CMOS infrared sensing structure 2 outputs positive electric signals and grounding electric signals through different electrode structures, the positive electric signals and the grounding electric signals are transmitted to the corresponding supporting base 8 through different first columnar structures 5 and second columnar structures 6, fig. 1 to 3 exemplarily show the direction parallel to the CMOS measuring circuit system 1, the CMOS infrared sensing structure 2 comprises two groups of columnar structures, each group of columnar structures comprises one first columnar structure 5 and one second columnar structure 6, one group of columnar structures can be arranged and used for transmitting the positive electric signals, the other group of columnar structures can be arranged and used for transmitting the grounding electric signals, the CMOS infrared sensing structure 2 also can be arranged and comprises four groups of columnar structures, and every two groups of columnar structures are respectively used as one group and transmit the positive electric signals and the grounding electric signals. In addition, the reflecting layer 3 comprises a reflecting plate 7 and a supporting base 8, a part of the reflecting layer 3 is used as a dielectric medium electrically connected with the CMOS measuring circuit system 1 in a columnar structure, namely, the supporting base 8, the reflecting plate 7 is used for reflecting infrared rays to the infrared conversion structure 4, and the secondary absorption of the infrared rays is realized by matching with a resonant cavity formed between the reflecting layer 3 and the infrared conversion structure 4, so that the infrared absorption rate of the infrared detector is improved, and the infrared detection performance of the infrared detector is optimized.

Referring to fig. 1 to 3, the infrared conversion structure 4 includes a plurality of beam structures 10 and an absorption plate 9, and the absorption plate 9 is used to convert an infrared signal into an electrical signal and is electrically connected to the corresponding second pillar structure 6 through the corresponding beam structure 10. In particular, the absorption plate 9 is used for converting infrared signals into electrical signals and is electrically connected with the corresponding second pillar structures 6 through the corresponding beam structures 10, the absorption plate 9 comprises a support layer 18, an electrode layer 19, a thermal sensitive layer 11 and a passivation layer 20, the beam structure 10 may comprise the support layer 18, the electrode layer 19 and the passivation layer 20, the beam structure 10 may further comprise the thermal sensitive layer 11, the support layer 18 is located on a side of the passivation layer 20 adjacent to the CMOS measurement circuitry 1, the electrode layer 19 and the thermal sensitive layer 11 are located between the support layer 18 and the passivation layer 20, the passivation layer 20 covers the electrode layer 19, the thermal sensitive layer 11 may be arranged to cover the position of the beam structure 10, and the thermal conductivity of the beam structure 10 is reduced by using the characteristic of small thermal conductivity of a thermal sensitive material, such as amorphous silicon, amorphous germanium, or amorphous silicon germanium, and the thermal sensitive layer 11 may be used as a support material of the beam structure 10 instead of the support layer 18, and may also be used as an electrode protection material of the beam structure 10 instead of the passivation layer 20.

Specifically, the supporting layer 18 is used for supporting an upper film layer in the infrared conversion structure 4 after the sacrificial layer 8 is released, the thermosensitive layer 11 is used for converting infrared temperature detection signals into infrared detection electrical signals, the electrode layer 19 is used for transmitting the infrared detection electrical signals converted by the thermosensitive layer 11 to the CMOS measurement circuit system 1 through the beam structures 10 on the left side and the right side, the two beam structures 10 respectively transmit positive and negative signals of the infrared detection electrical signals, a readout circuit in the CMOS measurement circuit system 1 realizes non-contact infrared temperature detection through analysis of the acquired infrared detection electrical signals, and the passivation layer 20 is used for protecting the electrode layer 19 from oxidation or corrosion. The thermosensitive layer 11 may be located above the electrode layer 19, or may be located below the electrode layer 19. The absorption plate 9 can be correspondingly arranged, the thermosensitive layer 11 and the electrode layer 19 are located in a closed space formed by the supporting layer 18 and the passivation layer 20, so that the thermosensitive layer 11 and the electrode layer 19 in the absorption plate 9 are protected, and the electrode layer 19 is located in a closed space formed by the supporting layer 18 and the passivation layer 20 corresponding to the beam structure 10, so that the electrode layer 19 in the beam structure 10 is protected.

For example, the material constituting the heat sensitive layer 11 may include at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, titanium oxide, vanadium oxide, or titanium vanadium oxide, the material constituting the support layer 18 may include one or more of amorphous carbon, aluminum oxide, amorphous silicon, amorphous germanium, or amorphous silicon germanium, the material constituting the electrode layer 19 may include one or more of titanium, titanium nitride, tantalum nitride, titanium tungsten alloy, nickel-chromium alloy, nickel-silicon alloy, nickel, or chromium, and the material constituting the passivation layer 20 may include one or more of amorphous carbon, aluminum oxide, amorphous silicon, amorphous germanium, or amorphous silicon germanium. In addition, when the absorption plate 9 is disposed to include the thermal sensitive layer 11, and the thermal sensitive layer 11 is made of amorphous silicon, amorphous carbon, amorphous germanium, or amorphous silicon germanium, the supporting layer 18 and/or the passivation layer 20 on the beam structure 10 may be replaced by the thermal sensitive layer 11, because the thermal conductivity of the amorphous silicon, amorphous germanium, or amorphous silicon germanium is relatively small, which is beneficial to reducing the thermal conductivity of the beam structure 10, and further improving the infrared responsivity of the infrared detector.

With reference to fig. 1 to 3, at least one layer of hermetic release isolation layer 17 may be included above the CMOS measurement circuitry 1, and the hermetic release isolation layer 17 is used to protect the CMOS measurement circuitry 1 from process influence during an etching process for manufacturing the CMOS infrared sensing structure 2. Optionally, a hermetic release barrier 17 is located at an interface between the CMOS measurement circuitry 1 and the CMOS infrared sensing structure 2 and/or in the CMOS infrared sensing structure 2, the hermetic release barrier 17 is used to protect the CMOS measurement circuitry 1 from erosion when performing a corrosion process to release the sacrificial layer, and the hermetic release barrier 17 is made of a CMOS process corrosion resistant material including at least one of silicon, germanium, silicon germanium alloy, amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon, silicon carbide, aluminum oxide, silicon nitride, or silicon carbonitride.

Fig. 2 exemplarily sets up the hermetic release insulating layer 17 in the CMOS infrared sensing structure 2, the hermetic release insulating layer 17 may be located above the metal interconnection layer of the reflective layer 3, for example, the hermetic release insulating layer 17 covers the first columnar structure 5, and the hermetic release insulating layer 17 covers the first columnar structure 5, so that on one hand, the hermetic release insulating layer 17 may be used as a support for the first columnar structure 5, thereby improving the stability of the first columnar structure 5, and ensuring the electrical connection between the first columnar structure 5 and the infrared conversion structure 4 as well as the support base 8. On the other hand, the closed release insulating layer 17 covering the first columnar structure 5 can reduce the contact between the first columnar structure 5 and the external environment, reduce the contact resistance between the first columnar structure 5 and the external environment, further reduce the noise of the infrared detector pixel, and improve the detection sensitivity of the infrared detection sensor. In addition, the resonant cavity of the infrared detector is realized by releasing the vacuum cavity after the silicon oxide sacrificial layer is released, the reflecting layer 3 is used as the reflecting layer of the resonant cavity, the sacrificial layer is positioned between the reflecting layer 3 and the infrared conversion structure 4, and when at least one layer of closed release isolating layer 17 positioned on the reflecting layer 3 selects silicon, germanium, silicon-germanium alloy, amorphous silicon, amorphous germanium or amorphous silicon-germanium as one part of the resonant cavity, the reflecting effect of the reflecting layer is not influenced, the height of the resonant cavity can be reduced, the thickness of the sacrificial layer is further reduced, and the release difficulty of the sacrificial layer formed by silicon oxide is reduced. In addition, a closed release isolation layer 17 and the first columnar structure 5 are arranged to form a closed structure, so that the CMOS measurement circuit system 1 is completely separated from the sacrificial layer, and the CMOS measurement circuit system 1 is protected.

Fig. 4 is a schematic cross-sectional structure view of another infrared detector provided in the embodiment of the present disclosure. Unlike the infrared detector having the structure shown in fig. 2 and 3, in the infrared detector having the structure shown in fig. 4, the hermetic release insulating layer 17 is located at the interface between the CMOS measurement circuitry 1 and the CMOS infrared sensing structure 2, for example, the hermetic release insulating layer 17 is located between the reflective layer 3 and the CMOS measurement circuitry 1, that is, the hermetic release insulating layer 17 is located below the metal interconnection layer of the reflective layer 3, and the support base 8 is electrically connected to the CMOS measurement circuitry 1 through a through hole penetrating through the hermetic release insulating layer 17. Specifically, because the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 are both formed by using a CMOS process, after the CMOS measurement circuit system 1 is formed, a wafer including the CMOS measurement circuit system 1 is transferred to a next process to form the CMOS infrared sensing structure 2, and since silicon oxide is the most commonly used dielectric material in the CMOS process and silicon oxide is mostly used as an insulating layer between metal layers on the CMOS circuit, if no insulating layer is used as a barrier when silicon oxide with a thickness of about 2um is corroded, the circuit will be seriously affected, so that a silicon oxide medium on the CMOS measurement circuit system is not corroded when the silicon oxide of the sacrificial layer is released, and a closed release insulating layer 17 is provided. After the CMOS measuring circuit system 1 is prepared and formed, a closed release isolation layer 17 is prepared and formed on the CMOS measuring circuit system 1, the CMOS measuring circuit system 1 is protected by the closed release isolation layer 17, in order to ensure the electric connection between the support base 8 and the CMOS measuring circuit system 1, after the closed release isolation layer 17 is prepared and formed, a through hole is formed in the area of the closed release isolation layer 17 corresponding to the support base 8 by adopting an etching process, and the electric connection between the support base 8 and the CMOS measuring circuit system 1 is realized through the through hole. In addition, a closed release isolation layer 17 and the support base 8 are arranged to form a closed structure, so that the CMOS measurement circuit system 1 is completely separated from the sacrificial layer, and the CMOS measurement circuit system 1 is protected.

Fig. 5 is a schematic cross-sectional structure view of another infrared detector provided in the embodiment of the present disclosure. Different from the infrared detector with the structure shown in fig. 2 to 4, in the infrared detector with the structure shown in fig. 5, at least one layer of airtight release insulating layer 17 is arranged on the interface between the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2, and at least one layer of airtight release insulating layer 17 is arranged in the CMOS infrared sensing structure 2, that is, at least one layer of airtight release insulating layer 17 is arranged between the reflection layer 3 and the CMOS measurement circuit system 1, and at least one layer of airtight release insulating layer 17 is arranged on the reflection layer 3, which has the same effects as above, and is not described herein again.

Illustratively, the material constituting the hermetic release barrier layer 17 may include at least one of silicon, germanium, a silicon-germanium alloy, amorphous silicon, amorphous germanium, amorphous silicon-germanium, amorphous carbon, silicon carbide, aluminum oxide, silicon nitride, or silicon carbonitride, and the thickness of the hermetic release barrier layer 17 is equal to or greater than 100A and equal to or less than 2000A. Specifically, silicon, germanium, a silicon-germanium alloy, amorphous silicon, amorphous germanium, amorphous silicon-germanium, amorphous carbon, silicon carbide, aluminum oxide, silicon nitride, and silicon carbonitride are all CMOS process corrosion resistant materials, i.e., these materials are not corroded by the sacrificial layer release agent, so the hermetic release barrier layer 17 can be used to protect the CMOS measurement circuitry 1 from corrosion when the corrosion process is performed to release the sacrificial layer. In addition, the closed release isolation layer 17 covers the CMOS measurement circuit system 1, and the closed release isolation layer 17 can also be used for protecting the CMOS measurement circuit system 1 from being influenced by the process in the etching process of manufacturing the CMOS infrared sensing structure 2. In addition, when at least one layer of airtight release isolation layer 17 is arranged on the reflection layer 3, the material for forming the airtight release isolation layer 17 is arranged to include at least one of silicon, germanium, silicon-germanium alloy, amorphous silicon, amorphous germanium, amorphous silicon-germanium, amorphous carbon, silicon carbide, aluminum oxide, silicon nitride or silicon carbonitride, the thickness of the first dielectric layer is greater than 100A and less than or equal to 2000A, when the airtight release isolation layer 17 is arranged to improve the stability of the first columnar structure 5, the airtight release isolation layer 17 hardly influences the reflection process in the resonant cavity, the influence of the airtight release isolation layer 17 on the reflection process of the resonant cavity can be avoided, and further the influence of the airtight release isolation layer 17 on the detection sensitivity of the infrared detector is avoided.

With reference to fig. 1 to 5, a CMOS fabrication process of the CMOS infrared sensing structure 2 includes a metal interconnection process, a via process and an RDL process, the CMOS infrared sensing structure 2 includes at least two metal interconnection layers, at least two dielectric layers and a plurality of interconnection vias, the dielectric layers include at least one sacrificial layer and one heat-sensitive dielectric layer, the heat-sensitive dielectric layer includes at least a thermal-sensitive layer 11, and may further include a supporting layer 18 and/or a passivation layer 20, and the metal interconnection layers include at least a reflective layer 3 and an electrode layer 19; the thermal sensitive medium layer comprises a thermal sensitive material with a resistance temperature coefficient larger than a set value, the resistance temperature coefficient can be larger than or equal to 0.015/K, for example, the thermal sensitive material with the resistance temperature coefficient larger than the set value forms a thermal sensitive layer 11 in the thermal sensitive medium layer, the thermal sensitive medium layer is used for converting temperature change corresponding to infrared radiation absorbed by the thermal sensitive medium layer into resistance change, and further converting an infrared target signal into a signal capable of realizing electric reading through the CMOS measuring circuit system 1.

Specifically, the metal interconnection process is used for realizing the electrical connection of an upper metal interconnection layer and a lower metal interconnection layer, the through hole process is used for forming an interconnection through hole for connecting the upper metal interconnection layer and the lower metal interconnection layer, the RDL process is a rewiring layer process, specifically, a layer of metal is re-distributed above the top metal of the circuit and is electrically connected with the top metal of the circuit through a tungsten column, the reflection layer 3 in the infrared detector can be prepared on the top metal of the CMOS measurement circuit system 1 through the RDL process, and the support base 8 on the reflection layer 3 is electrically connected with the top metal of the CMOS measurement circuit system 1. In addition, the heat-sensitive dielectric layer comprises a heat-sensitive material with a resistance temperature coefficient larger than a set value, and the resistance temperature coefficient can be larger than or equal to 0.015/K, so that the detection sensitivity of the infrared detector can be improved.

Fig. 6 is a schematic cross-sectional view of another infrared detector provided in the embodiments of the present disclosure. As shown in fig. 6, on the basis of the above embodiment, the CMOS manufacturing process of the CMOS measurement circuit system 1 may also include a metal interconnection process and a via process, the CMOS measurement circuit system 1 includes metal interconnection layers 101, dielectric layers 102 and a silicon substrate 103 at the bottom, the upper and lower metal interconnection layers 101 are electrically connected through vias 104,

with reference to fig. 1 to 6, the CMOS infrared sensing structure 2 includes a resonant cavity formed by a reflective layer 3 and a heat sensitive dielectric layer, a suspended microbridge structure for controlling heat transfer, and a columnar structure having electrical connection and support functions, the columnar structure includes a first columnar structure 5 and a second columnar structure 6, and the CMOS measurement circuit system 1 is configured to measure and process an array resistance value formed by one or more CMOS infrared sensing structures 2, and convert an infrared signal into an image electrical signal.

Specifically, the resonant cavity may be formed by a cavity between the reflective layer 3 and the absorbing plate 9, for example, the infrared light is reflected back and forth in the resonant cavity through the absorbing plate 9, so as to improve the detection sensitivity of the infrared detector, and due to the arrangement of the first columnar structure 5 and the second columnar structure 6, the beam structure 10 and the absorbing plate 9 form a suspension micro-bridge structure for controlling the heat transfer, and the first columnar structure 5 and the second columnar structure 6 are electrically connected to the supporting base 8 and the corresponding beam structure 10, and are used for supporting the infrared conversion structure 4 on the second columnar structure 6.

Fig. 7 is a schematic structural diagram of a CMOS measurement circuit system according to an embodiment of the present disclosure. With reference to fig. 1 to fig. 7, the CMOS measurement circuit system 1 includes a bias voltage generation circuit 701, a column-level analog front-end circuit 801 and a row-level circuit 901, an input terminal of the bias voltage generation circuit 701 is connected to an output terminal of the row-level circuit 901, an input terminal of the column-level analog front-end circuit 801 is connected to an output terminal of the bias voltage generation circuit 701, the row-level circuit 901 includes a row-level mirror image element Rsm and a row selection switch K1, and the column-level analog front-end circuit 801 includes a blind image element RD; the row-level circuit 901 is distributed in each pixel, selects a signal to be processed according to a row strobe signal of the timing generation circuit, and outputs a current signal to the column-level analog front-end circuit 801 under the action of the bias generation circuit 701 to perform current-voltage conversion output; the row stage circuit 901 outputs a third bias voltage VRsm to the bias generation circuit 701 when being controlled by the row selection switch K1 to be gated, the bias generation circuit 701 outputs a first bias voltage V1 and a second bias voltage V2 according to the input constant voltage and the third bias voltage VRsm, and the column stage analog front-end circuit 801 obtains two currents according to the first bias voltage V1 and the second bias voltage V2, performs transimpedance amplification on the difference between the two generated currents, and outputs the amplified current as an output voltage.

Specifically, the row-level circuit 901 includes a row-level mirror image element Rsm and a row selection switch K1, and the row-level circuit 901 is configured to generate a third bias voltage VRsm according to a gating state of the row selection switch K1. For example, the row-level image elements Rsm may be subjected to a shading process such that the row-level image elements Rsm are subjected to a fixed radiation by a shading sheet having a temperature constantly equal to a substrate temperature, the row selection switch K1 may be implemented by a transistor, the row selection switch K1 is closed, and the row-level image elements Rsm are connected to the bias generation circuit 701, that is, the row-level circuit 901 outputs the third bias voltage VRsm to the bias generation circuit 701 when being gated by the row selection switch K1. The bias generation circuit 701 may include a first bias generation circuit 71 and a second bias generation circuit 72, the first bias generation circuit 71 being configured to generate a first bias voltage V1 according to an input constant voltage, which may be, for example, a positive power supply signal with a constant voltage. The second bias generating circuit 72 may include a bias control sub-circuit 721 and a plurality of gate driving sub-circuits 722, the bias control sub-circuit 721 controlling the gate driving sub-circuits 722 to generate the corresponding second bias voltages V, respectively, according to the third bias voltage VRsm.

The column-level analog front-end circuit 801 includes a plurality of column control sub-circuits 81, the column control sub-circuits 81 are disposed corresponding to the gate driving sub-circuits 722, and exemplarily, the column control sub-circuits 81 may be disposed corresponding to the gate driving sub-circuits 722 in a one-to-one manner, and the gate driving sub-circuits 722 are configured to provide the second bias voltage V2 to the corresponding column control sub-circuits 81 according to their own gate states. For example, it may be set that when the gate driving sub-circuit 722 is gated, the gate driving sub-circuit 722 supplies the second bias voltage V2 to the corresponding column control sub-circuit 81; when the gate driving sub-circuit 722 is not gated, the gate driving sub-circuit 722 stops supplying the second bias voltage V2 to the corresponding column control sub-circuit 81.

The column-level analog front-end circuit 801 comprises an effective pixel RS and a blind pixel RD, the column control sub-circuit is used for generating a first current I1 according to a first bias voltage V1 and the blind pixel RD, generating a second current I2 according to a second bias voltage V2 and the effective pixel RS, performing transimpedance amplification on a difference value between the first current I1 and the second current I2, and outputting the difference value, and the row-level mirror image pixel Rsm and the effective pixel RS have the same temperature drift amount at the same ambient temperature.

Illustratively, the row-level image elements Rsm are thermally insulated from the CMOS measurement circuitry 1 and are shaded, and the row-level image elements Rsm are subjected to a fixed radiation from a shade sheet having a temperature constantly equal to the substrate temperature. The absorption plate 9 of the active pixel RS is thermally insulated from the CMOS measurement circuitry 1 and the active pixel RS receives external radiation. The absorbing plates 9 of the row-level mirror image elements Rsm and the effective elements RS are thermally insulated from the CMOS measuring circuit system 1, so that the row-level mirror image elements Rsm and the effective elements RS have a self-heating effect.

When the corresponding row-level mirror image element Rsm is gated through the row selection switch K1, the resistance value of the row-level mirror image element Rsm and the resistance value of the effective element RS are changed due to joule heat, but when the row-level mirror image element Rsm and the effective element RS are subjected to the same fixed radiation, the resistance value of the row-level mirror image element Rsm and the resistance value of the effective element RS are the same, the temperature coefficients of the row-level mirror image element Rsm and the temperature coefficient of the effective element RS are the same, the temperature drift amounts of the row-level mirror image element Rsm and the effective element RS are the same at the same ambient temperature, the change of the row-level mirror image element Rsm and the temperature drift amounts of the effective element RS at the same ambient temperature are synchronized, the resistance value change of the row-level mirror image element Rsm and the effective element RS due to the self-heating effect is effectively compensated, and the stable output of the reading circuit is achieved.

In addition, by arranging the second bias generating circuit 701 to include a bias control sub-circuit 721 and a plurality of gate driving sub-circuits 722, the bias control sub-circuit 721 is configured to control the gate driving sub-circuits 722 to generate corresponding second bias voltages V2 respectively according to the row control signal, so that each row of pixels has one path to drive the whole columns of pixels of the row individually, the requirement for the second bias voltage V2 is reduced, that is, the driving capability of the bias generating circuit 701 is improved, and the readout circuit is advantageously used for driving a larger-scale infrared detector pixel array. In addition, the specific detailed operation principle of the CMOS measurement circuit system 1 is well known to those skilled in the art and will not be described herein.

Alternatively, the CMOS infrared sensing structure 2 may be disposed on a metal interconnect layer of the CMOS measurement circuitry 1 or fabricated on the same layer. Specifically, the metal interconnection layer of the CMOS measurement circuitry 1 may be a top metal layer in the CMOS measurement circuitry 1, and in conjunction with fig. 1 to 7, the CMOS infrared sensing structure 2 may be fabricated on the metal interconnection layer of the CMOS measurement circuitry 1, and the CMOS infrared sensing structure 2 is electrically connected to the CMOS measurement circuitry 1 through a supporting base 8 on the metal interconnection layer of the CMOS measurement circuitry 1, so as to transmit an electrical signal converted by an infrared signal to the CMOS measurement circuitry 1.

Fig. 8 is a schematic cross-sectional structure view of another infrared detector provided in the embodiment of the present disclosure, and as shown in fig. 8, a CMOS infrared sensing structure 2 is prepared on the same layer of a metal interconnection layer of a CMOS measurement circuit system 1, that is, the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 are arranged on the same layer, as shown in fig. 8, the CMOS infrared sensing structure 2 is arranged on one side of the CMOS measurement circuit system 1, and a hermetic release isolation layer 17 may also be arranged on the top of the CMOS measurement circuit system 1 to protect the CMOS measurement circuit system 1.

Alternatively, referring to fig. 1 to 8, the CMOS infrared sensing structure 2 includes an absorption plate 9, a beam structure 10, a reflection layer 3, a first pillar structure 5 and a second pillar structure 6, the absorption plate 9 includes a metal interconnection layer and at least one thermal sensitive medium layer, the material of the thermal sensitive medium layer includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, titanium oxide, vanadium oxide or vanadium titanium oxide, the metal interconnection layer of the absorption plate 9 is an electrode layer 19 of the absorption plate 9 for transmitting the electrical signal converted from the infrared signal, the thermal sensitive medium layer includes at least a thermal sensitive layer 11 and may further include a supporting layer 18 and a passivation layer 20, the material of the thermal sensitive medium layer includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, titanium oxide, vanadium oxide or vanadium titanium oxide, that is, the material constituting the thermosensitive layer 11 includes at least one of amorphous silicon, amorphous germanium, amorphous silicon-germanium, titanium oxide, vanadium oxide, or titanium vanadium oxide.

The beam structure 10, the first columnar structure 5 and the second columnar structure 6 are used for transmitting electrical signals and for supporting and connecting the absorption plate 9, the electrode layer 19 in the absorption plate 9 includes two patterned electrode structures, the two patterned electrode structures output positive electrical signals and ground electrical signals respectively, the positive electrical signals and the ground electrical signals are transmitted to the supporting base electrically connected with the columnar structures through the different beam structures 10 and the different columnar structures and then transmitted to the CMOS measurement circuit system 1, the beam structure 10 includes a metal interconnection layer and at least one dielectric layer, the metal interconnection layer in the beam structure 10 is the electrode layer 19 in the beam structure 10, the electrode layer 19 in the beam structure 10 is electrically connected with the electrode layer 19 in the absorption plate 9, and the dielectric layer in the beam structure 10 may include a supporting layer 18 and a passivation layer 20.

The first columnar structure 5 and the second columnar structure 6 are connected with the beam structure 10 and the CMOS measuring circuit system 1 by adopting a metal interconnection process and a through hole process, the upper part of the second columnar structure 6 needs to be electrically connected with an electrode layer 19 in the beam structure 10 through a through hole penetrating through a supporting layer 18 in the beam structure 10, and the lower part of the first columnar structure 5 needs to be electrically connected with a corresponding supporting base 8 through a through hole penetrating through a dielectric layer on the supporting base 8. The reflecting plate 7 is used for reflecting infrared signals and forms a resonant cavity with the heat-sensitive medium layer, namely the reflecting plate 7 is used for reflecting infrared signals and forms a resonant cavity with the heat-sensitive medium layer in the heat-sensitive medium layer, and the reflecting layer 3 comprises at least one metal interconnection layer which is used for forming a supporting base 8 and is also used for forming the reflecting plate 7.

Alternatively, it is possible to provide that at least two ends of the beam structure 10 and the absorber plate 9 are electrically connected, the CMOS infrared sensing structure 2 includes at least two columnar structures, one columnar structure includes the first columnar structure 5 and the second columnar structure 6, and at least two supporting bases 8, and the electrode layer 19 includes at least two electrode terminals. Specifically, as shown in fig. 1, the beam structures 10 are electrically connected to two ends of the absorption plate 9, each beam structure 10 is electrically connected to one end of the absorption plate 9, the CMOS infrared sensing structure 2 includes two columnar structures, the electrode layer 19 includes at least two electrode terminals, at least a portion of the electrode terminals transmit positive electrical signals, at least a portion of the electrode terminals transmit negative electrical signals, and the signals are transmitted to the supporting base 8 through the corresponding beam structures 10 and the columnar structures.

Fig. 9 is a schematic perspective view of another infrared detector provided in the embodiments of the present disclosure. As shown in fig. 9, it is also possible to provide beam structures 10 electrically connected to four ends of the absorber plate 9, each beam structure 10 electrically connected to two ends of the absorber plate 9, the CMOS infrared sensing structure 2 includes four pillar structures, one pillar structure includes the first pillar structure 5 and the second pillar structure 6, and one beam structure 10 connects the two pillar structures. It should be noted that, in the embodiment of the present disclosure, the number of the connecting ends of the beam structure 10 and the absorbing plate 9 is not specifically limited, and it is sufficient that the beam structure 10 and the electrode terminal are respectively present, and the beam structure 10 is used for transmitting the electrical signal output by the corresponding electrode terminal.

Alternatively, the infrared detector may be configured based on a 3nm, 7nm, 10nm, 14nm, 22nm, 28nm, 32nm, 45nm, 65nm, 90nm, 130nm, 150nm, 180nm, 250nm or 350nm CMOS process, which characterizes process nodes of the integrated circuit, i.e., features during the processing of the integrated circuit.

Alternatively, the metal wiring material constituting the metal interconnection layer in the infrared detector may be configured to include at least one of aluminum, copper, tungsten, titanium, nickel, chromium, platinum, silver, ruthenium, or cobalt, and for example, the material constituting the reflective layer may be configured to include at least one of aluminum, copper, tungsten, titanium, nickel, chromium, platinum, silver, ruthenium, or cobalt. In addition, both the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 are prepared by using a CMOS process, and the CMOS infrared sensing structure 2 is directly prepared on the CMOS measurement circuit system 1, so that the radial side length of the columnar structure can be greater than or equal to 0.5um and less than or equal to 3um, for example, the radial side length of the first columnar structure 5 is greater than or equal to 0.5um and less than or equal to 3um, the radial side length of the second columnar structure 6 is greater than or equal to 0.5um and less than or equal to 3um, the width of the beam structure 10, that is, the width of a single line in the beam structure 10 is less than or equal to 0.3um, the height of the resonant cavity is greater than or equal to 1.5um and less than or equal to 2.5um, and the side length of a single pixel in the CMOS infrared sensing structure 2 is greater than or equal to 6um and less than or equal to 17 um.

The embodiment of the disclosure also provides a method for manufacturing an infrared detector based on a CMOS process, and fig. 10 is a schematic flow chart of the method for manufacturing an infrared detector provided by the embodiment of the disclosure. The method of manufacturing the infrared detector may be used to manufacture the infrared detector as in the above embodiments. As shown in fig. 10, the method for manufacturing the infrared detector based on the CMOS process includes:

and S110, forming a reflecting layer on the CMOS measuring circuit system.

As shown in fig. 11 and 12, a CMOS measurement circuit system 1 is provided, an entire reflection layer 3 is formed on the CMOS measurement circuit system 1, a material constituting the reflection layer 3 may be, for example, aluminum, the entire reflection layer 3 is etched to form a reflection plate 7 and a support base 8, a fourth dielectric layer 21 is formed on the reflection layer 3, and the fourth dielectric layer 21 is processed by a CMP process, the material constituting the fourth dielectric layer 21 may be, for example, silicon oxide, and a polishing termination interface of the CMP process for the fourth dielectric layer 21 is flush with a surface of the reflection layer 3 away from the CMOS measurement circuit system 1, that is, an upper surface of the fourth dielectric layer 21 is polished flush with an upper surface of the reflection layer 3. Therefore, the surface planarization of the patterned medium structure, the reflecting plate 7 and the supporting base 8 is effectively realized, the preparation difficulty of subsequent films can be reduced, and the planarization degree of the whole infrared detector is favorably optimized. In addition, the fourth dielectric layer 21, the reflector 7 and the supporting base 8 are reasonably matched, so that the CMOS measuring circuit system 1 can be well protected. Illustratively, the material constituting the fourth dielectric layer 21 may be configured to include at least one of silicon, germanium, a silicon-germanium alloy, amorphous silicon, amorphous germanium, amorphous silicon-germanium, amorphous carbon, silicon carbide, aluminum oxide, silicon carbonitride or silicon nitride, and the thickness of the fourth dielectric layer 21 may be greater than or equal to 1000A and less than or equal to 10000A.

As shown in fig. 13, after depositing the fourth dielectric layer 21 and processing the fourth dielectric layer 21 by using a CMP process, at least one protective dielectric layer 22 is formed on the reflective layer 3, and the protective dielectric layer 22 is etched to form a through hole corresponding to the position of the support base 8, where at least a portion of the support base 8 is exposed by the through hole, the protective dielectric layer 22 may be, for example, silicon nitride, and the thickness of the through hole may be, for example, 1000A, and the protective dielectric layer 22 can effectively protect the reflective layer 3 and the fourth dielectric layer 21 from external water oxygen or a reagent for releasing a sacrificial layer. In addition, the fourth dielectric layer 21 also plays a role of electrical insulation, which can effectively prevent the first columnar structure 5 and the reflector 7 from being electrically connected, and the fourth dielectric layer 21 also plays a role of isolation, which is used as an etching stop interface of the first columnar structure 5.

And S120, forming a first columnar structure on the reflecting layer.

As shown in fig. 14, the first columnar structure 5 may be formed on the reflective layer 3, for example, the first columnar structure 5 may be formed on the protective dielectric layer 22 shown in fig. 13, the material constituting the first columnar structure 5 may be, for example, aluminum, and the cross section of the first columnar structure 5 has a regular trapezoid shape.

As shown in fig. 15, after the first columnar structure 5 is formed on the reflective layer 3, an entire first dielectric layer 15 is formed, for example, the entire first dielectric layer 15 may be formed above the first columnar structure 5, the material constituting the first dielectric layer 15 may be, for example, silicon carbide, the first dielectric layer 15 covers the side surface of the first columnar structure 5 and covers the CMOS measurement circuit system 1, so that the first columnar structure 5 and the CMOS measurement circuit system 1 are effectively protected, and the first columnar structure 5 and the CMOS measurement circuit system 1 are not affected by water and oxygen in the external environment and are not affected by a reagent for releasing a sacrificial layer.

As shown in fig. 16, at least one layer of hermetic release insulating layer 17 is formed on the first dielectric layer 15, and the first dielectric layer 15 and the hermetic release insulating layer 17 are processed by using a CMP process, and a polishing termination interface of the CMP process for the first dielectric layer 15 and the hermetic release insulating layer 17 is flush with a surface of the first columnar structure 5 away from the CMOS measurement circuit system 1, that is, the first dielectric layer 15 and the hermetic release insulating layer 17 are polished by using the CMP process, so that an upper surface of the first columnar structure 5 is exposed after polishing, and preparation is made for subsequently realizing electrical contact between the second columnar structure 6 and the first columnar structure 5. In addition, utilize airtight release insulating layer 17 to strengthen the support intensity of first columnar structure 5 department, improved the mechanical stability of first columnar structure 5, airtight release insulating layer 17 has occupied a part space between reflector layer 3 and infrared conversion structure 4, has occupied the space that sets up of sacrificial layer promptly, is favorable to reducing the resonant cavity height between reflector layer 3 and the infrared conversion structure 4, and then reduces the thickness of sacrificial layer, has reduced the release degree of difficulty of sacrificial layer.

Illustratively, the material forming the hermetic release isolation layer may include at least one of silicon, germanium, silicon germanium, amorphous silicon, amorphous germanium or amorphous silicon germanium, the thickness of the hermetic release isolation layer 17 is greater than or equal to 0.5 micrometers and less than or equal to 2 micrometers, so that when the hermetic release isolation layer 17 is arranged to improve the stability of the first columnar structure 5, the hermetic release isolation layer 17 hardly affects the reflection process in the resonant cavity, that is, the hermetic release isolation layer 17 may be effectively prevented from affecting the reflection process of the resonant cavity, and further, the influence of the hermetic release isolation layer 7 on the detection sensitivity of the CMOS infrared sensing structure 2 is prevented.

S130, forming a sacrificial layer on the reflecting layer; wherein the material constituting the sacrificial layer includes silicon oxide.

As shown in fig. 17, the sacrifice layer 23 may be formed on the reflection layer 3, and the sacrifice layer 23 may be formed on the hermetic release barrier layer 17.

S140, etching the sacrificial layer to form a first through hole corresponding to the position of the first columnar structure; wherein, the first through hole exposes at least part of the first columnar structure.

As shown in fig. 17, the sacrificial layer 23 is etched to form a first via corresponding to the position of the first pillar structure 5, and the first via exposes at least a portion of the first pillar structure 5, so as to prepare for the subsequent electrical contact between the second pillar structure 6 and the first pillar structure 5.

And S150, forming a second columnar structure in the first through hole.

As shown in fig. 18, the second columnar structure 6 is formed in the first via hole, and the entire second dielectric layer 16 may be formed first and the second dielectric layer 16 may be etched to form a second via hole corresponding to the position of the first columnar structure 5, where at least a portion of the first columnar structure 5 is exposed by the second via hole, so as to prepare for subsequently achieving electrical contact between the second columnar structure 6 and the first columnar structure 5. Specifically, the second dielectric layer 16 covers at least the side surface of the second columnar structure 6, the material forming the second dielectric layer 16 may be, for example, amorphous carbon or alumina, and the second dielectric layer 16 covers at least the side surface of the second columnar structure 6, so that the second columnar structure 6 is effectively protected, and the second columnar structure 6 is not affected by water and oxygen in the external environment, and is not affected by the reagent for releasing the sacrificial layer.

As shown in fig. 19, an entire adhesion layer 14 is formed on the second dielectric layer 16, the adhesion layer 14 covers the contact surfaces of the first pillar structure 5 and the second pillar structure 6, and the material constituting the adhesion layer 14 includes at least one of titanium, titanium nitride, tantalum or tantalum nitride, so as to optimize the electrical contact effect between the first pillar structure 5 and the second pillar structure 6.

As shown in fig. 20, a metal layer is formed on the whole surface, the metal layer fills the second through hole, and then the metal layer, the adhesion layer 14 and the second dielectric layer 16 are processed by a CMP process, a polishing termination interface of the CMP process for the metal layer, the adhesion layer 14 and the second dielectric layer 16 is flush with the surface of the sacrificial layer away from the CMOS measurement circuit system 1, that is, CMP polishing is performed until the upper surface of the sacrificial layer 23 is exposed, and the metal layer located in the second through hole forms the second columnar structure 6. Illustratively, the material constituting the metal layer may be, for example, tungsten, that is, the material constituting the second columnar structure 6 may be tungsten.

And S160, forming an infrared conversion structure above the sacrificial layer.

As shown in fig. 21, the infrared conversion structure 4 is formed above the sacrificial layer 23, the support layer 18 may be formed on the sacrificial layer 23, and the support layer 18 disposed at a position corresponding to the position of the second columnar structure 6 may be etched to form a through hole exposing the upper surface of the second columnar structure 6.

As shown in fig. 22, the entire electrode layer 19 is formed on the support layer 18, the electrode layer 19 is etched to form a patterned electrode structure, the patterned electrode structure corresponding to the position of the absorption plate 9 includes two patterned electrode structures for transmitting positive and negative signals, respectively, and the patterned electrode structure corresponding to the shape of the beam structure 10 is formed at the same time, and the patterned electrode structure is electrically connected to the corresponding second columnar structure 6 through a through hole corresponding to the upper surface of the second columnar structure 6.

As shown in fig. 23, the entire surface of the thermosensitive layer 11 is formed on the electrode layer, and as shown in fig. 24, the entire surface of the passivation layer 20 is formed on the thermosensitive layer 11.

And S170, forming a reinforcing structure.

As shown in fig. 25, the reinforcing structure 12 may be formed by forming a whole reinforcing layer on the infrared conversion structure 4, etching the reinforcing layer to form the reinforcing structure 12, and the reinforcing structure 12 includes the weight block structure 13. Alternatively, referring to fig. 3, forming the reinforcing structure 12 may be forming a through hole at a position where the infrared conversion structure 4 corresponds to the second columnar structure 6, the through hole exposing at least a portion of the second columnar structure 6, forming a reinforcing layer on the infrared conversion structure 4 over the entire surface, etching the reinforcing layer to form the reinforcing structure 12, the reinforcing structure 12 including a weighted block-shaped structure 13, the weighted block-shaped structure 13 including a first portion filling the through hole and a second portion located outside the through hole, an orthographic projection of the second portion covering an orthographic projection of the first portion.

As shown in fig. 26, the passivation layer 20, the thermal sensitive layer 11 and the support layer 18 are etched, so that the thermal sensitive layer 11 and the electrode layer 19 are located in a sealed space formed by the support layer 18 and the passivation layer 20 corresponding to the absorption plate 9, and the thermal sensitive layer 11 and the electrode layer 19 in the absorption plate 9 are protected, and the thermal sensitive layer 11 and the electrode layer 19 are located in a sealed space formed by the support layer 18 and the passivation layer 20 corresponding to the beam structure 10, and the thermal sensitive layer 11 and the electrode layer 19 in the beam structure 10 are protected.

As shown in fig. 2, after forming the reinforcing structure 12, a sacrificial release layer 23 is further included to form a final infrared detector product, and the sacrificial layer 23 may be made of silicon oxide, for example, at least one of gaseous hydrogen fluoride, carbon tetrafluoride and trifluoromethane may be used as a sacrificial release layer.

It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The foregoing are merely exemplary embodiments of the present disclosure, which enable those skilled in the art to understand or practice the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An infrared detector based on a CMOS process, comprising:

2. The CMOS process-based infrared detector according to claim 1, wherein the reinforcing structure comprises a weighted block structure located on a side of the infrared conversion structure remote from the CMOS measurement circuitry and the weighted block structure is disposed in contact with the infrared conversion structure.

3. The CMOS process-based infrared detector according to claim 2, wherein a material constituting the weighted bulk structure includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon, silicon carbide, aluminum oxide, aluminum, copper, tungsten, gold, platinum, nickel, chromium, titanium tungsten alloy, nickel chromium alloy, nickel platinum alloy, or nickel silicon alloy.

4. The CMOS process-based infrared detector as claimed in claim 1, wherein a through hole is formed in the position of the infrared conversion structure corresponding to the second columnar structure, and at least part of the second columnar structure is exposed through the through hole;

5. The CMOS process based infrared detector of claim 4, wherein said weighted block structure is comprised of a material comprising at least one of aluminum, copper, tungsten, gold, platinum, nickel, chromium, titanium tungsten alloy, nickel chromium alloy, nickel platinum alloy or nickel silicon alloy.

6. The CMOS process-based infrared detector according to claim 1, wherein a material constituting the first columnar structure comprises aluminum and a material constituting the second columnar structure comprises tungsten.

7. The CMOS process-based infrared detector according to claim 1, wherein the CMOS infrared sensing structure further comprises an adhesion layer covering at least contact surfaces of the first pillar structure and the second pillar structure.

8. The CMOS process-based infrared detector according to claim 1, wherein the CMOS infrared sensing structure further comprises a first dielectric layer covering at least a side surface of the first pillar structure;

9. The infrared detector based on the CMOS process as claimed in claim 1, wherein a sacrificial layer in the infrared detector is used for enabling the CMOS infrared sensing structure to form a hollow structure, the material forming the sacrificial layer is silicon oxide, and the sacrificial layer is etched by a post-CMOS process;

10. A method for manufacturing an infrared detector based on a CMOS process, which is used for manufacturing the infrared detector based on a CMOS process according to any one of claims 1 to 9, the method for manufacturing the infrared detector based on a CMOS process comprising:

forming the reflective layer on the CMOS measurement circuitry;

forming the first columnar structure on the reflective layer;

forming the second columnar structure in the first through hole;

forming the infrared conversion structure on the sacrificial layer;

forming the reinforcing structure.

11. The method of claim 10, further comprising, before forming the first pillar structure on the reflective layer:

forming a whole layer of reflecting layer on the CMOS measuring circuit system;

12. The method of claim 10, wherein forming the second pillar structure within the first via comprises:

forming a whole adhesive layer;

forming a whole metal layer; wherein the metal layer fills the second via;

13. The method of claim 10, wherein forming the reinforcing structure comprises:

forming a whole reinforcing layer on the infrared conversion structure;

alternatively, forming the reinforcing structure comprises:

forming a whole reinforcing layer on the infrared conversion structure;

14. The method for manufacturing an infrared detector based on a CMOS process according to claim 10, further comprising, after forming the reinforcing structure:

and releasing the sacrificial layer.