CN113720483A

CN113720483A - Infrared detector pixel and infrared detector based on CMOS (complementary metal oxide semiconductor) process

Info

Publication number: CN113720483A
Application number: CN202110324096.7A
Authority: CN
Inventors: 翟光杰; 武佩; 潘辉; 翟光强
Original assignee: Beijing North Gaoye Technology Co ltd
Current assignee: Beijing North Gaoye Technology Co ltd
Priority date: 2021-03-26
Filing date: 2021-03-26
Publication date: 2021-11-30
Anticipated expiration: 2041-03-26
Also published as: CN113720483B

Abstract

The present disclosure relates to an infrared detector pixel and an infrared detector based on a CMOS process, including: the CMOS measuring circuit system and the CMOS infrared sensing structure on the CMOS measuring circuit system are prepared by adopting a full CMOS process; the CMOS infrared sensing structure comprises a reflecting layer, an infrared conversion structure, a plurality of columnar structures, a medium protective layer and an etching barrier layer, wherein the medium protective layer and the etching barrier layer are positioned on the reflecting layer; the columnar structure comprises at least two layers of stand columns which are arranged in an overlapping mode and located between the reflecting layer and the infrared conversion structure, the reflecting layer comprises a reflecting plate and a supporting base, and the infrared conversion structure is electrically connected with the CMOS measuring circuit system through the columnar structure and the supporting base; each layer of upright column can be at least one of a solid metal column, a non-metal solid column or a hollow column; the dielectric protection layer surrounds the side face of the columnar structure, and the etching barrier layer at least covers the corner position of the dielectric protection layer. Therefore, the problems of low performance, low pixel scale, low yield and the like of the traditional MEMS process infrared detector are solved; and the detection sensitivity and the structural stability are improved.

Description

Infrared detector pixel and infrared detector based on CMOS (complementary metal oxide semiconductor) process

Technical Field

The disclosure relates to the technical field of infrared detection, in particular to an infrared detector pixel and an infrared detector based on a CMOS (complementary metal oxide semiconductor) process.

Background

The fields of monitoring markets, vehicle and auxiliary markets, home markets, intelligent manufacturing markets, mobile phone applications and the like have strong demands on uncooled high-performance chips, certain requirements are provided for the performance of the chips, the performance consistency and the product price, the potential demands of more than one hundred million chips are expected every year, and the current process scheme and architecture cannot meet the market demands.

At present, an infrared detector adopts a mode of combining a measuring circuit and an infrared sensing structure, the measuring circuit is prepared by adopting a Complementary Metal-Oxide-Semiconductor (CMOS) process, and the infrared sensing structure is prepared by adopting a Micro-Electro-Mechanical System (MEMS) process, so that the following problems are caused:

(1) the infrared sensing structure is prepared by adopting an MEMS (micro-electromechanical systems) process, polyimide is used as a sacrificial layer, and the infrared sensing structure is incompatible with a CMOS (complementary metal oxide semiconductor) process.

(2) Polyimide is used as a sacrificial layer, so that the problem that the vacuum degree of a detector chip is influenced due to incomplete release exists, the growth temperature of a subsequent film is limited, and the selection of materials is not facilitated.

(3) Polyimide can cause the height of the resonant cavity to be inconsistent, and the working dominant wavelength is difficult to guarantee.

(4) The control of the MEMS process is far worse than that of the CMOS process, and the performance consistency and the detection performance of the chip are restricted.

(5) MEMS has low productivity, low yield and high cost, and can not realize large-scale batch production.

(6) The existing process capability of the MEMS is not enough to support the preparation of a detector with higher performance, and the MEMS has smaller line width and thinner film thickness, thereby being not beneficial to realizing the miniaturization of a chip.

Meanwhile, the detection sensitivity is low, and the structural stability is poor.

Disclosure of Invention

In order to solve the technical problem or at least partially solve the technical problem, the present disclosure provides an infrared detector pixel and an infrared detector, which solve the problems of low performance, low pixel scale, low yield and the like of the conventional MEMS process infrared detector, improve the detection sensitivity, and improve the structural stability.

The present disclosure provides an infrared detector pixel, which includes:

the CMOS infrared sensing device comprises a CMOS measuring circuit system and a CMOS infrared sensing structure positioned on the CMOS measuring circuit system, wherein the CMOS measuring circuit system and the CMOS infrared sensing structure are both prepared by adopting a CMOS process, and the CMOS infrared sensing structure is directly prepared on the CMOS measuring circuit system;

The CMOS measurement circuit system comprises at least one layer of closed release isolation layer above the CMOS measurement circuit system, wherein the closed release isolation layer is used for protecting the CMOS measurement circuit system from being influenced by a process in the etching process of manufacturing the CMOS infrared sensing structure;

the CMOS manufacturing process of the CMOS infrared sensing structure comprises a metal interconnection process, a through hole process and an RDL (remote data link) process, wherein the CMOS infrared sensing structure comprises at least two metal layers, at least two dielectric layers and a plurality of interconnection through holes;

the CMOS infrared sensing structure comprises a reflecting layer, an infrared conversion structure and a plurality of columnar structures, wherein the reflecting layer, the infrared conversion structure and the columnar structures are positioned on the CMOS measuring circuit system;

the columnar structure comprises at least two layers of upright posts which are arranged in an overlapping mode; each layer of the upright column can be at least one of a solid metal column, a non-metal solid column or a hollow column, and the material for forming the side wall of the non-metal solid column and the material for forming the side wall of the hollow column both comprise metal;

The CMOS infrared sensing structure also comprises a medium protective layer and an etching barrier layer which are positioned on the reflecting layer; the dielectric protection layer surrounds the side face of the columnar structure, and the etching barrier layer at least covers the corner position of the dielectric protection layer.

In some embodiments, the CMOS infrared sensing structure comprises a sacrificial layer, the sacrificial layer is used for enabling the CMOS infrared sensing structure to form a hollow structure, the material forming the sacrificial layer is silicon oxide, and the sacrificial layer is etched by a post-CMOS process;

the post-CMOS process etches the sacrificial layer using at least one of gaseous hydrogen fluoride, carbon tetrafluoride, and trifluoromethane.

In some embodiments, the etch stop layer comprises a side layer and a planar layer disposed adjacent to each other, the planar layer being disposed in a ring shape, the side layer being disposed in a barrel shape;

the side surface layer of the etching barrier layer covers the side surface of the dielectric protection layer facing the columnar structure, and the plane layer of the etching barrier layer surrounds the columnar structure and covers the surface of the dielectric protection layer adjacent to the side surface.

In some embodiments, a corresponding dielectric protective layer is provided corresponding to each layer of pillars; the etching barrier layer is at least arranged at the corner position of the uppermost dielectric protection layer.

In some embodiments, the shape and size of each etch stop layer in the same layer are the same.

In some embodiments, when the etching barrier layer is at least two layers, the shape and size of the etching barrier layer at each different layer are the same; or

The size of the etching barrier layer positioned on the upper layer is different from that of the etching barrier layer positioned on the lower layer.

In some embodiments, the planar layer comprises discretely disposed bulk structures;

the projection of the block structures of the plane layers on the reflecting layer along the axial direction of the columnar structure is overlapped and surrounds the columnar structure.

In some embodiments, the material comprising the etch stop layer comprises at least one of a metallic material or a dielectric material;

the metal material comprises at least one of aluminum, copper, tungsten or titanium-tungsten alloy;

the dielectric material comprises at least one of amorphous silicon, amorphous germanium, amorphous silicon, silicon carbide or aluminum oxide.

In some embodiments, each layer of pillars in the same columnar structure is the same type of pillar; and/or

The upright columns on the same layer are all of the same type.

In some embodiments, the pillars in the columnar structure comprise a bottom layer pillar and a top layer pillar; wherein

The bottom layer upright posts and the top layer upright posts are solid metal upright posts;

or the bottom layer upright post is a solid metal post, and the top layer upright post is a non-metal solid post;

or the bottom layer upright post is a solid metal post, and the top layer upright post is a hollow post;

or the bottom layer upright post is a non-metal solid post, and the top layer upright post is a hollow post;

or the bottom layer upright post is a hollow post, and the top layer upright post is a solid metal post or a non-metal solid post.

In some embodiments, the number of the upright columns in the columnar structure is n, wherein n is more than or equal to 3 and is an integer; wherein

The n layers of upright columns are all solid metal columns;

or the n-1 layers of upright columns close to the reflecting layer are all solid metal columns, and the nth layer of upright column is a hollow column;

or the n-1 layers of upright columns close to the reflecting layer are all non-metal solid columns, and the nth layer of upright column is a hollow column.

In some embodiments, the total height of the columnar structures is greater than or equal to 1.5 micrometers and less than or equal to 2.5 micrometers;

the cross section one-way width of the uppermost layer of the pillars far away from the reflecting layer is more than or equal to 0.5 micrometer and less than or equal to 3 micrometers.

In some embodiments, the CMOS infrared sensing structure further comprises an adhesion layer,

the adhesion layer covers at least the bottom surface of the columnar structure contacting the support base.

In some embodiments, the adhesive layer is also located between two adjacent layers of the pillars.

In some embodiments, the material comprising the adhesion layer comprises at least one of titanium, titanium nitride, tantalum, or tantalum nitride.

In some embodiments, the side wall of the hollow column is formed by combining metal and medium, and the side wall of the hollow column sequentially comprises a first medium layer, a metal layer and a second medium layer along the radial direction of the hollow column;

the first medium layer and the metal layer are both U-shaped, and the U-shaped bottom of the metal layer is in contact with the supporting base or in contact with the metal of other upright columns between the hollow column and the supporting base;

the second dielectric layer is arranged on one side of the metal layer, which is far away from the first dielectric layer.

In some embodiments, the metallic material constituting the side wall of the hollow pillar comprises at least one of titanium, titanium nitride, tantalum, or tantalum nitride, or the metallic material constituting the side wall of the hollow pillar comprises at least one of titanium tungsten alloy, nickel chromium alloy, nickel platinum alloy, nickel silicon alloy, nickel, chromium, or platinum;

The dielectric material forming the side wall of the hollow column comprises at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon, silicon carbide or aluminum oxide.

In some embodiments, the side walls and the bottom of the non-metal solid column are formed by a metal material, and the space surrounded by the side walls is filled with a non-metal material.

In some embodiments, the non-metallic material comprises at least one of silicon dioxide, silicon nitride, amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon, silicon carbide, silicon carbonitride or aluminum oxide;

the metal material comprises at least one of titanium, titanium nitride, tantalum or tantalum nitride, or the metal material comprises at least one of titanium-tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, nickel-silicon alloy, nickel, chromium or platinum.

In some embodiments, the material comprising the solid metal posts comprises at least one of aluminum, copper, or tungsten.

The present disclosure also provides an infrared detector based on the cmos process, which includes any one of the above infrared detector pixels;

and the infrared detector pixels are arranged in an array.

Compared with the prior art, the technical scheme provided by the embodiment of the disclosure has the following advantages:

(1) In the infrared detector pixel provided by the embodiment of the disclosure, the CMOS process is utilized to realize the integrated preparation of the CMOS measurement circuit system and the CMOS infrared sensing structure on the CMOS production line, compared with the MEMS process, the CMOS has no process compatibility problem, the technical difficulty faced by the MEMS process is solved, and the transportation cost can be reduced and the risk caused by the problems of transportation and the like can be reduced by adopting the CMOS process production line process to prepare the infrared detector; the infrared detector takes silicon oxide as a sacrificial layer, the silicon oxide is completely compatible with a CMOS (complementary metal oxide semiconductor) process, the preparation process is simple and easy to control, the CMOS process does not have the problem that the polyimide of the sacrificial layer is not released cleanly to influence the vacuum degree of a detector chip, the subsequent film growth temperature is not limited by the material of the sacrificial layer, the multilayer process design of the sacrificial layer can be realized, the process is not limited, the planarization can be easily realized by using the sacrificial layer, and the process difficulty and the possible risks are reduced; the infrared detector prepared by the integrated CMOS process can realize the aims of high yield, low cost, high yield and large-scale integrated production of chips, and provides a wider application market for the infrared detector; the infrared detector based on the CMOS process can realize smaller size and thinner film thickness of a characteristic structure, so that the infrared detector has larger duty ratio, lower thermal conductivity and smaller thermal capacity, and the infrared detector has higher detection sensitivity, longer detection distance and better detection performance; the infrared detector based on the CMOS process can make the pixel size of the detector smaller, realize smaller chip area under the same array pixel, and is more beneficial to realizing the miniaturization of a chip; the infrared detector based on the CMOS process has mature process production line and higher process control precision, can better meet the design requirement, has better product consistency, is more beneficial to the adjustment performance of a circuit chip and is more beneficial to industrialized mass production;

(2) By arranging the CMOS infrared sensing structure to comprise a columnar structure with at least two layers of stand columns which are arranged in a superposition way, each layer of upright post can be at least one of a solid metal post, a non-metal solid post or a hollow post, the material for forming the side wall of the non-metal solid post and the material for forming the side wall of the hollow post comprise metal, the height of each layer of upright post can be reduced while the integral height of the columnar structure meets the requirement and the electric connection between the infrared conversion structure and the supporting base is realized, because the height of the upright post is lower, the better the steepness, therefore, each layer of upright post with better steepness is easy to form, thereby leading the whole steepness of the columnar structure to be better, the overall size of the infrared conversion structure can be smaller, so that the occupied space of the columnar structure is favorably reduced, the effective area of the infrared conversion structure is increased, the duty ratio is further improved, and the detection sensitivity is improved;

(3) the CMOS infrared sensing structure further comprises a medium protection layer and an etching barrier layer, wherein the medium protection layer is located on the reflection layer and surrounds the side face of the columnar structure, and the etching barrier layer at least covers the corner position of the medium protection layer; meanwhile, the dielectric protection layer coating the columnar structure can reduce the contact between the columnar structure and the external environment, reduce the contact resistance between the columnar structure and the external environment, further reduce the noise of the infrared detector pixel, improve the detection sensitivity of the infrared detection sensor and improve the detection performance of the infrared detection sensor; on the other hand, because the etching barrier layer is arranged to at least cover the corner position of the medium protection layer, the medium protection layer can be protected by the etching barrier layer, and the influence of the process of removing the sacrificial layer on the medium protection layer is weakened, so that the medium protection layer can effectively protect and support the columnar structure, and the structural stability of the infrared detector is improved.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.

In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present disclosure, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.

Fig. 1 is a schematic perspective structure diagram of an infrared detector pixel according to an embodiment of the present disclosure;

FIG. 2 is a schematic cross-sectional structure diagram of an infrared detector pixel according to an embodiment of the present disclosure;

FIG. 3 is a schematic cross-sectional structure diagram of another infrared detector pixel according to an embodiment of the disclosure;

FIG. 4 is a schematic cross-sectional structure diagram of a pixel of another infrared detector according to an embodiment of the disclosure;

FIG. 5 is a schematic cross-sectional structure diagram of a pixel of another infrared detector according to an embodiment of the disclosure;

FIG. 6 is a schematic cross-sectional structure diagram of a pixel of another infrared detector according to an embodiment of the disclosure;

FIG. 7 is a schematic cross-sectional structure diagram of a pixel of another infrared detector according to an embodiment of the disclosure;

FIG. 8 is a schematic cross-sectional view of an infrared detector pixel according to an embodiment of the disclosure;

FIG. 9 is a schematic cross-sectional view of an infrared detector pixel according to an embodiment of the disclosure;

FIG. 10 is a schematic cross-sectional view of an infrared detector pixel according to an embodiment of the disclosure;

FIG. 11 is a top view of a corrosion barrier structure in an infrared detector pixel of an embodiment of the disclosure;

FIG. 12 is a top view of another corrosion barrier structure in an infrared detector pixel of an embodiment of the disclosure;

fig. 13 is a schematic perspective structure diagram of an infrared detector pixel according to an embodiment of the present disclosure;

FIG. 14 is a schematic diagram of a CMOS measurement circuitry according to an embodiment of the disclosure;

FIG. 15 is a schematic cross-sectional view of another infrared detector in accordance with an embodiment of the disclosure;

FIG. 16 is a schematic cross-sectional view of another infrared detector in accordance with an embodiment of the disclosure;

FIG. 17 is a schematic cross-sectional view of another infrared detector according to an embodiment of the disclosure

Fig. 18 is a schematic cross-sectional view of another infrared detector according to an embodiment of the disclosure.

Detailed Description

In order that the above objects, features and advantages of the present disclosure may be more clearly understood, aspects of the present disclosure will be further described below. It should be noted that the embodiments and features of the embodiments of the present disclosure may be combined with each other without conflict.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced in other ways than those described herein; it is to be understood that the embodiments disclosed in the specification are only a few embodiments of the present disclosure, and not all embodiments.

Fig. 1 is a schematic perspective structure diagram of an infrared detector pixel according to an embodiment of the present disclosure, and fig. 2 is a schematic cross-sectional structure diagram of an infrared detector pixel according to an embodiment of the present disclosure. Referring to fig. 1 and 2, the infrared detector pixel includes: the CMOS measurement circuit system comprises a CMOS measurement circuit system 1 and a CMOS infrared sensing structure 2 positioned on the CMOS measurement circuit system 1, wherein the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 are both prepared by adopting a CMOS process; the CMOS infrared sensing structure 2 is fabricated directly on the CMOS measurement circuitry 1.

Specifically, the CMOS infrared sensing structure 2 is configured to convert an external infrared signal into an electrical signal and transmit the electrical signal to the CMOS measurement circuit system 1, and the CMOS measurement circuit system 1 reflects temperature information corresponding to the infrared signal according to the received electrical signal, thereby implementing a temperature detection function of the infrared detector. The CMOS measuring circuit system 1 and the CMOS infrared sensing structure 2 are both prepared by using a CMOS process, and the CMOS infrared sensing structure 2 is directly prepared on the CMOS measuring circuit system 1, namely, the CMOS measuring circuit system 1 is prepared by using the CMOS process, and then the CMOS infrared sensing structure 2 is continuously prepared by using the CMOS process by using the CMOS production line and parameters of various processes compatible with the production line.

Therefore, the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 are integrally prepared on the CMOS production line by utilizing the CMOS process, compared with the MEMS process, the CMOS process does not have the process compatibility problem, the technical difficulty of the MEMS process is solved, the transportation cost can be reduced by adopting the CMOS production line process to prepare the infrared detector, and the risk caused by the transportation problem and the like is reduced; the infrared detector takes silicon oxide as a sacrificial layer, the silicon oxide is completely compatible with a CMOS (complementary metal oxide semiconductor) process, the preparation process is simple and easy to control, the CMOS process does not have the problem that the polyimide of the sacrificial layer is not released cleanly to influence the vacuum degree of a detector chip, the subsequent film growth temperature is not limited by the material of the sacrificial layer, the multilayer process design of the sacrificial layer can be realized, the process is not limited, the planarization can be easily realized by using the sacrificial layer, and the process difficulty and the possible risks are reduced; the infrared detector prepared by the integrated CMOS process can realize the aims of high yield, low cost, high yield and large-scale integrated production of chips, and provides a wider application market for the infrared detector; the infrared detector based on the CMOS process can realize smaller size and thinner film thickness of a characteristic structure, so that the infrared detector has larger duty ratio, lower thermal conductivity and smaller thermal capacity, and the infrared detector has higher detection sensitivity, longer detection distance and better detection performance; the infrared detector based on the CMOS process can make the pixel size of the detector smaller, realize smaller chip area under the same array pixel, and is more beneficial to realizing the miniaturization of a chip; the infrared detector based on the CMOS process has the advantages of mature process production line, higher process control precision, better meeting design requirements, better product consistency, more contribution to circuit chip adjustment performance and more contribution to industrialized mass production.

With reference to fig. 1 and fig. 2, the CMOS infrared sensing structure 2 includes a reflective layer 21, an infrared conversion structure 23, and a plurality of columnar structures 22 on the CMOS measurement circuitry 1, the columnar structures 22 are located between the reflective layer 21 and the infrared conversion structure 23, the reflective layer 21 includes a reflective plate 212 and a supporting base 211, and the infrared conversion structure 23 is electrically connected to the CMOS measurement circuitry 1 through the columnar structures 22 and the supporting base 211; the columnar structure 22 comprises at least two layers of columns which are arranged in an overlapping manner; each layer of upright column can be at least one of a solid metal column, a non-metal solid column or a hollow column, and the material for forming the side wall of the non-metal solid column and the material for forming the side wall of the hollow column both comprise metal; the CMOS infrared sensing structure 2 further comprises a dielectric protection layer 24 and an etching barrier layer 25 which are positioned on the reflecting layer 21; the dielectric protection layer 24 surrounds the side surfaces of the columnar structures 22, and the etching stop layer 25 at least covers the corner positions of the dielectric protection layer 24.

The reflecting layer 21 is used for reflecting infrared rays to an infrared conversion structure 23 in the CMOS infrared sensing structure, and is matched with the resonant cavity to realize secondary absorption of the infrared rays; the columnar structure 22 is located between the reflective layer 21 and the infrared conversion structure 23, and is used for supporting the infrared conversion structure 23 in the CMOS infrared sensing structure 2 after the sacrificial layer on the CMOS measurement circuit system 1 is released, the infrared conversion structure 23 detects an infrared radiation signal and converts the detected infrared radiation signal into an electrical signal, the electrical signal is transmitted to the CMOS measurement circuit system 1 through the columnar structure 22 and the corresponding supporting base 211, and the CMOS measurement circuit system 1 processes the electrical signal to reflect temperature information, so that the non-contact infrared temperature detection of the infrared detector is realized. Specifically, the CMOS infrared sensing structure 2 outputs a positive electric signal and a ground electric signal through different electrode structures, and the positive electric signal and the ground electric signal are transmitted to the supporting base 211 electrically connected to the pillar structures 22 through different pillar structures 22. In addition, the reflective layer 21 includes a reflective plate 212 and a supporting base 211, a portion of the reflective layer 21 serves as a dielectric for electrically connecting the columnar structure 22 with the CMOS measurement circuit system 1, that is, the supporting base 211, and the reflective plate 212 is used for reflecting the infrared rays to the infrared conversion structure 23, and the secondary absorption of the infrared rays is realized by matching with a resonant cavity formed between the reflective layer 21 and the infrared conversion structure 23, so as to improve the infrared absorption rate of the infrared detector and optimize the infrared detection performance of the infrared detector.

Referring to fig. 1, the infrared conversion structure 23 may structurally include an absorption plate 2301 and a beam structure 2302, the absorption plate 2301 being connected with the pillar structure 22 through the beam structure 2302; meanwhile, the film structure of the infrared conversion structure 23 may include a heat sensitive layer 232, an electrode layer 231, and a passivation layer 233; wherein the thermosensitive layer 232 is only located on the absorption plate 2301 for converting a temperature signal into an electrical signal, the electrode layer 231 for adjusting the electrical resistance of the thermosensitive layer 232 and transmitting the electrical signal of the thermosensitive layer 232 to the CMOS measurement circuitry 1 through the beam structure 2302, and the passivation layer 233 for protecting the thermosensitive layer and the electrode layer.

Or, the absorption plate 2301 includes a support layer, an electrode layer, a thermal sensitive layer and a passivation layer, the beam structure 2302 may include the support layer, the electrode layer and the passivation layer, the beam structure 2302 may further include the thermal sensitive layer, the support layer is located on a side of the passivation layer adjacent to the CMOS measurement circuit system 1, the electrode layer and the thermal sensitive layer are located between the support layer and the passivation layer, the passivation layer covers the electrode layer, the thermal sensitive layer may be disposed to cover the beam structure 2302, the thermal conductivity of the beam structure 2302 is reduced by using the characteristic of small thermal conductivity of the thermal sensitive material such as amorphous silicon, amorphous germanium or amorphous silicon germanium, and the thermal sensitive layer may serve as a support material of the beam structure 2302 instead of the support layer, or may serve as an electrode protection material of the beam structure 2302 instead of the passivation layer.

Specifically, the supporting layer is used for supporting the upper film layer in the infrared conversion structure 23 after the sacrificial layer is released, the thermosensitive layer is used for converting infrared temperature detection signals into infrared detection electric signals, the electrode layer is used for transmitting the infrared detection electric signals converted from the thermosensitive layer to the CMOS measurement circuit system 1 through the beam structures 2302 on the left side and the right side, the two beam structures 2302 respectively transmit positive and negative signals of the infrared detection electric signals, the read-out circuit in the CMOS measurement circuit system 1 realizes non-contact infrared temperature detection through analysis of the acquired infrared detection electric signals, and the passivation layer is used for protecting the electrode layer from oxidation or corrosion. In addition, the thermosensitive layer may be located above the electrode layer or below the electrode layer. Can set up and correspond absorption plate 2301, temperature sensing layer and electrode layer are located the airtight space that supporting layer and passivation layer formed, realize the protection to temperature sensing layer and electrode layer in absorption plate 2301, correspond beam structure 2302, and the electrode layer is located the airtight space that supporting layer and passivation layer formed, realizes the protection to electrode layer in beam structure 2302.

For example, the material forming the heat sensitive layer may include at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, titanium oxide, vanadium oxide, or titanium vanadium oxide, the material forming the support layer may include one or more of amorphous carbon, aluminum oxide, amorphous silicon, amorphous germanium, or amorphous silicon germanium, the material forming the electrode layer may include one or more of titanium, titanium nitride, tantalum nitride, titanium tungsten alloy, nickel-chromium alloy, nickel-silicon alloy, nickel, or chromium, and the material forming the passivation layer may include one or more of amorphous carbon, aluminum oxide, amorphous silicon, amorphous germanium, or amorphous silicon germanium. In addition, when the absorbing plate 2301 is configured to include a thermal sensitive layer, and the thermal sensitive layer is made of amorphous silicon, amorphous carbon, amorphous germanium, or amorphous silicon germanium, the supporting layer and/or the passivation layer on the beam structure 2302 may be replaced by the thermal sensitive layer, because the thermal conductivity of the amorphous silicon, amorphous germanium, or amorphous silicon germanium is relatively low, which is beneficial to reducing the thermal conductivity of the beam structure 2302 and further improving the infrared responsivity of the infrared detector.

In other embodiments, the infrared detector pixel may further include other structures, which are not described or limited herein.

The reflective layer 21 includes a reflective plate 212 and a supporting base 211, the reflective plate 212 reflects infrared radiation, the supporting base 211 is electrically connected to the pillar structure 22 and the CMOS measurement circuit system 1, when the infrared conversion structure 23 detects an infrared radiation signal and converts the detected infrared radiation signal into an electrical signal, the electrical signal can be transmitted to the CMOS measurement circuit system 1 through the pillar structure 22 and the supporting base 211, and the CMOS measurement circuit system 1 receives the electrical signal.

The CMOS measurement circuitry 1 may further include at least one hermetic release isolation layer (not shown) above the CMOS measurement circuitry 1, where the hermetic release isolation layer is used to protect the CMOS measurement circuitry 1 from process effects during an etching process for fabricating the CMOS infrared sensing structure 2.

Optionally, a hermetic release barrier is located at an interface between the CMOS measurement circuitry 1 and the CMOS infrared sensing structure 2 and/or in the CMOS infrared sensing structure 2, the hermetic release barrier is used to protect the CMOS measurement circuitry 1 from erosion when performing a corrosion process to release the sacrificial layer, and the hermetic release barrier uses a CMOS process corrosion resistant material including at least one of silicon, germanium, silicon germanium alloy, amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon, silicon carbide, aluminum oxide, silicon nitride, or silicon carbonitride.

Illustratively, the close-release isolation layer is located in the CMOS infrared sensing structure 2, and the close-release isolation layer may be located above a metal interconnection layer (also referred to as a "metal layer") of the reflection layer 21, and the close-release isolation layer covers the columnar structure 22, and by providing the close-release isolation layer to cover the columnar structure 22, on one hand, the close-release isolation layer may be used as a support at the columnar structure 22, so as to improve the stability of the columnar structure 22, and ensure the electrical connection between the columnar structure 22 and the infrared conversion structure 23 as well as the support base 211. On the other hand, the airtight release insulating layer coating the columnar structure 22 can reduce the contact between the columnar structure 22 and the external environment, reduce the contact resistance between the columnar structure 22 and the external environment, further reduce the noise of the infrared detector pixel, and improve the detection sensitivity of the infrared detection sensor. In addition, the resonant cavity of the infrared detector is realized by releasing the vacuum cavity after the silicon oxide sacrificial layer is released, the reflecting layer 21 is used as the reflecting layer of the resonant cavity, the sacrificial layer is positioned between the reflecting layer 21 and the infrared conversion structure 23, and when at least one layer of closed release isolating layer positioned on the reflecting layer 21 is arranged to select silicon, germanium, silicon-germanium alloy, amorphous silicon, amorphous germanium or amorphous silicon-germanium as a part of the resonant cavity, the reflecting effect of the reflecting layer is not influenced, the height of the resonant cavity can be reduced, the thickness of the sacrificial layer is further reduced, and the release difficulty of the sacrificial layer formed by silicon oxide is reduced. In addition, a closed release isolation layer and the columnar structure 22 are arranged to form a closed structure, so that the CMOS measurement circuit system 1 is completely separated from the sacrificial layer, and the CMOS measurement circuit system 1 is protected.

Alternatively, the hermetic release isolation layer 11 is located at the interface between the CMOS measurement circuitry 1 and the CMOS infrared sensing structure 2, for example, the hermetic release isolation layer is located between the reflection layer 21 and the CMOS measurement circuitry 1, that is, the hermetic release isolation layer is located below the metal interconnection layer of the reflection layer 21, and the support base 211 is electrically connected to the CMOS measurement circuitry 1 through a through hole penetrating through the hermetic release isolation layer, as shown in fig. 17. Specifically, because the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 are both formed by using a CMOS process, after the CMOS measurement circuit system 1 is formed, a wafer including the CMOS measurement circuit system 1 is transferred to a next process to form the CMOS infrared sensing structure 2, and since silicon oxide is the most commonly used dielectric material in the CMOS process and silicon oxide is mostly used as an insulating layer between metal layers on the CMOS circuit, if no insulating layer is used as a barrier when silicon oxide with a thickness of about 2um is corroded, the circuit will be seriously affected, so a hermetic release insulating layer is provided to release the silicon oxide on the CMOS measurement circuit system without corroding the silicon oxide on the sacrificial layer. After the CMOS measurement circuit system 1 is prepared and formed, a closed release isolation layer is prepared and formed on the CMOS measurement circuit system 1, the CMOS measurement circuit system 1 is protected by the closed release isolation layer, and in order to ensure the electrical connection between the support base 211 and the CMOS measurement circuit system 1, after the closed release isolation layer is prepared and formed, a through hole is formed in a region of the closed release isolation layer corresponding to the support base 211 by using an etching process, and the support base 211 is electrically connected with the CMOS measurement circuit system 1 through the through hole. In addition, a closed release isolation layer and the support base 211 are arranged to form a closed structure, so that the CMOS measurement circuit system 1 is completely separated from the sacrificial layer, and the CMOS measurement circuit system 1 is protected.

Or, in the infrared detector, the interface between the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 is provided with at least one layer of closed release insulating layer, that is, at least one layer of closed release insulating layer is provided between the reflection layer 21 and the CMOS measurement circuit system 1, and at least one layer of closed release insulating layer is provided on the reflection layer 21, as shown in fig. 18, the effect is the same as above, and details are not repeated here.

Illustratively, the material constituting the hermetic release barrier layer may include silicon, germanium, silicon-germanium alloy, amorphous silicon, amorphous germanium, amorphous siliconAt least one of silicon germanium, amorphous carbon, silicon carbide, aluminum oxide, silicon nitride or silicon carbonitride, and the thickness of the sealing release isolation layer is more than or equal to that of the sealing release isolation layer

Is less than or equal to

Specifically, silicon, germanium, a silicon-germanium alloy, amorphous silicon, amorphous germanium, amorphous silicon-germanium, amorphous carbon, silicon carbide, aluminum oxide, silicon nitride, and silicon carbonitride are all CMOS process corrosion-resistant materials, i.e., these materials are not corroded by the sacrificial layer release agent, so the hermetic release barrier layer can be used to protect the CMOS measurement circuitry 1 from corrosion when the corrosion process is performed to release the sacrificial layer. In addition, the closed release isolation layer covers the CMOS measurement circuit system 1, and the closed release isolation layer can also be used for protecting the CMOS measurement circuit system 1 from being influenced by the process in the etching process of manufacturing the CMOS infrared sensing structure 2. In addition, when at least one airtight release insulating layer is disposed on the reflective layer 21, the material for forming the airtight release insulating layer includes at least one of silicon, germanium, silicon-germanium alloy, amorphous silicon, amorphous germanium, amorphous silicon-germanium, amorphous carbon, silicon carbide, aluminum oxide, silicon nitride or silicon carbonitride, and the thickness of the first dielectric layer is greater than that of the first dielectric layer

Is less than or equal to

When setting up airtight release insulating layer and improving columnar structure 22 stability, airtight release insulating layer can hardly influence the reflection process in the resonant cavity, can avoid airtight release insulating layer to influence the reflection process of resonant cavity, and then avoids airtight release insulating layer to infrared detector detectivity's influence.

The CMOS manufacturing process of the CMOS infrared sensing structure 2 comprises a metal interconnection process, a through hole process and an RDL (remote description language) process, and the CMOS infrared sensing structure 2 comprises at least two metal interconnection layers, at least two dielectric layers and a plurality of interconnection through holes so as to construct and communicate all structural components in the infrared detector.

Illustratively, the dielectric layer at least comprises a sacrificial layer and a heat-sensitive dielectric layer, the heat-sensitive dielectric layer at least comprises a heat-sensitive layer, and also comprises a supporting layer and/or a passivation layer, and the metal interconnection layer at least comprises a reflecting layer 21 and an electrode layer; the thermal sensitive medium layer comprises a thermal sensitive material with a resistance temperature coefficient larger than a set value, the resistance temperature coefficient can be larger than or equal to 0.015/K, for example, the thermal sensitive material with the resistance temperature coefficient larger than the set value forms a thermal sensitive layer in the thermal sensitive medium layer, the thermal sensitive medium layer is used for converting temperature change corresponding to infrared radiation absorbed by the thermal sensitive medium layer into resistance change, and then an infrared target signal is converted into a signal capable of being read electrically through the CMOS measuring circuit system 1.

Specifically, the metal interconnection process is used for realizing the electrical connection of an upper metal interconnection layer and a lower metal interconnection layer, the through hole process is used for forming an interconnection through hole for connecting the upper metal interconnection layer and the lower metal interconnection layer, the RDL process is a rewiring layer process, specifically, a layer of metal is re-distributed above the top metal of the circuit and is electrically connected with the top metal of the circuit through a tungsten column, the RDL process can be used for preparing a reflection layer in the infrared detector on the top metal of the CMOS measurement circuit system 1, and a supporting base on the reflection layer is electrically connected with the top metal of the CMOS measurement circuit system 1. In addition, the heat-sensitive dielectric layer comprises a heat-sensitive material with a resistance temperature coefficient larger than a set value, and the resistance temperature coefficient can be larger than or equal to 0.015/K, so that the detection sensitivity of the infrared detector can be improved.

In addition, the CMOS manufacturing process of the CMOS measurement circuit system 1 may also include a metal interconnection process and a via process, the CMOS measurement circuit system 1 includes metal interconnection layers, dielectric layers, and a silicon substrate at the bottom, which are disposed at intervals, and the upper and lower metal interconnection layers are electrically connected through vias.

Optionally, the sacrificial layer is used to form the CMOS infrared sensing structure 2 into a hollow structure, the material of the sacrificial layer is silicon oxide, and the sacrificial layer is etched by a post-CMOS process, which may, for example, use at least one of gaseous hydrogen fluoride, carbon tetrafluoride and trifluoromethane to etch the sacrificial layer. Specifically, a sacrificial layer (not shown in the figure) is arranged between the reflection layer and the beam structure, when the reflection layer is provided with the closed release isolation layer, the sacrificial layer is arranged between the closed release isolation layer and the beam structure, the material forming the sacrificial layer is silicon oxide, so as to be compatible with a CMOS process, and a post-CMOS process can be adopted, that is, the post-CMOS process corrodes the sacrificial layer to release the sacrificial layer in the final infrared detection chip product.

In the infrared detector pixel, by arranging the CMOS infrared sensing structure 2 to comprise the columnar structure 22 of at least two layers of columns which are arranged in a superposition manner, each layer of column can be at least one of a solid metal column, a non-metal solid column or a hollow column, and the material for forming the side wall of the non-metal solid column and the material for forming the side wall of the hollow column both comprise metal, the height of each layer of column can be reduced while the whole height of the columnar structure 22 meets the requirement and the electric connection between the infrared conversion structure 23 and the supporting base 211 is realized, and the lower the height of the column is, the better the steepness is, therefore, each layer of column with better steepness is easy to form, so that the whole steepness of the columnar structure 22 is better, the whole size of the column can be smaller, the occupied space of the columnar structure 22 is beneficial to reducing, and the effective area of the infrared conversion structure 23 is increased, and further, the duty ratio is improved, and the detection sensitivity is improved.

Meanwhile, by arranging the CMOS infrared sensing structure 2 to further include the dielectric protection layer 24 and the etching barrier layer 25 on the reflection layer 21, the dielectric protection layer 24 surrounds the side surface of the columnar structure 22, and the etching barrier layer 25 at least covers the corner position of the dielectric protection layer 24, on one hand, the bottom of the columnar structure 22 can be coated by the dielectric protection layer 24, and the mechanical stability of the columnar structure 22 is improved, so that the better connection performance between the columnar structure 22 and the support base 211 as well as the infrared conversion structure 23 is ensured, and the structural stability is improved; meanwhile, the dielectric protection layer 24 covering the columnar structure 22 can also reduce the contact between the columnar structure 22 and the external environment, reduce the contact resistance between the columnar structure 22 and the external environment, further reduce the noise of the infrared detector pixel, improve the detection sensitivity of the infrared detection sensor, and improve the detection performance of the infrared detection sensor; on the other hand, because the etching blocking layer 25 is at least covered on the corner position of the dielectric protection layer 24, the dielectric protection layer 24 can be protected by the etching blocking layer 25, the influence of the process of removing the sacrificial layer on the dielectric protection layer 24 is weakened, the dielectric protection layer 24 can effectively protect and support the columnar structure 22, and the structural stability of the infrared detector is improved.

Of the cross-sectional structures of the various infrared detector pixels, only the reflective layer 21 is exemplarily shown to include one reflective plate 212 and two supporting bases 211, and correspondingly, the infrared detector pixel includes two columnar structures 22; the infrared detector pixel in the corresponding perspective structural diagram (i.e., fig. 1) includes four columnar structures 22, but does not limit the infrared detector pixel provided in the embodiments of the present disclosure.

In other embodiments, the number of the pillar structures 22 in the infrared detector pixel can be set based on the structural requirements thereof, and is not limited herein.

In some embodiments, the material comprising the dielectric protection layer 24 comprises at least one of silicon (Si), germanium (Ge), amorphous silicon (a-Si), amorphous germanium (a-Ge), silicon germanium (SiGe), or amorphous silicon germanium (a-SiGe).

Wherein, materials such as silicon (Si), germanium (Ge), amorphous silicon (a-Si), amorphous germanium (a-Ge), silicon germanium (SiGe) and amorphous silicon germanium (a-SiGe) are all better to the transmissivity of infrared light, and do not influence the reflection of reflector layer to infrared light basically, therefore set up the material of medium protective layer 24 and be at least one of above-mentioned materials, when utilizing medium protective layer 24 to improve the stability of columnar structure 22, can avoid the influence of the material of medium protective layer 24 to the reflection process in resonance chamber, and then avoid medium protective layer 24 to the influence of CMOS infrared sensing structure detection sensitivity.

In addition, when the material constituting the dielectric protection layer 24 includes at least one of silicon (Si), germanium (Ge), amorphous silicon (a-Si), amorphous germanium (a-Ge), silicon germanium (SiGe) or amorphous silicon germanium (a-SiGe), the dielectric protection layer 24 prepared to be formed may occupy a portion of the space of the resonant cavity, so that the thickness of the sacrificial layer for forming the resonant cavity may be reduced, thereby reducing the difficulty of releasing the sacrificial layer corresponding to the formation of the resonant cavity.

In some embodiments, each layer of pillars in the same columnar structure 22 is the same type of pillar (as shown in FIG. 2); and/or the upright columns on the same layer are all the same type of upright columns.

Wherein, each layer of the pillars in the same columnar structure 22 is a solid metal pillar, as shown in fig. 2; or all the non-metal solid columns or all the hollow columns. Thus, the types of the pillars in the same columnar structure 22 can be reduced, which is beneficial to simplifying the preparation process of the columnar structure.

And/or the columns on the same layer are all solid metal columns, as shown in fig. 2; or all non-metal solid columns, or all hollow columns, as shown in fig. 5. By the arrangement, the stand columns on the same layer can be formed by the same process step, and the preparation process of the columnar structure is simplified.

In other embodiments, the same pillar structure 22 may further include a plurality of different types of pillars, and the same layer may also be provided with a plurality of different types of pillars, which may be provided based on the requirements of the infrared detector pixel, and is not limited herein.

In the above embodiment, the number of the pillar layers in the same columnar structure 22 may be two, three or more, which is exemplarily described below with reference to fig. 2 to 8.

In some embodiments, fig. 3 is a schematic cross-sectional structure diagram of another infrared detector pixel according to an embodiment of the present disclosure, fig. 4 is a schematic cross-sectional structure diagram of another infrared detector pixel according to an embodiment of the present disclosure, fig. 5 is a schematic cross-sectional structure diagram of another infrared detector pixel according to an embodiment of the present disclosure, fig. 6 is a schematic cross-sectional structure diagram of another infrared detector pixel according to an embodiment of the present disclosure, and fig. 7 is a schematic cross-sectional structure diagram of another infrared detector pixel according to an embodiment of the present disclosure. With reference to fig. 2-7, the pillars in the columnar structure 22 include a bottom-layer pillar (shown as second-layer pillar 222) and a top-layer pillar (shown as first-layer pillar 221); wherein, the bottom layer upright post and the top layer upright post are both solid metal upright posts, which can be seen in figure 2; or the bottom layer upright post is a solid metal post, and the top layer upright post is a non-metal solid post, which can be seen in fig. 3 or fig. 7; or the bottom layer upright post is a solid metal post, and the top layer upright post is a hollow post, which can be seen in fig. 4; or the bottom layer upright post is a non-metal solid post, and the top layer upright post is a hollow post, which can be seen in fig. 5; or the bottom layer upright post is a hollow post, and the top layer upright post is a solid metal post, which can be seen in fig. 6; the bottom layer upright post is a hollow post, and the top layer upright post is a non-metal solid post.

As shown in fig. 2, a double-layer solid metal column is supported between the infrared conversion structure 23 and the support base 211, so that the space occupied by the columnar structure 22 is reduced to improve the duty ratio, thereby improving the detection sensitivity, and meanwhile, the mechanical stability of the solid metal column is better, thereby being beneficial to improving the support stability between the support base 211 and the infrared conversion structure 23, and further improving the structural stability of the infrared sensor pixel and the infrared detector comprising the infrared sensor pixel; meanwhile, the solid metal column has relatively low resistance, so that the signal loss in the process of transmitting the electric signal between the infrared conversion structure 23 and the CMOS measurement circuit system 1 is reduced, and the detection performance of the infrared detector is improved; in addition, the size of the solid metal column is easier to accurately control, so that the requirement for smaller chip size is met, and the miniaturization of the infrared detector is realized.

Or, as shown in fig. 4, the pillar structure 22 formed by stacking solid metal pillars and hollow pillars is used to connect the infrared conversion structure 23 and the supporting base 211, so that on one hand, the corresponding effect of the solid metal pillars can be achieved; on the other hand, because the side wall of the hollow column is formed by combining metal and medium, when the electrical connection between the infrared conversion structure 23 and the CMOS measurement circuit system 1 through the supporting base 211 is ensured to be realized by the columnar structure 22 comprising the hollow column, the heat conduction of the columnar structure 22 can be reduced by utilizing the structure of the hollow column, so that the influence of the heat radiation generated by the columnar structure 22 on the electric signal generated by the infrared conversion structure 23 is reduced, and the improvement of the detection performance of the infrared detector pixel and the infrared detector comprising the infrared detector pixel is facilitated.

Or, as shown in fig. 5, the pillar structure 22 formed by stacking the non-metal solid columns on the hollow columns is used to connect the infrared conversion structure 23 and the supporting base 211, so that the corresponding effect of the hollow columns can be realized, and the corresponding effect of the non-metal solid columns is also realized, which specifically includes: the side wall and the bottom (the side wall and the bottom are shown by 222) of the non-metal solid column are made of metal materials, and the space 221 surrounded by the side wall is filled with non-metal materials, so that on one hand, the heat conduction of the columnar structure 22 can be reduced, the influence of the heat radiation of the columnar structure 22 on the electric signal of the infrared conversion structure 23 can be reduced, and the detection performance can be improved; on the other hand fills non-metallic material through the space that surrounds at the lateral wall, is favorable to improving columnar structure 22's mechanical stability to promote columnar structure 22 and support stability between support base 211 and infrared conversion structure 23, be favorable to promoting the infrared detector pixel and including this infrared detector pixel's overall structure stability, thereby realize giving consideration to better structural stability and detection performance.

Alternatively, as shown in fig. 3 or fig. 7, the pillar structure 22 formed by stacking the solid metal pillar and the non-metal solid pillar is used to connect the infrared conversion structure 23 and the supporting base 211, which has the effects achieved by the solid metal pillar and the non-metal solid pillar, and is not described herein again.

Alternatively, as shown in fig. 6, the pillar structure 22 formed by stacking a hollow pillar and a solid metal pillar is used to connect the infrared conversion structure 23 and the supporting base 211, which has the effects achieved by the hollow pillar and the solid metal pillar, and is not described herein again.

In other embodiments, when the bottom layer stand column is a hollow column, the top layer stand column can also be a non-metal solid column, and the infrared detector pixel with the columnar structure has the effect that the hollow column and the non-metal solid column can realize, which is not described herein again.

In other embodiments, when the bottom layer upright post is a hollow post, the top layer upright post can also be a hollow post, i.e. a columnar structure is formed by utilizing the double-layer hollow post; or when the bottom layer stand column is the solid metal column, the top layer stand column can be the nonmetal solid column or the solid metal column, and the effect that can be realized can be understood in combination with the above, which is not described herein. It should be noted that, when the bottom layer upright is a hollow column, the film layer deposited in the subsequent step may be filled in the hollow column to improve the stability of the columnar structure 22, thereby improving the structural stability.

Thus, when the pillar structure 22 includes two layers of pillars, the type of each pillar may be set based on the requirements of the infrared detector pixel and the achievable effects of each pillar, which is not limited herein.

In some embodiments, the number of layers of the pillars in the columnar structure 22 is n, where n is greater than or equal to 2 and is an integer; wherein, the n layers of upright columns are all solid metal columns; or the n-1 layers of upright columns close to the reflecting layer 21 are all solid metal columns, and the nth layer of upright column is a hollow column; or the n-1 layers of upright columns close to the reflecting layer 21 are all non-metal solid columns, and the nth layer of upright column is a hollow column.

Exemplarily, fig. 8 is a schematic cross-sectional structure diagram of another infrared detector pixel according to an embodiment of the disclosure, and illustrates a structure of an infrared detector pixel including three layers of pillars in the pillar structure 22, where the three layers of pillars (illustrated as a first layer of pillars 221, a second layer of pillars 222, and a third layer of pillars 223) are all solid metal pillars.

In other embodiments, the number of the columns in the columnar structure 22 may also be three or more, each of the columns may be any one of a solid metal column, a non-metal solid column, and a hollow column, and may be set based on the requirements of the infrared detector pixel and the CMOS process requirements, which is not limited herein.

Thus, the columnar structure 22 may be two layers of columns, or may be three or more layers of columns; the stand can set up to the arbitrary combination of metal solid post, hollow post and nonmetal solid post, can set up based on the demand of infrared detector pixel and the technological demand of CMOS, does not limit here.

In some embodiments, the side wall of the hollow column is formed by combining metal and medium, and the side wall of the hollow column sequentially comprises a first medium layer, a metal layer and a second medium layer along the radial direction of the hollow column; the first medium layer and the metal layer are both U-shaped, and the U-shaped bottom of the metal layer is in contact with the supporting base 211 or in contact with the metal of other upright columns between the hollow column and the supporting base 211; the second dielectric layer is arranged on one side of the metal layer, which is far away from the first dielectric layer.

The metal layer may be formed of at least one metal material in the following embodiments, and the first dielectric layer and the second dielectric layer may be formed of at least one dielectric material in the following embodiments, and the materials may be the same or different, and are not limited herein.

Wherein the metal layer is sandwiched between the first dielectric layer, the second dielectric layer, and the support pedestal 211 (or the metal of the other pillars). Specifically, the U-shaped sidewall of the metal layer is sandwiched between the U-shaped sidewall of the first dielectric layer and the second dielectric layer, and the U-shaped bottom of the metal layer is sandwiched between the U-shaped bottom of the first dielectric layer and the supporting base 211 (or the metal of the other pillars). Therefore, the hollow column comprising the metal layer is electrically connected with the infrared conversion structure 23, the supporting base 211 or other layers of columns, and meanwhile, the first dielectric layer and the second dielectric layer are used for realizing insulation protection inside and outside the metal layer, so that the performance attenuation of the metal layer is reduced, and the service life of the infrared detector is prolonged; and the multi-membrane layer structure of the columnar structure 22 is utilized, so that multi-membrane layer support can be realized, and the structural stability can be improved.

In addition, set up the metal level into U type structure, utilize its U type end to realize the bottom sprag and the contact of hollow post, still can increase the area of contact between the metal level of hollow post and support base 211 or other layers of stand, reduce contact resistance, reduce the loss to the signal of telecommunication, promote the detection performance.

In other embodiments, the hollow column can be also arranged into hollow columns with other structures, such as a barrel-shaped structure, the structural form is simple, and the process difficulty is low; alternatively, the hollow column may be configured as other hollow column structures known to those skilled in the art, which are not described or limited herein.

In some embodiments, the metal material constituting the sidewall of the hollow pillar includes at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), or the metal material constituting the sidewall of the hollow pillar includes at least one of titanium tungsten alloy (TiW), nickel chromium alloy (NiCr), nickel platinum alloy (NiPt), nickel silicon alloy (NiSi), nickel (Ni), chromium (Cr), or platinum (Pt); the dielectric material forming the side wall of the hollow column comprises amorphous silicon (a-Si), amorphous germanium (a-Ge), amorphous silicon germanium (a-SiGe), amorphous carbon (a-C), silicon carbide (SiC) or aluminum oxide (Al)₂O₃) At least one of (1).

The various metals or metal alloys have good contact performance and electrical performance, and the hollow columns can be stably connected with the infrared conversion structure 23, the supporting base 211 or other layers of columns by utilizing the good contact performance of the metals or metal alloys, so that the columns are not easy to fall off, and the structural stability is enhanced; by utilizing the better electrical property, when the hollow column transmits the electric signal between the infrared conversion structure 23 and the supporting base 211, the loss of the electric signal is smaller, which is beneficial to improving the detection performance. In addition, the heat conduction of the various metals or metal alloys is small, so that the heat conduction of the columnar structure 22 is small, the influence of the heat radiation generated by the columnar structure 22 on the electric signal generated by the infrared conversion structure 23 is favorably reduced, and the detection performance is improved.

In other embodiments, the metal material forming the side wall of the hollow pillar may further include other materials known to those skilled in the art, which may meet the requirements of the infrared detector pixel, and is not limited herein.

Wherein, the dielectric materials are not corroded by VHF, so that the columnar structure 22 is not corroded when the sacrificial layer is taken out by using the VHF corrosion in the subsequent process steps; meanwhile, the mechanical strength of the joint can be enhanced, and the upper layer structure (namely the infrared conversion structure 23) and the columnar structure 22 are prevented from being connected firmly and falling off, so that the structural stability is enhanced.

In other embodiments, the dielectric material forming the sidewall of the hollow pillar may further include other materials known to those skilled in the art, which are not limited herein, and may meet the requirements of the infrared detector pixel.

In some embodiments, the sidewalls and bottom of the non-metallic solid post are formed of a metallic material, and the space surrounded by the sidewalls is filled with a non-metallic material.

So, when utilizing the lateral wall and the bottom realization electricity of nonmetal solid post to connect, can utilize the non-metallic material of its packing to realize more stable support to promote structural stability.

In some embodiments, the non-metallic material comprises silicon dioxide (SiO)₂) Silicon nitride (SiNx), nonCrystalline silicon (a-Si), amorphous germanium (a-Ge), amorphous silicon germanium (a-SiGe), amorphous carbon (a-C), silicon carbide (SiC), silicon carbonitride (SiCN) or aluminum oxide (Al)₂O₃) At least one of; the metal material includes at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), or the metal material includes at least one of titanium tungsten alloy (TiW), nickel chromium alloy (NiCr), nickel platinum alloy (NiPt), nickel silicon alloy (NiSi), nickel (Ni), chromium (Cr), or platinum (Pt).

Wherein, the mechanical stability of above-mentioned various non-metallic materials is all better, utilizes wherein at least one kind to pack the space that the lateral wall of non-metallic solid post surrounded, is favorable to promoting the holistic support performance of non-metallic solid post to improve structural stability. Meanwhile, silicon (Si), germanium (Ge), amorphous silicon (a-Si), amorphous germanium (a-Ge), amorphous silicon germanium (a-SiGe), amorphous carbon (a-C), silicon carbide (SiC) and aluminum oxide (Al) ₂O₃) The sacrificial layer is not corroded by the VHF, so that the non-metal solid column cannot be corroded when the sacrificial layer is taken out by the VHF corrosion in the subsequent process steps; meanwhile, the mechanical strength of the joint can be enhanced, and the infrared conversion structure 23, the supporting base 211 or other layers of upright columns are prevented from being connected firmly and falling off, so that the structural stability is enhanced.

In other embodiments, the non-metal material used for filling the non-metal solid pillars may further include other materials known to those skilled in the art, and the requirements of the infrared detector pixel are met, which is not limited herein.

The various metals or metal alloys have good contact performance and electrical performance, and by utilizing the good contact performance, the non-metal solid column can be stably connected with the infrared conversion structure 23, the supporting base 211 or other layers of stand columns, and is not easy to fall off, so that the structural stability is favorably enhanced; by utilizing the better electrical property of the non-metallic solid column, when the non-metallic solid column transmits the electrical signal between the infrared conversion structure 23 and the supporting base 211, the loss of the electrical signal is smaller, and the detection performance is favorably improved. In addition, the heat conduction of the various metals or metal alloys is small, so that the heat conduction of the columnar structure 22 is small, the influence of the heat radiation generated by the columnar structure 22 on the electric signal generated by the infrared conversion structure 23 is favorably reduced, and the detection performance is improved.

In other embodiments, the metal material forming the side wall and the bottom of the non-metal solid pillar may further include other materials known to those skilled in the art, which are not limited herein, and the requirements of the infrared detector pixel are met.

In some embodiments, the material comprising the solid metal posts comprises at least one of aluminum (Al), copper (Cu), or tungsten (W).

According to the arrangement, the solid metal column is formed by adopting at least one of the three metals of aluminum (Al), copper (Cu) or tungsten (W), so that the mechanical property of the solid metal column is met, stable support is realized, and simultaneously, the resistance of the solid metal column is favorably reduced, thereby reducing the loss of an electric signal and improving the detection performance of the infrared detector; in addition, the solid metal column is prepared by adopting a CMOS process, and the process integration requirement is met.

In other embodiments, the material of the solid metal column may also be other materials, and the process requirement and the performance requirement of the infrared detector pixel are met, which is not limited herein.

In some embodiments, fig. 9 is a schematic cross-sectional structure diagram of a pixel of another infrared detector according to an embodiment of the disclosure. Referring to fig. 9, the CMOS infrared sensing structure 2 further includes an adhesion layer 240, and the adhesion layer 240 covers at least the bottom surface of the pillar structures 22 contacting the support base 211.

Wherein, the adhesion layer 240 can be used for enhancing the connection performance between the columnar structure 22 and the supporting base 211 and for enhancing the connection performance between the adjacent layer columns; the connection performance can include the mechanical connection performance of the intensifier, the structural stability is improved, the electrical connection performance of the intensifier is also included, the contact resistance is reduced, the loss in the electrical signal transmission process is reduced, and the detection performance is improved.

For example, the adhesion layer 240 may be disposed only between the pillar-shaped structure 22 and the supporting base 211, and also between two adjacent layers of pillars.

In some embodiments, the material comprising adhesion layer 2400 includes at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN).

Thus, the adhesion layer 240 formed by using at least one of the four conductive materials of titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) can satisfy the requirement of using the adhesion layer 240 to enhance the mechanical and electrical connection performance between the supporting base 211 and the pillar structure 22, and enhance the mechanical and electrical connection performance between two adjacent layers of pillars; meanwhile, the adhesion layer 240 is prepared by adopting a CMOS process, and the process integration requirement is met.

Illustratively, the adhesion layer 240 may be provided as a single layer structure, a double layer structure, or a multi-layer structure, may be formed of a single material, or may be formed of two or more materials, and may be provided based on the requirements of the infrared detector and its pixel, which is not limited herein.

In other embodiments, the material of the adhesion layer 240 may also be other materials, and it is sufficient to meet the process requirements and performance requirements of the infrared detector pixel, which is not limited herein.

In some embodiments, with continued reference to fig. 9, in the case where the pillars are solid metal pillars or non-metal solid pillars (not shown in the figure), the infrared detector pixel further includes a dielectric layer 250; dielectric layer 250 covers the sides of the pillars.

The dielectric layer 250 wraps the outer side of the stand column 22, so that the electric insulation effect can be achieved, the performance degradation of the stand column 22 is slowed down, and the service life of the infrared detector is prolonged. Meanwhile, the dielectric layer 250 may serve as an auxiliary support structure for the pillar 22, and together with the pillar 22, may function to support the infrared conversion structure 23, thereby further enhancing the structural stability. Illustratively, the width of dielectric layer 250 along the axial direction of pillars 22 may be the same as the height of pillars 22.

In some embodiments, the material comprising dielectric layer 250 includes at least one of (Si), germanium (Ge), amorphous silicon (a-Si), amorphous germanium (a-Ge), amorphous silicon germanium (a-SiGe), amorphous carbon (a-C), silicon carbide (SiC), or aluminum oxide (Al2O 3).

Wherein, the above materials are not corroded by VHF, so that the dielectric layer 250 is not corroded when the sacrificial layer is taken out by using VHF corrosion in the subsequent process steps; meanwhile, the mechanical strength of the joint can be enhanced, and the upper layer structure (comprising the infrared conversion structure 23 and other layers of upright columns) is prevented from being connected with the upright columns firmly to fall off, so that the structural stability is enhanced.

In some embodiments, with continued reference to any of fig. 2-9, the total height of the pillar structures 22 is greater than or equal to 1.5 microns and less than or equal to 2.5 microns; the cross-sectional unidirectional width of the uppermost pillar (illustrated by first layer pillar 221) away from reflective layer 21 is less than or equal to 3 microns; optionally, the width may also be less than or equal to 1 micron.

By the arrangement, the size of the columnar structure 22 on the plane where the reflecting plate 212 is located can be reduced while stable support is achieved by the columnar structure 22, so that the smaller chip area under the same array pixel is realized, and the miniaturization of a chip is realized; in addition, the occupation ratio of the effective areas of the reflection plate 212 and the corresponding infrared conversion structure 23 is favorably improved, the signal intensity is enhanced, and the detection performance is improved.

Illustratively, when the uppermost pillar is circular in cross-section, its diameter is less than or equal to 3 microns; when the section of the uppermost upright post is square, the side length is less than or equal to 3 micrometers; when the cross section of the uppermost upright post is polygonal, the diagonal length of the uppermost upright post is less than or equal to 3 micrometers; when the section of the uppermost upright post is in a long strip shape, the length of the long side of the uppermost upright post is less than or equal to 3 micrometers.

Illustratively, the cross-sectional maximum unidirectional width of the uppermost pillar may be 3 microns, 2.5 microns, 2 microns, 1 micron, 0.8 microns or other width values, which may be set based on the requirements of the infrared detector, and is not limited herein.

In some embodiments, to meet other requirements of the infrared detector, the maximum unidirectional width of the cross section of the uppermost pillar may be set to be greater than 3 micrometers, which is not limited herein.

The total height of the columnar structure 22 is the height of the columnar structure in the direction perpendicular to the plane of the reflection plate 212, the stacking height of each layer of the columns, which may also be referred to as the axial height of the columnar structure 22, and may be the supporting height of the columnar structure 22, and also the distance between two parallel planes of the resonant cavity of the infrared detector pixel, that is, the distance between the reflection surface of the reflection plate 212 and the absorption surface of the infrared conversion structure 23.

On the basis, the total height of the columnar structure 22 is larger than or equal to 1.5 microns, so that the implementation of a CMOS process is facilitated, and the process difficulty is reduced; on the other hand, the distance requirement between the parallel planes of the resonant cavity can be met, and the infrared absorption efficiency is improved, so that the detection sensitivity is improved. Meanwhile, by setting the total height of the columnar structure 22 to be less than or equal to 2.5 micrometers, the total height of the columnar structure 22 can not be too high, so that the problem of poor stability caused by too high columnar structure 22 is avoided, namely, the structural stability is favorably improved; meanwhile, the size of the infrared detector pixel and the size of the whole infrared detector in the height direction are reduced, and the light, thin and small design of the infrared detector is achieved.

Illustratively, the total height of the pillar structures 22 may be 1.5 microns, 1.8 microns, 2.0 microns, 2.1 microns, 2.4 microns, 2.5 microns, or other height values, and may be set based on the performance requirements of the infrared detector and the CMOS process requirements, but is not limited thereto.

In some embodiments, with continued reference to fig. 3, etch stop layer 25 comprises a side layer 252 and a planar layer 251 disposed adjacent to each other, planar layer 251 being disposed in a ring shape, side layer 252 being disposed in a barrel shape; the side layer 252 of the etching stop layer 25 covers the side of the dielectric protection layer 24 facing the pillar structure 22, and the planar layer 251 of the etching stop layer 25 surrounds the pillar structure 22 and covers the surface of the dielectric protection layer 24 adjacent to the side.

Wherein, the side layer 252 is disposed between the pillar structure 22 and the dielectric passivation layer 24, on one hand, the dielectric passivation layer 24 can be protected from being corroded by VHF; on the other hand, the columnar structure 22 can be supported in an auxiliary manner, and the supporting performance of the columnar structure 22 is improved. Illustratively, the barrel structure of the side layer 252 may be configured as a barrel, a square barrel or other shape barrel, and may be configured based on the side shape of the pillar structure 22, which is not limited herein.

Wherein the planarization layer 251 is disposed adjacent to the side layer 252 to form an etch stop layer 25 at least covering the corner locations of the dielectric protection layer 24. For example, the ring structure of the planar layer 251 may be specifically configured as a circular ring, a square ring, or other shapes, and may be configured based on the shape of the upper surface of the pillar structure 22 and the protection requirement of the dielectric protection layer 24, which is not limited herein.

In some embodiments, the planar layer 251 may be provided in a continuous ring shape, or a ring shape formed by a plurality of independent block-shaped split pieces, which is not limited herein. The split structure is exemplified later in conjunction with fig. 11 and 12.

In some embodiments, fig. 10 is a schematic cross-sectional structure diagram of a pixel of another infrared detector according to an embodiment of the disclosure. Referring to any of fig. 2-10, a corresponding dielectric protective layer 24 is provided for each layer of pillars; the dielectric protection layer 24 is at least one layer, and correspondingly, the etching barrier layer 25 is at least one layer; the etching stop layer 25 is at least arranged at the corner position of the uppermost dielectric protection layer 24.

Illustratively, referring to fig. 3, the dielectric protection layer 24 is one layer, and the etch stop layer 25 is one layer; referring to fig. 2, 4, 5, 7, 9 or 10, the dielectric protection layer 24 is two layers, and correspondingly, the etch stop layer 25 is two layers; referring to fig. 6, the dielectric protection layer 24 is two layers, the etching stop layer 25 is one layer, and the etching stop layer 25 is disposed at the corner position of the uppermost dielectric protection layer 24; referring to fig. 8, the dielectric protection layer 24 is three-layered and the etch stopper 25 is three-layered. Meanwhile, the dielectric protective layer 24 may be provided as one layer, two layers or more corresponding to each layer of the pillars, which is not limited herein.

When the dielectric protection layer 24 has two or more layers, a part of the dielectric protection layers 24 is provided with a corresponding etching stop layer 25 for protection, for example, only the uppermost dielectric protection layer 24, only the lowermost dielectric protection layer 24, or the other dielectric protection layer or layers 24 is provided with a corresponding etching stop layer 25, which is not limited herein.

In some embodiments, with continued reference to any of FIGS. 2-10, each etch stop layer 25 in the same layer is the same shape and size.

Wherein, the shape and size of the etching barrier layer 5, including the shape and size of the planar layer 251 thereof, may be a lateral width; also included is the shape and size of its side layer 252, which may be the longitudinal height. The corresponding positions are not described in detail hereinafter.

Therefore, the same process flow and the same process parameters can be adopted to form the etching barrier layer 25 of the same layer, so that the process difficulty is lower, and the cost is lower; meanwhile, the etching barrier layers 25 at different positions on the same layer have more consistent influence on the infrared detector pixel and the performance (including mechanical performance and electrical performance) of the infrared detector comprising the infrared detector pixel, and are favorable for ensuring more uniform detection performance.

In some embodiments, with continued reference to fig. 7, when the etch stop layer 25 is at least two layers, the etch stop layer 25 at each different layer is the same shape and size.

Therefore, the etching barrier layers 25 of different layers can be formed by adopting the same process flow and process parameters, so that the process difficulty is lower and the cost is lower; meanwhile, the etching barrier layers 25 on different layers have relatively consistent influence on the infrared detector pixel and the performance (including mechanical performance and electrical performance) of the infrared detector comprising the infrared detector pixel, and are favorable for ensuring relatively good detection performance.

In some embodiments, with continued reference to any of fig. 8-10, when the etch stop layer 25 is at least two layers, the size of the etch stop layer 25 located on the upper layer is different from the size of the etch stop layer 25 located on the lower layer.

Illustratively, the size of the etching barrier layer 25 on the upper layer is larger than the size of the etching barrier layer 25 on the lower layer, or the size of the etching barrier layer 25 on the upper layer is smaller than the size of the etching barrier layer 25 on the lower layer (as shown in fig. 8, fig. 9, or fig. 10), so that it is beneficial to change the corrosion path and reduce the corrosion rate of the dielectric protection layer 24 at the position near the columnar structure 22, thereby being beneficial to achieving effective protection and support of the dielectric protection layer 24 on the columnar structure 22, and further improving the structural stability of the infrared detector.

In some embodiments, FIG. 11 is a top view of one corrosion-blocking structure in an infrared detector pixel of an embodiment of the disclosure, and FIG. 12 is a top view of another corrosion-blocking structure in an infrared detector pixel of an embodiment of the disclosure. Referring to fig. 11 or 12, the planar layers include separately disposed block structures (the block structures of two different planar layers are shown as 2511 and 2512, respectively); the block structures of the planar layers overlap in projection onto the reflective layer 21 in the axial direction of the columnar structures 22, and surround the columnar structures 22.

Wherein, the block structures of each layer of the planar layer have overlapping projections on the reflective layer 21 along the axial direction of the columnar structure 22, that is, the block structures of each layer of the planar layer have overlapping projections perpendicular to the plane of the reflective layer 21 along the longitudinal direction, which jointly form an annular structure, and the annular structure surrounds the columnar structure 22.

Therefore, in the two adjacent layers of block structures, the edge positions of the two adjacent block structures on the upper layer and the lower layer are staggered, so that the VHF corrosion path is changed, the VHF corrosion rate at the corresponding position is reduced, and the protection of the medium protection layer 24 is realized.

Illustratively, referring to fig. 11, the block structure may be of a fan-blade design; alternatively, referring to fig. 12, the block structure may be of a trapezoidal design; in other embodiments, the block structure may also take other shapes, and is not limited herein.

Illustratively, fig. 11 and 12 each show that each layer of block structures has the same shape, but do not constitute a limitation on the infrared detector pixel provided by the embodiments of the present disclosure. In other embodiments, the block structures located at different layers may be designed in different shapes, and are not limited herein.

In some embodiments, the material comprising etch stop layer 25 comprises at least one of a metallic material or a dielectric material; the metal material comprises at least one of aluminum (Al), copper (Cu), tungsten (W) or titanium-tungsten alloy (TiW); the dielectric material comprises amorphous silicon (a-Si), amorphous germanium (a-Ge), amorphous silicon germanium (a-SiGe), amorphous carbon (a-C), silicon carbide (SiC) or aluminum oxide (Al)₂O₃) At least one of (1).

All the materials are not corroded by the VHF, so that the etching barrier layer 25 cannot be corroded when the sacrificial layer is removed by the VHF corrosion in the subsequent process steps, the medium protection layer 24 covered by the etching barrier layer 25 cannot be corroded, and the medium protection layer 24 is protected; meanwhile, the etching barrier layer 25 is formed by at least one of the above materials, so that the mechanical property of the etching barrier layer 25 is better, and part of the etching barrier layer 25 is positioned between the columnar structure 22 and the medium protective layer 24 and can play a role of auxiliary support, thereby improving the support stability of the columnar structure 22 and enhancing the structural stability of the infrared detector.

In other embodiments, the materials forming the dielectric protection layer 24 and the etching stop layer 25 may also include other materials known to those skilled in the art, which are not limited herein, and can meet the requirements of the infrared detector pixel.

The embodiment of the present disclosure further provides an infrared detector, which includes any one of the above-mentioned infrared detector pixels, and has corresponding beneficial effects, which are not described in detail later.

Exemplarily, fig. 13 is a schematic perspective view of an infrared detector according to an embodiment of the present disclosure. Referring to fig. 13, the infrared detector includes infrared detector pixels 10 arranged in an array.

Illustratively, fig. 13 shows that the infrared detector pixel 10 is arranged in 3 rows and 3 columns, but does not constitute a limitation of the infrared detector provided by the embodiment of the present disclosure.

In other embodiments, the number and arrangement of the infrared detector pixels 10 in the infrared detector can also be set based on the requirement of the infrared detector pixels, which is not limited herein.

In some embodiments, the infrared detector type may be an amorphous silicon detector, a titanium oxide detector, a vanadium oxide detector, or the like, that is, the material constituting the thermosensitive layer may include at least one of amorphous silicon, titanium oxide, or vanadium oxide, which is not limited by the embodiments of the present disclosure.

In some embodiments, fig. 14 is a schematic structural diagram of a CMOS measurement circuit system according to an embodiment of the present disclosure. Referring to fig. 1 and 14, the CMOS measurement circuit system 1 includes a bias voltage generation circuit 7, a column-level analog front-end circuit 8 and a row-level circuit 9, an input end of the bias voltage generation circuit 7 is connected to an output end of the row-level circuit 9, an input end of the column-level analog front-end circuit 8 is connected to an output end of the bias voltage generation circuit 7, the row-level circuit 9 includes a row-level mirror image element Rsm and a row selection switch K1, and the column-level analog front-end circuit 8 includes a blind image element RD; the row-level circuit 9 is distributed in each pixel, selects a signal to be processed according to a row strobe signal of the timing sequence generating circuit, and outputs a current signal to the column-level analog front-end circuit 8 under the action of the bias generating circuit 7 to perform current-voltage conversion output; the row stage circuit 9 outputs a third bias voltage VRsm to the bias generation circuit 7 when being controlled by the row selection switch K1 to be gated, the bias generation circuit 7 outputs a first bias voltage V1 and a second bias voltage V2 according to the input constant voltage and the third bias voltage VRsm, and the column stage analog front-end circuit 8 obtains two currents according to the first bias voltage V1 and the second bias voltage V2, performs transimpedance amplification on the difference between the two generated currents, and outputs the amplified current as an output voltage.

Specifically, the row-level circuit 9 includes a row-level mirror image element Rsm and a row selection switch K1, and the row-level circuit 9 is configured to generate a third bias voltage VRsm according to a gating state of the row selection switch K1. Illustratively, the row-level image elements Rsm may be subjected to a light-shielding process such that the row-level image elements Rsm are subjected to a fixed radiation by a light-shielding sheet having a temperature constantly equal to a substrate temperature, the row selection switch K1 may be implemented by a transistor, the row selection switch K1 is closed, and the row-level image elements Rsm are connected to the bias generation circuit 7, that is, the row-level circuit 9 outputs the third bias voltage VRsm to the bias generation circuit 7 when being gated by the row selection switch K1. The bias generation circuit 7 may include a first bias generation circuit 71 and a second bias generation circuit 72, the first bias generation circuit 71 being configured to generate a first bias voltage V1 according to an input constant voltage, which may be, for example, a positive power supply signal with a constant voltage. The second bias generating circuit 72 may include a bias control sub-circuit 721 and a plurality of gate driving sub-circuits 722, the bias control sub-circuit 721 controlling the gate driving sub-circuits 722 to generate the corresponding second bias voltages V, respectively, according to the third bias voltage VRsm.

The column-level analog front-end circuit 8 includes a plurality of column control sub-circuits 81, the column control sub-circuits 81 are disposed in correspondence with the gate driving sub-circuits 722, and exemplarily, the column control sub-circuits 81 may be disposed in one-to-one correspondence with the gate driving sub-circuits 722, and the gate driving sub-circuits 722 are configured to provide the second bias voltage V2 to the corresponding column control sub-circuits 81 according to their own gate states. For example, it may be set that when the gate driving sub-circuit 722 is gated, the gate driving sub-circuit 722 supplies the second bias voltage V2 to the corresponding column control sub-circuit 81; when the gate driving sub-circuit 722 is not gated, the gate driving sub-circuit 722 stops supplying the second bias voltage V2 to the corresponding column control sub-circuit 81.

The column-level analog front-end circuit 8 comprises an effective pixel RS and a blind pixel RD, the column control sub-circuit is used for generating a first current I1 according to a first bias voltage V1 and the blind pixel RD, generating a second current I2 according to a second bias voltage V2 and the effective pixel RS, performing transimpedance amplification on a difference value of the first current I1 and the second current I2, and outputting the difference value, and the row-level mirror image pixel Rsm and the effective pixel RS have the same temperature drift amount at the same ambient temperature.

Illustratively, the row-level image elements Rsm are thermally insulated from the CMOS measurement circuitry 1 and are shaded, and the row-level image elements Rsm are subjected to a fixed radiation from a shade sheet having a temperature constantly equal to the substrate temperature. The absorption plate 10 of the active pixel RS is thermally insulated from the CMOS measurement circuitry 1 and the active pixel RS receives external radiation. The absorbing plates 10 of the row-level mirror image elements Rsm and the effective elements RS are thermally insulated from the CMOS measuring circuit system 1, so that the row-level mirror image elements Rsm and the effective elements RS have a self-heating effect.

When the corresponding row-level mirror image element Rsm is gated through the row selection switch K1, the resistance value of the row-level mirror image element Rsm and the resistance value of the effective element RS are changed due to joule heat, but when the row-level mirror image element Rsm and the effective element RS are subjected to the same fixed radiation, the resistance value of the row-level mirror image element Rsm and the resistance value of the effective element RS are the same, the temperature coefficients of the row-level mirror image element Rsm and the temperature coefficient of the effective element RS are the same, the temperature drift amounts of the row-level mirror image element Rsm and the effective element RS are the same at the same ambient temperature, the change of the row-level mirror image element Rsm and the temperature drift amounts of the effective element RS at the same ambient temperature are synchronized, the resistance value change of the row-level mirror image element Rsm and the effective element RS due to the self-heating effect is effectively compensated, and the stable output of the reading circuit is achieved.

In addition, by arranging the second bias generating circuit 7 to include a bias control sub-circuit 721 and a plurality of gate driving sub-circuits 722, the bias control sub-circuit 721 is configured to control the gate driving sub-circuits 722 to generate the corresponding second bias voltages V2 respectively according to the row control signals, so that each row of pixels has one path to drive the whole columns of pixels of the row individually, the requirement for the second bias voltage V2 is reduced, that is, the driving capability of the bias generating circuit 7 is improved, and the readout circuit is advantageously used to drive a larger-scale infrared detector pixel array. In addition, the specific detailed operation principle of the CMOS measurement circuit system 1 is well known to those skilled in the art and will not be described herein.

Fig. 15 is a schematic cross-sectional view of another infrared detector according to an embodiment of the disclosure. As shown in fig. 15, on the basis of the above embodiment, the CMOS manufacturing process of the CMOS measurement circuit system 1 may also include a metal interconnection process and a via process, the CMOS measurement circuit system 1 includes metal interconnection layers 101, dielectric layers 102 and a silicon substrate 103 at the bottom, the upper and lower metal interconnection layers 101 are electrically connected through vias 104,

referring to fig. 1 to 15, the CMOS infrared sensing structure 2 includes a resonant cavity formed by a reflective layer 21 and a thermal sensitive medium layer, a suspended microbridge structure for controlling heat transfer, and a pillar structure 22 having electrical connection and support functions, and the CMOS measurement circuit system 1 is configured to measure and process an array resistance value formed by one or more CMOS infrared sensing structures 2, and convert an infrared signal into an electrical image signal.

Specifically, the resonant cavity may be formed by a cavity between the reflective layer 21 and the absorbing plate 2301, for example, infrared light is reflected back and forth in the resonant cavity through the absorbing plate 2301 to improve the detection sensitivity of the infrared detector, and due to the arrangement of the columnar structures 22, the beam structures 2302 and the absorbing plate 2301 constitute a suspended micro-bridge structure for controlling heat transfer, and the columnar structures 22 are electrically connected to the supporting base 211 and the corresponding beam structures 2302 and are used for supporting the infrared conversion structures 23 on the columnar structures 22.

Alternatively, the CMOS infrared sensing structure 2 may be disposed on a metal interconnect layer of the CMOS measurement circuitry 1 or fabricated on the same layer. Specifically, the metal interconnection layer of the CMOS measurement circuitry 1 may be a top metal layer in the CMOS measurement circuitry 1, and in conjunction with fig. 15, the CMOS infrared sensing structure 2 may be fabricated on the metal interconnection layer of the CMOS measurement circuitry 1, and the CMOS infrared sensing structure 2 is electrically connected to the CMOS measurement circuitry 1 through a supporting base 211 on the metal interconnection layer of the CMOS measurement circuitry 1, so as to transmit the electrical signal converted by the infrared signal to the CMOS measurement circuitry 1.

Fig. 16 is a schematic cross-sectional structure view of another infrared detector provided in the embodiment of the present disclosure, and as shown in fig. 16, a CMOS infrared sensing structure 2 is prepared on the same layer of a metal interconnection layer of a CMOS measurement circuit system 1, that is, the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 are arranged on the same layer, as shown in fig. 16, the CMOS infrared sensing structure 2 is arranged on one side of the CMOS measurement circuit system 1, and a hermetic release isolation layer 11 may also be arranged on the top of the CMOS measurement circuit system 1 to protect the CMOS measurement circuit system 1.

Optionally, the CMOS infrared sensing structure 2 includes an absorption plate 2301, a beam structure 2302, a reflective layer 21 and a columnar structure 22, the absorption plate 2301 includes a metal interconnection layer and at least one thermal sensitive medium layer, the material constituting the thermal sensitive medium layer includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, titanium oxide, vanadium oxide or vanadium titanium oxide, the metal interconnection layer in the absorption plate 2301 is an electrode layer in the absorption plate 2301 for transmitting an electrical signal obtained by converting an infrared signal, the thermal sensitive medium layer includes at least a thermal sensitive layer and may further include a support layer and a passivation layer, the material constituting the thermal sensitive medium layer includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, titanium oxide, vanadium oxide or vanadium titanium oxide, that is, the material constituting the thermal sensitive layer includes amorphous silicon, amorphous germanium, amorphous silicon germanium, titanium oxide, vanadium oxide or vanadium oxide, that is to form a thermal sensitive layer, At least one of amorphous germanium, amorphous silicon-germanium, titanium oxide, vanadium oxide or titanium vanadium oxide.

The beam structure 2302 and the columnar structure 22 are used for transmitting electrical signals and for supporting and connecting the absorption plate 2301, the electrode layer in the absorption plate 2301 includes two patterned electrode structures, the two patterned electrode structures output positive electrical signals and ground electrical signals, respectively, the positive electrical signals and the ground electrical signals are transmitted to the supporting base electrically connected with the columnar structure 22 through the different beam structures 2302 and the different columnar structures 22 and further transmitted to the CMOS measurement circuit system 1, the beam structure 2302 includes a metal interconnection layer and at least one dielectric layer, the metal interconnection layer in the beam structure 2302 is an electrode layer in the beam structure 2302, the electrode layer in the beam structure 2302 is electrically connected with the electrode layer in the absorption plate 2301, and the dielectric layer in the beam structure 2302 may include a supporting layer and a passivation layer.

The columnar structures 22 are connected with the beam structure 2302 and the CMOS measurement circuit system 1 by adopting a metal interconnection process and a through hole process, the upper parts of the columnar structures 22 need to be electrically connected with electrode layers in the beam structure 2302 through holes penetrating through a supporting layer in the beam structure 2302, and the lower parts of the columnar structures 22 need to be electrically connected with corresponding supporting bases 211 through holes penetrating through dielectric layers on the supporting bases 211. The reflective plate 212 is used for reflecting infrared signals and forms a resonant cavity with the heat-sensitive medium layer, that is, the reflective plate 212 is used for reflecting infrared signals and forms a resonant cavity with the heat-sensitive medium layer, and the reflective layer 21 includes at least one metal interconnection layer for forming the supporting base 211 and also for forming the reflective plate 212.

Alternatively, at least two ends of the beam structure 2302 and the absorption plate 2301 may be electrically connected, the CMOS infrared sensing structure 2 includes at least two pillar structures 22 and at least two supporting bases 211, and the electrode layer includes at least two electrode terminals. Specifically, as shown in fig. 1, the beam structures 2302 are electrically connected to two ends of the absorption plate 2301, each beam structure 2302 is electrically connected to one end of the absorption plate 2301, the CMOS infrared sensing structure 2 includes two column structures 22, the electrode layer includes at least two electrode terminals, at least a portion of the electrode terminals transmit positive electrical signals, at least a portion of the electrode terminals transmit negative electrical signals, and the signals are transmitted to the supporting base 211 through the corresponding beam structures 2302 and the column structures 22.

Alternatively, with continued reference to fig. 1, it is also possible to provide beam structures 2302 electrically connected to four ends of the absorbing plate 2301, each beam structure 2302 electrically connected to two ends of the absorbing plate 2301, and the CMOS infrared sensing structure 2 includes four columnar structures 22, and one beam structure 2302 connects two columnar structures 22. It should be noted that, in the embodiment of the present disclosure, the number of the connecting ends of the beam structure 2302 and the absorbing plate 2301 is not particularly limited, and it is sufficient that the beam structure 2302 corresponds to the electrode terminals, and the beam structure 2302 is used for transmitting the electrical signals output by the corresponding electrode terminals.

Alternatively, the infrared detector may be configured based on a 3nm, 7nm, 10nm, 14nm, 22nm, 28nm, 32nm, 45nm, 65nm, 90nm, 130nm, 150nm, 180nm, 250nm or 350nm CMOS process, which characterizes process nodes of the integrated circuit, i.e., features during the processing of the integrated circuit.

Alternatively, the metal wiring material constituting the metal interconnection layer in the infrared detector may be configured to include at least one of aluminum, copper, tungsten, titanium, nickel, chromium, platinum, silver, ruthenium, or cobalt, and for example, the material constituting the reflective layer may be configured to include at least one of aluminum, copper, tungsten, titanium, nickel, chromium, platinum, silver, ruthenium, or cobalt. In addition, the CMOS measuring circuit system 1 and the CMOS infrared sensing structure 2 are both prepared by using a CMOS process, the CMOS infrared sensing structure 2 is directly prepared on the CMOS measuring circuit system 1, the radial side length of the columnar structure 22 can be more than or equal to 0.5um and less than or equal to 3um, the width of the beam structure 2302, namely the width of a single line in the beam structure 2302 is less than or equal to 0.3um, the height of a resonant cavity is more than or equal to 1.5um and less than or equal to 2.5um, and the side length of a single pixel of the CMOS infrared sensing structure 2 is more than or equal to 6um and less than or equal to 17 um.

It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The foregoing are merely exemplary embodiments of the present disclosure, which enable those skilled in the art to understand or practice the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An infrared detector pixel based on CMOS technology, comprising:

2. The infrared detector pixel as claimed in claim 1, wherein the CMOS infrared sensing structure comprises a sacrificial layer, the sacrificial layer is used for making the CMOS infrared sensing structure form a hollowed-out structure, the material constituting the sacrificial layer is silicon oxide, and the sacrificial layer is etched by a post-CMOS process;

3. The infrared detector as set forth in claim 1, wherein the etch stop layer comprises a side layer and a planar layer disposed adjacently, the planar layer being disposed in a ring shape, the side layer being disposed in a barrel shape;

4. An infrared detector pixel as claimed in claim 1, wherein a corresponding dielectric protective layer is provided corresponding to each layer of the pillar; the etching barrier layer is at least arranged at the corner position of the uppermost dielectric protection layer.

5. The infrared detector pixel as recited in claim 4, wherein the etch stop layers on the same layer are the same shape and size; and/or

When the etching barrier layer is at least two layers, the shape and the size of the etching barrier layer positioned on each different layer are the same; or

6. The infrared detector pixel of claim 3, wherein the planar layer comprises discretely disposed block-like structures;

7. The infrared detector pixel of claim 1, wherein a material comprising the etch stop layer comprises at least one of a metal material or a dielectric material;

8. The infrared detector pixel of claim 1, wherein each layer of pillars in the same columnar structure is a same type of pillar; and/or

The upright columns on the same layer are all of the same type.

9. The infrared detector pixel of claim 1, wherein the pillars in the columnar structure comprise a bottom layer pillar and a top layer pillar; wherein

Or the bottom layer upright post is a hollow post, and the top layer upright post is a solid metal post or a non-metal solid post;

or the number of the upright columns in the columnar structure is n, wherein n is not less than 3 and is an integer; wherein

The n layers of upright columns are all solid metal columns;

10. An infrared detector pixel as recited in claim 1, wherein the total height of the columnar structures is greater than or equal to 1.5 microns and less than or equal to 2.5 microns; and/or

11. The infrared detector pixel of claim 1, further comprising an adhesion layer,

the adhesion layer at least covers the bottom surface of the columnar structure, which is contacted with the support base;

preferably, the adhesion layer is also positioned between two adjacent upright columns;

preferably, the material constituting the adhesion layer includes at least one of titanium, titanium nitride, tantalum, or tantalum nitride.

12. The infrared detector pixel of claim 1, wherein the sidewall of the hollow pillar is formed by a combination of metal and a medium, and the sidewall of the hollow pillar sequentially comprises a first medium layer, a metal layer and a second medium layer along a radial direction of the hollow pillar;

the second dielectric layer is arranged on one side of the metal layer, which is far away from the first dielectric layer;

the metal material forming the side wall of the hollow column comprises at least one of titanium, titanium nitride, tantalum or tantalum nitride, or the metal material forming the side wall of the hollow column comprises at least one of titanium-tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, nickel-silicon alloy, nickel, chromium or platinum;

the dielectric material for forming the side wall of the hollow column comprises at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon, silicon carbide or aluminum oxide;

the side wall and the bottom of the non-metal solid column are made of metal materials, and a space surrounded by the side wall is filled with non-metal materials;

The non-metal material forming the non-metal solid column comprises at least one of silicon dioxide, silicon nitride, amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon, silicon carbide, silicon carbonitride or aluminum oxide;

the metal material constituting the nonmetal solid column comprises at least one of titanium, titanium nitride, tantalum or tantalum nitride, or at least one of titanium-tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, nickel-silicon alloy, nickel, chromium or platinum;

the material constituting the solid metal pillar includes at least one of aluminum, copper, or tungsten.

13. An infrared detector based on a CMOS process, comprising the infrared detector pixel of any one of claims 1 to 12;

and the infrared detector pixels are arranged in an array.