CN114023879A - Etching method of polycrystalline silicon structure with rough surface - Google Patents

Etching method of polycrystalline silicon structure with rough surface Download PDF

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Publication number
CN114023879A
CN114023879A CN202111219428.1A CN202111219428A CN114023879A CN 114023879 A CN114023879 A CN 114023879A CN 202111219428 A CN202111219428 A CN 202111219428A CN 114023879 A CN114023879 A CN 114023879A
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etching
layer
polycrystalline silicon
dielectric layer
pattern
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孙娟
熊磊
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers

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Abstract

The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to an etching method of a polycrystalline silicon structure with a rough surface. The method comprises the following steps: providing at least one layer of polycrystalline silicon structure with a rough surface, wherein the polycrystalline silicon structure comprises a polycrystalline silicon layer with the rough surface and a dielectric layer covering the rough surface of the polycrystalline silicon layer, and the shape of the dielectric layer is consistent with that of the rough surface of the polycrystalline silicon layer; forming an anti-reflection layer on the dielectric layer; defining an etching pattern on the reflecting layer through a photoetching process, wherein the etching pattern comprises an etching area and a protection area; performing first etching on the basis of the etching pattern, and etching to remove the anti-reflection layer at the position of the etching area to form a first etching stop surface in the dielectric layer, wherein the surface of the first etching stop surface is smooth; performing isotropic second etching based on the etching pattern, and etching to remove the residual dielectric layer at the position of the etching area; and etching and removing the polysilicon layer at the position of the etching area based on the etching pattern.

Description

Etching method of polycrystalline silicon structure with rough surface
Technical Field
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a polycrystalline silicon structure etching method.
Background
A DTC (Deep Trench capacitor) is used for storing charges, and generally includes a plurality of polysilicon plates 110 as shown in fig. 1, a dielectric layer 120 is formed between two adjacent polysilicon plates 110, and the material of the dielectric layer 120 may be an oxide layer manufactured by a thermal oxidation process.
To enable the DTC to store more charge, this can be achieved by increasing the surface area of the polysilicon plate. In the related art, a method of roughening the surface of the polysilicon plate may be employed to effectively increase the surface of the polysilicon plate.
However, the surface roughness of the polysilicon plates is increased in the related art, so that the appearance of the dielectric layer between two adjacent polysilicon plates is fluctuated along with the roughness change of the surfaces of the polysilicon plates to form a convex or concave shape. Therefore, when the polysilicon is etched, the dielectric layer at the position of the protrusion or the recess is difficult to etch and remove, and the dielectric layer which is not etched and removed can block the subsequent etching of the polysilicon polar plate, so that the polysilicon remains. If the scheme of over-etching is adopted to avoid polysilicon residue, the appearance of the polysilicon electrode plate is easily affected adversely, and even the problem of through silicon via occurs.
Disclosure of Invention
The application provides an etching method of a polycrystalline silicon structure with a rough surface, which can solve the problems that in the related technology, an over-etching scheme is adopted to remove polycrystalline silicon residues, the appearance of a polycrystalline silicon polar plate is easily adversely affected, and silicon perforation occurs.
In order to solve the technical problem in the background art, the present application provides an etching method for a polysilicon structure with a rough surface, which includes the following steps:
providing at least one layer of polycrystalline silicon structure with a rough surface, wherein one layer of polycrystalline silicon structure comprises a polycrystalline silicon layer with a rough surface and a dielectric layer covering the rough surface of the polycrystalline silicon layer, and the shape of the dielectric layer is consistent with that of the rough surface of the polycrystalline silicon layer;
forming an anti-reflection layer on the dielectric layer;
defining an etching pattern on the reflecting layer through a photoetching process, wherein the etching pattern comprises an etching area and a protection area;
performing first etching on the basis of the etching pattern, and etching to remove the anti-reflection layer at the position of the etching area to form a first etching stop surface in the dielectric layer, wherein the surface of the first etching stop surface is smooth;
based on the etching pattern, carrying out isotropic second etching, and etching to remove the residual dielectric layer at the position of the etching area;
and etching and removing the polycrystalline silicon layer at the position of the etching area based on the etching pattern.
Optionally, under the same etching condition, the etching rate of the antireflection layer is greater than that of the dielectric layer.
Optionally, under the same etching condition, the etching rate of the antireflection layer is 6 times to 8 times of the etching rate of the dielectric layer.
Optionally, the step of removing the polysilicon layer at the position of the etching region by etching based on the etching pattern includes:
based on the etching pattern, starting to etch the main body of the polycrystalline silicon layer from the upper surface of the polycrystalline silicon layer at the position of the etching area at a first etching rate to form a second etching stop surface in the polycrystalline silicon layer;
based on the etching pattern, etching the bottom of the polycrystalline silicon layer from the second etching stop surface at a second etching rate;
and etching and removing the residual polycrystalline silicon in the polycrystalline silicon layer at a third etching rate based on the etching pattern.
Optionally, under the same etching condition, the second etching rate is greater than the first etching rate.
Optionally, under the same etching condition, the third etching rate is greater than the second etching rate.
Optionally, the step of performing isotropic second etching based on the etching pattern to remove the remaining dielectric layer at the etching region by etching includes:
and based on the etching pattern, performing isotropic second etching at the source power ranging from 200W to 500W, and etching to remove the residual dielectric layer at the position of the etching region.
Optionally, the step of performing isotropic second etching based on the etching pattern to remove the remaining dielectric layer at the etching region by etching includes:
and based on the etching pattern, carrying out isotropic second etching by using a bias voltage with a voltage range of-10V to 10V, and etching to remove the residual dielectric layer at the position of the etching area.
The technical scheme at least comprises the following advantages: performing first etching on the basis of the etching pattern, and etching to remove the anti-reflection layer at the position of the etching area to form a first etching stop surface in the dielectric layer, wherein the surface of the first etching stop surface is smooth; and performing isotropic second etching on the basis of the etching pattern, and etching to remove the residual dielectric layer at the position of the etching area, so that the dielectric layer on the polycrystalline silicon layer with a rough surface can be completely etched and removed, the dielectric layer residue at the part of a sunken or protruded interface is avoided, and the etching of the polycrystalline silicon cannot be blocked due to the residual dielectric layer in the process of etching the polycrystalline silicon layer, so that the surface of the etched polycrystalline silicon is smooth.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 shows a cross-sectional structural view of a DTC in the related art;
FIG. 2 illustrates a method for etching a rough-surfaced polysilicon structure according to an embodiment of the present application;
FIG. 2a is a schematic cross-sectional view of a rough-surfaced polysilicon structure according to an embodiment of the present application;
FIG. 2b is a schematic cross-sectional structure of the device after an anti-reflection layer is coated on the device of FIG. 2 a;
FIG. 2c is a schematic cross-sectional structural view of a device for forming an etching pattern based on FIG. 2 b;
FIG. 2d is a schematic cross-sectional view of a device formed after a first etch based on the etch pattern of FIG. 2 c;
FIG. 2e is a schematic cross-sectional view of the device after a second etching step to remove the remaining dielectric layer at the etching region shown in FIG. 2 d;
FIG. 3a is a schematic diagram illustrating a cross-sectional structure of the device after step S261 is completed;
FIG. 3b is a schematic cross-sectional view of the device after completion of step S262;
fig. 3c shows a schematic cross-sectional structural diagram of the device after step S263 is completed.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Fig. 2 shows a flowchart of a method for etching a polysilicon structure with a rough surface according to an embodiment of the present application, and as can be seen from fig. 2, the method for etching a polysilicon structure with a rough surface includes the following steps that are performed in sequence:
step S21: at least one layer of polysilicon structure with rough surface is provided.
The polycrystalline silicon structure comprises a polycrystalline silicon layer with a rough surface and a dielectric layer covering the rough surface of the polycrystalline silicon layer, and the shape of the dielectric layer is consistent with the rough surface of the polycrystalline silicon layer.
Referring to fig. 2a, a schematic cross-sectional structure diagram of a rugged polysilicon structure provided in an embodiment of the present application is shown. As can be seen from fig. 2a, the present embodiment provides two polysilicon structures stacked one above the other, namely a first polysilicon structure 201 located at an upper layer and a second polysilicon structure 202 located at a lower layer. Each polysilicon structure 201, 202 includes a polysilicon layer 210 with a rough surface, and a dielectric layer 220 covering the rough surface of the polysilicon layer 210, wherein the profile of the dielectric layer 220 is consistent with the profile of the rough surface of the polysilicon layer 210.
The dielectric layer 220 may be an oxide layer grown by a thermal oxidation process, and the thickness of the dielectric layer 220 may range from 70A to 80A.
The first polysilicon structure 201 and the second polysilicon structure 202 may have a thickness in a range of 1000A to 2000A.
Step S22: and forming an anti-reflection layer on the dielectric layer.
In the photoetching process, exposure light can generate light interference phenomenon at the interface position of the layer to be etched and the photoresist layer, so that standing wave effect and multiple exposure are formed in the photoresist layer, the critical dimension CD of an etched pattern formed by the photoresist layer after development cannot be controlled, wavy or zigzag loss occurs on the side wall of the etched pattern, and adverse effect is generated on the subsequent polysilicon etching step performed according to the etched pattern.
Referring to fig. 2b, which shows a schematic cross-sectional structure of the device after the anti-reflection layer is coated on the basis of fig. 2a, it can be seen from fig. 2b that an anti-reflection layer 230 is spin-coated on the dielectric layer 220 of the first polysilicon structure 201 before the photoresist is coated.
The anti-reflection layer 230 absorbs the lithography reflection light during exposure, thereby reducing the problem of light interference, avoiding the formation of standing wave effect and multiple exposure in the photoresist layer, and making the side wall of the etched pattern smooth.
Alternatively, the Anti-Reflective layer 230 may be a BARC (Bottom Anti-Reflective Coating) layer with a thickness ranging from 1500A to 2500A.
Step S23: and defining an etching pattern on the reflecting layer through a photoetching process, wherein the etching pattern comprises an etching area and a protection area.
Referring to fig. 2c, a schematic cross-sectional structure of the device for forming an etching pattern based on fig. 2b is shown. As can be seen from fig. 2c, a photoresist 300 is coated on the upper surface of the anti-reflection layer 230 shown in fig. 2b, and after the photoresist 300 is etched by photolithography, the photoresist 30 defines an etching pattern. The etching pattern includes an etching region 310 and a protection region 320, the surface of the anti-reflection layer 230 at the position of the etching region 310 is exposed and not covered with the photoresist 300, and the anti-reflection layer 230 at the position of the protection region 320 is covered with the photoresist 300, and the photoresist 300 can protect the polysilicon structure at the position of the protection region 320 from being etched.
Alternatively, the photoresist 300 may have a thickness of 10000A to 15000A.
Step S24: and performing first etching on the basis of the etching pattern, and etching to remove the anti-reflection layer at the position of the etching area to form a first etching stop surface in the dielectric layer, wherein the surface of the first etching stop surface is smooth.
Referring to fig. 2d, a schematic cross-sectional structure of the device formed after the first etching based on the etching pattern shown in fig. 2c is shown. As can be seen from fig. 2d, after the first etching, the anti-reflection layer 230 and a portion of the dielectric layer 220 of the first polysilicon structure 201 in the etching region 310 are removed by etching, so that the first etch stop surface 410 of the first etching is located in the dielectric layer 220 of the first polysilicon structure 201, and the surface of the first etch stop surface 410 is smooth.
Illustratively, the etch rate for the antireflective layer is greater than the etch rate for the dielectric layer under the same etch conditions, so that a smooth first etch stop surface 410 can be formed when etching the undulated interface of antireflective layer 230 and dielectric layer 220.
Optionally, the etch rate of antireflective layer 230 is 6 to 8 times the etch rate of dielectric layer 220 under the same etch conditions.
HBr and oxygen O including hydrobromic acid can be used2The first etching is performed with the etching gas.
Step S25: and performing isotropic second etching based on the etching pattern, and etching to remove the residual dielectric layer at the position of the etching area.
Referring to fig. 2e, which shows a schematic cross-sectional structure of the device after the second etching to remove the remaining dielectric layer at the position of the etching region shown in fig. 2d, it can be seen from fig. 2e that, because the second etching uses an isotropic etching process, the remaining dielectric layer 220 on the polysilicon layer 210 with a rough surface at the position of the etching region 310 can be completely etched and removed, so that the dielectric layer 220 at the partial concave or convex interface is prevented from remaining. The upper surface of the polysilicon layer 210 of the first polysilicon structure 201 after the second etching is completed is exposed.
Illustratively, the source power of the etching process may be in a range of 200W to 500W and the bias voltage may be in a range of-10V to 10V during the second etching process, so that the dielectric layer 220 remaining on the polysilicon layer 210 with the rough surface can be completely etched and removed, and the dielectric layer 220 at the interface of the recess or the protrusion is prevented from remaining.
Step S26: and etching and removing the polycrystalline silicon layer at the position of the etching area based on the etching pattern.
In the embodiment, the first etching is carried out based on the etching pattern, the anti-reflection layer at the position of the etching area is removed by etching, a first etching stop surface in the dielectric layer is formed, and the surface of the first etching stop surface is smooth; and performing isotropic second etching on the basis of the etching pattern, and etching to remove the residual dielectric layer at the position of the etching area, so that the dielectric layer on the polycrystalline silicon layer with a rough surface can be completely etched and removed, the dielectric layer residue at the part of a sunken or protruded interface is avoided, and the etching of the polycrystalline silicon cannot be blocked due to the residual dielectric layer in the process of etching the polycrystalline silicon layer, so that the surface of the etched polycrystalline silicon is smooth.
In order to completely etch away the polysilicon layer 210 of the first polysilicon structure 201 at the location of the etched region 310, in step S26: the process of removing the polysilicon layer at the etching region by etching based on the etching pattern may include the following steps performed in sequence:
step S261: and starting to etch the main body of the polycrystalline silicon layer from the upper surface of the polycrystalline silicon layer at the position of the etching area at a first etching rate based on the etching pattern to form a second etching stop surface in the polycrystalline silicon layer.
Referring to fig. 3a, a schematic cross-sectional structural diagram of the device after step S261 is completed is illustrated. As can be seen from fig. 3a, step S261 is performed on the basis of the device structure shown in fig. 2e, so that the polysilicon layer 210 of the first polysilicon structure 201, a body portion from the upper surface thereof downwards is etched away, and a second etch stop surface 420 located in the polysilicon layer 210 is formed. The second etch stop surface 420 is also located a distance from the lower surface of the polysilicon layer 210.
Step S262: and based on the etching pattern, etching the bottom of the polycrystalline silicon layer from the second etching stop surface at a second etching rate.
Referring to fig. 3b, a schematic cross-sectional structural diagram of the device after step S262 is completed is shown. As can be seen from fig. 3b, step S262 is performed on the basis of the device structure shown in fig. 3a, so that the bottom of the polysilicon layer 210, which is downward from the second etch stop surface 420, is etched away.
However, since the first polysilicon structure 201 is located on the second polysilicon structure 202 with a rough surface, the lower surface of the polysilicon layer 210 of the first polysilicon structure 201 is rough and has an uneven shape, so that at the second etching rate, after the bottom etching of the polysilicon layer 210 is completed from the second etching stop surface 420, polysilicon still remains in the recess on the upper surface of the second polysilicon structure 202 and is not removed by etching.
Step S263: and etching and removing the residual polycrystalline silicon in the polycrystalline silicon layer at a third etching rate based on the etching pattern.
Referring to fig. 3c, a schematic cross-sectional structural diagram of the device after step S263 is completed is shown. As can be seen from fig. 3c, step S263 is performed on the basis of the device structure shown in fig. 3b, so that the remaining polysilicon of the polysilicon layer 210 at the location of the etched region 310 in fig. 3b is completely etched away.
Optionally, under the same etching condition, the second etching rate is greater than the first etching rate, and under the same etching condition, the third etching rate is greater than the second etching rate.
In the embodiment, the polycrystalline silicon layer of the first polycrystalline silicon structure is etched sequentially at three different etching rates, so that the polycrystalline silicon layer is completely etched and removed while the morphology of the polycrystalline silicon layer is prevented from being damaged and the silicon perforation is avoided, and the residue is avoided.
After the etching of the polysilicon layer of the first polysilicon structure at the etching region is completed, the steps S22 to S26 and the steps S261 to S263 may be repeated to etch the first polysilicon structure 202, which is not described herein again.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims (8)

1. The method for etching the polycrystalline silicon structure with the rough surface is characterized by comprising the following steps of:
providing at least one layer of polycrystalline silicon structure with a rough surface, wherein one layer of polycrystalline silicon structure comprises a polycrystalline silicon layer with a rough surface and a dielectric layer covering the rough surface of the polycrystalline silicon layer, and the shape of the dielectric layer is consistent with that of the rough surface of the polycrystalline silicon layer;
forming an anti-reflection layer on the dielectric layer;
defining an etching pattern on the reflecting layer through a photoetching process, wherein the etching pattern comprises an etching area and a protection area;
performing first etching on the basis of the etching pattern, and etching to remove the anti-reflection layer at the position of the etching area to form a first etching stop surface in the dielectric layer, wherein the surface of the first etching stop surface is smooth;
based on the etching pattern, carrying out isotropic second etching, and etching to remove the residual dielectric layer at the position of the etching area;
and etching and removing the polycrystalline silicon layer at the position of the etching area based on the etching pattern.
2. The method of claim 1, wherein the etching rate of the anti-reflective layer is greater than the etching rate of the dielectric layer under the same etching condition.
3. The method of claim 2, wherein the etching rate of the anti-reflection layer is 6 to 8 times of the etching rate of the dielectric layer under the same etching condition.
4. The method of etching a rough-surface polysilicon structure according to claim 1, wherein the step of removing the polysilicon layer at the location of the etched region by etching based on the etching pattern comprises:
based on the etching pattern, starting to etch the main body of the polycrystalline silicon layer from the upper surface of the polycrystalline silicon layer at the position of the etching area at a first etching rate to form a second etching stop surface in the polycrystalline silicon layer;
based on the etching pattern, etching the bottom of the polycrystalline silicon layer from the second etching stop surface at a second etching rate;
and etching and removing the residual polycrystalline silicon in the polycrystalline silicon layer at a third etching rate based on the etching pattern.
5. The method of claim 4, wherein the second etch rate is greater than the first etch rate under the same etch conditions.
6. The method of claim 5, wherein the third etching rate is greater than the second etching rate under the same etching condition.
7. The method for etching a polysilicon structure with a rough surface according to claim 1, wherein the step of performing isotropic second etching based on the etching pattern to remove the remaining dielectric layer at the position of the etching region by etching comprises:
and based on the etching pattern, performing isotropic second etching at the source power ranging from 200W to 500W, and etching to remove the residual dielectric layer at the position of the etching region.
8. The method for etching the polysilicon structure with the rough surface according to claim 7, wherein the step of performing isotropic second etching based on the etching pattern to remove the dielectric layer remaining at the etching region by etching comprises:
and based on the etching pattern, carrying out isotropic second etching by using a bias voltage with a voltage range of-10V to 10V, and etching to remove the residual dielectric layer at the position of the etching area.
CN202111219428.1A 2021-10-20 2021-10-20 Etching method of polycrystalline silicon structure with rough surface Pending CN114023879A (en)

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