CN115440734A - Method for manufacturing flash memory device - Google Patents
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- CN115440734A CN115440734A CN202211215827.5A CN202211215827A CN115440734A CN 115440734 A CN115440734 A CN 115440734A CN 202211215827 A CN202211215827 A CN 202211215827A CN 115440734 A CN115440734 A CN 115440734A
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Abstract
The invention provides a manufacturing method of a flash memory device, wherein a plurality of separated floating gate structures are formed in a memory cell area of a substrate, and each floating gate structure comprises a floating gate and a floating gate mask layer which are sequentially formed on the surface of the substrate; forming a protective layer, wherein the protective layer covers the floating gate structure and the substrate at two sides of the floating gate structure; and etching the substrates on two sides of the floating gate structure to form an isolation groove. According to the invention, the floating gate is protected in the groove etching process by forming the protective layer, and the lateral line width loss of the floating gate is reduced, so that the appearance of the floating gate is improved, the process window of the subsequent process is further improved, and the performance and yield of the flash memory device are improved. Furthermore, the thickness of the floating gate mask layer is controlled to be 60% -80% of the thickness of the floating gate, the line width uniformity of the floating gate is improved by controlling the thickness of the floating gate mask layer, and the appearance of the floating gate is further improved.
Description
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a manufacturing method of a flash memory device.
Background
The existing flash memory structure, taking a NAND flash memory structure as an example, generally includes a memory cell region and a peripheral region, where the memory cell region includes the most basic data memory cells, and is usually characterized by memory transistors, and the peripheral region includes a logic control unit, and may include a high voltage P-type MOS transistor (HVPMOS), a high voltage N-type MOS transistor (HVNMOS), a low voltage P-type MOS transistor (LVPMOS), a low voltage N-type MOS transistor (LVNMOS), and so on.
Currently, in order to increase the storage density of a memory cell region, a flash memory device has entered a 1 × Generation node, i.e., a feature size of a memory transistor is between 16nm and 19 nm. Referring to fig. 1, in order to form a memory transistor device conforming to the feature size, the memory Cell region (i.e., cell region) X1 is formed by Self-aligned Double imaging (SADP) to form a first mask Pattern (Pattern) 11 having a final feature size (Pitch) of 52nm and a second mask Pattern (Pattern) 12 of the peripheral region (i.e., peri region) X2, so as to separately etch the memory Cell region X1 and the peripheral region X2, as defined by the ArF exposure limit during photolithography.
With the reduction of the critical dimension of the flash memory device, the sensitivity of the electrical property of the device to the shape change in the flash memory device is gradually improved. For example, referring to fig. 2, in the memory cell region X1, the sidewalls of the floating gates 13 are perpendicular to the surface of the substrate 10, and the shallow trenches 14 have a Vertical U-Shape (Vertical U-Shape) which has a great advantage in controlling the uniformity of line width. However, in the conventional process, the floating gate 13 is usually formed first and then the shallow trench 14 is formed, the floating gate 13 and the substrate 10 are both made of silicon, and the floating gate 13 is in an exposed state, so that the floating gate 13 is inevitably damaged in the subsequent process of etching the substrate 10 to form the shallow trench 14, and the electrical performance of the finally formed flash memory device is affected. In addition, referring to fig. 3, in the subsequent process of forming the gate 20, the topography of the floating gate 13 will also affect the process window and leakage performance of the etching of the gate 20, and the height of the floating gate 13 will also affect the electrical coupling ratio of the finally formed flash memory device.
In view of the above, there is a need for a method to improve the floating gate topography to improve the process window of the subsequent process and the performance of the finally formed flash memory device.
Disclosure of Invention
The invention aims to provide a manufacturing method of a flash memory device, which reduces or avoids lateral line width loss of a floating gate in a groove etching process, improves line width uniformity and improves floating gate appearance of the flash memory device.
In order to achieve the above object, the present invention provides a method of manufacturing a flash memory device, including:
providing a substrate, wherein a plurality of separated floating gate structures are formed on the surface of a storage unit area of the substrate, and each floating gate structure comprises a floating gate and a floating gate mask layer which are sequentially formed on the surface of the substrate;
forming a protective layer, wherein the protective layer covers the floating gate structure and the substrates on two sides of the floating gate structure; and the number of the first and second groups,
and etching the substrates at two sides of the floating gate structure to form an isolation groove.
Optionally, the protective layer is formed by an atomic layer deposition process.
Optionally, the thickness of the floating gate mask layer is 60% to 80% of the thickness of the floating gate.
Optionally, the process of forming a plurality of floating gate structures on the surface of the memory cell region of the substrate includes:
forming a floating gate material layer, a floating gate mask layer and an amorphous silicon layer on the substrate in sequence;
forming a side wall pattern on the amorphous silicon layer in the memory unit region;
etching the amorphous silicon layer and the floating gate mask layer by taking the side wall pattern as a mask, and transferring the pattern of the side wall pattern to the amorphous silicon layer and the floating gate mask layer; and the number of the first and second groups,
and etching the floating gate material layer by taking the amorphous silicon layer and the floating gate mask layer as masks to form a plurality of floating gate structures.
Optionally, the sidewall patterns are formed by a self-aligned dual imaging process.
Optionally, after the forming the floating gate structure, the method further includes:
and carrying out a wet cleaning process to remove by-products in the etching process.
Optionally, the etchant of the wet cleaning process is dilute hydrofluoric acid.
Optionally, the floating gate mask layer includes a first mask layer and a second mask layer from bottom to top.
Optionally, the first mask layer is a silicon nitride layer, and the second mask layer is a silicon oxide layer.
Optionally, the manufacturing method of the flash memory device is used for manufacturing a NAND flash memory.
In summary, the present invention provides a method for manufacturing a flash memory device, in which a plurality of separated floating gate structures are formed in a memory cell region of a substrate, and each floating gate structure includes a floating gate and a floating gate mask layer sequentially formed on a surface of the substrate; forming a protective layer, wherein the protective layer covers the floating gate structure and the substrate at two sides of the floating gate structure; and etching the substrates on two sides of the floating gate structure to form an isolation groove. According to the invention, the floating gate is protected in the groove etching process by forming the protective layer, and the lateral line width loss of the floating gate is reduced, so that the appearance of the floating gate is improved, the process window of the subsequent process is further improved, and the performance and yield of the flash memory device are improved.
Furthermore, the thickness of the floating gate mask layer is controlled to be 60% -80% of the thickness of the floating gate, the line width uniformity of the floating gate is improved by controlling the thickness of the floating gate mask layer, and the appearance of the floating gate is further improved.
Drawings
FIG. 1 is a schematic diagram of a flash memory device before a floating gate is fabricated;
FIG. 2 is a schematic diagram of a flash memory device after fabrication of a floating gate and a trench;
FIG. 3 is a schematic diagram of a corresponding three-dimensional structure of a flash memory device after gate etching;
FIG. 4 is a flow chart of a method for manufacturing a flash memory device according to an embodiment of the present invention;
fig. 5 to fig. 13 are schematic structural diagrams corresponding to steps in a method for manufacturing a flash memory device according to an embodiment of the present invention;
wherein the reference numbers are as follows:
10-a substrate; 11 — a first mask pattern; 12-a second mask pattern; 13-floating gate; 14-shallow trench; 20-a gate;
100-a substrate; 101-an isolation trench; 110-a dielectric layer; 120-a layer of floating gate material; 121-floating gate; 130-floating gate mask layer; 131-a first mask layer; 132-a second mask layer; 140-an amorphous silicon layer; 150-a sacrificial layer; 151-an anti-reflection layer; 152-a first photoresist layer; 153-side wall pattern; 154-a second photoresist layer; 160-a protective layer;
x1-memory cell area; x2-peripheral region; a-a floating gate structure.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is provided for the purpose of facilitating and clearly illustrating embodiments of the present invention.
Fig. 4 is a flowchart of a method for manufacturing a flash memory device according to an embodiment of the invention. Referring to fig. 4, the method for manufacturing the flash memory device according to the present embodiment includes:
step S01: providing a substrate, wherein a plurality of separated floating gate structures are formed on the surface of a storage unit area of the substrate, and each floating gate structure comprises a floating gate and a floating gate mask layer which are sequentially formed on the surface of the substrate;
step S02: forming a protective layer, wherein the protective layer covers the floating gate structure and the substrates on two sides of the floating gate structure; and the number of the first and second groups,
step S03: and etching the substrates on two sides of the floating gate structure to form an isolation groove.
Fig. 5 to fig. 13 are schematic structural diagrams corresponding to steps in a manufacturing method of a flash memory device according to an embodiment of the present invention, and the manufacturing method of the flash memory device according to the embodiment is described in detail below with reference to fig. 5 to fig. 13.
First, referring to fig. 5 to 11, step S01 is performed to provide a substrate 100, wherein a plurality of separated floating gate structures a are formed on a surface of a memory cell region X1 of the substrate 100, and the floating gate structures a include a floating gate 121 and a floating gate mask layer 130 which are sequentially formed on the surface of the substrate 100. In this embodiment, the substrate 100 includes the memory cell region X1 and the peripheral region X2.
Specifically, the process of forming the floating gate structure a includes the following steps.
First, referring to fig. 5, a floating gate material layer 120, a floating gate mask layer 130, and an amorphous silicon layer 140 are sequentially formed on the substrate 100. Optionally, a dielectric layer 110 is further formed between the substrate 100 and the floating gate material layer 120.
In this embodiment, the substrate 100 is a silicon substrate, the dielectric layer 110 is a silicon oxide layer, the floating gate material layer 120 is a polysilicon layer, and the floating gate mask layer 130 includes a first mask layer 131 and a second mask layer 132 from bottom to top, where the first mask layer 131 is a silicon nitride layer, and the second mask layer 132 is a silicon oxide layer, in other embodiments of the present invention, the materials of the substrate 100, the dielectric layer 110, the first mask layer 131, and the second mask layer 132 may be adjusted according to actual needs, for example, the material of the second mask layer 132 may also be Tetraethoxysilane (TEOS), which is not limited in this respect. It should be noted that the thickness of the floating gate mask layer 130 is 60% to 80% of the thickness of the floating gate 121, so as to improve the line width uniformity of the floating gate formed subsequently.
Next, referring to fig. 6 to 9, a sidewall spacer pattern 153 is formed on the amorphous silicon layer 140 in the memory cell region X1. In this embodiment, the sidewall patterns 153 are formed by a Self-aligned Double Patterning (SADP) process. Specifically, referring to fig. 6, a sacrificial layer 150, an anti-reflection layer 151, and a first photoresist layer 152 are sequentially formed on the amorphous silicon layer 140; referring to fig. 7, the anti-reflection layer 151 and the sacrificial layer 150 are etched using the first photoresist layer 152 as a mask to transfer a pattern on the first photoresist layer 152 onto the sacrificial layer 150; referring to fig. 8, a spacer material layer (not shown) is deposited on the amorphous silicon layer 140 and the sacrificial layer 150, and the spacer material layer is etched to form a spacer pattern 153 on the sidewall of the sacrificial layer 150; referring to fig. 9, the sacrificial layer 150 is removed. Optionally, in the self-aligned dual imaging process, the sidewall material Layer may be formed by using an Atomic Layer Deposition (ALD) process, the sidewall pattern 153 may be formed by using a dry etching process, and the sacrificial Layer 150 may be removed by using a wet etching process. It should be noted that, in other embodiments of the present invention, other process steps and methods may be adopted to form the sidewall patterns 153, which is not limited in the present invention.
Subsequently, referring to fig. 9 and 10, the amorphous silicon layer 140 and the floating gate mask layer 130 are etched using the sidewall patterns 153 as masks, and the patterns of the sidewall patterns 153 are transferred onto the amorphous silicon layer 140 and the floating gate mask layer 130. It should be noted that, because the sidewall patterns 153 formed by etching are located in the device unit region X1, before the etching, a second photoresist layer 154 covering the peripheral region X2 is further formed, so as to prevent each film layer in the peripheral region X2 from being damaged in the etching process. Optionally, the sidewall patterns 153 are removed together in the etching process, the second photoresist layer 154 may be completely removed in the etching process, or may be partially removed in the etching process, and the remaining part of the second photoresist layer 154 may be completely removed in an ashing process and a wet cleaning process after the gate structure is formed.
Next, referring to fig. 11, the amorphous silicon layer 140 and the floating gate mask layer 130 are used as masks to etch and form the floating gate material layer 120, so as to form a plurality of floating gate structures a, which include the floating gates 121 and the floating gate mask layer 130 on the floating gates 121. In this embodiment, the floating gate mask layer 130 and the floating gate material layer 120 are etched by a dry etching process to form the floating gate structure a. Optionally, the amorphous silicon layer 140 is completely removed during the etching process.
Optionally, after the floating gate structure a is formed by using the self-aligned etching process as described above, a wet cleaning process may be performed to remove a byproduct in the current etching process, and an etchant of the wet cleaning process is Dilute Hydrofluoric Acid (DHF).
Next, referring to fig. 12, step S02 is performed to form a protective layer 160, where the protective layer 160 covers the floating gate structure a and the substrate 100 on both sides of the floating gate structure a. In this embodiment, the protection layer 160 is formed by using an Atomic Layer Deposition (ALD) process to improve the uniformity of the protection layer 160, and the protection layer 160 covers the top and the sidewall of the floating gate structure a, so as to protect the floating gate 121 in the subsequent process of forming the isolation trench and reduce the lateral line width loss of the floating gate 121. In this embodiment, the protection layer 160 is an oxide layer, and the material forming the protection layer 160 may be silicon oxide, tetraethoxysilane or other commonly used oxide materials in a semiconductor process, which is not limited in the present invention.
Subsequently, referring to fig. 13, step S03 is performed to etch the substrate 100 at two sides of the floating gate structure a to form an isolation trench 101. In this embodiment, a Self-aligned (Self-aligned) etching process with a high selectivity ratio is adopted to etch the substrate 100 on both sides of the floating gate structure a step by step to form the isolation trench 101. Optionally, after the self-aligned etching process, a wet cleaning process may be performed to remove a byproduct in the etching process, and an etchant of the wet cleaning process is diluted hydrofluoric acid.
With reference to fig. 13, in the present embodiment, by controlling the thickness of the floating gate mask layer 130, the line width uniformity of the floating gate 121 is improved, and by forming the uniform protection layer 160 on the floating gate structure, the damage of the floating gate structure a in the etching process of the isolation trench 101 is reduced or avoided, and the lateral line width loss of the floating gate 121 is reduced, so that the floating gate morphology is improved, the process window of the subsequent process is further improved, and the performance and yield of the flash memory device are improved. In this embodiment, the method for manufacturing the flash memory device is used to manufacture a NAND flash memory, and in other embodiments of the present invention, the method for manufacturing the flash memory device may be used to manufacture other flash memory devices or other semiconductor devices with the same or similar structures, which is not limited in this respect.
In summary, the present invention provides a method for manufacturing a flash memory device, in which a plurality of separated floating gate structures are formed in a memory cell region of a substrate, and each floating gate structure includes a floating gate and a floating gate mask layer sequentially formed on a surface of the substrate; forming a protective layer, wherein the protective layer covers the floating gate structure and the substrate at two sides of the floating gate structure; and etching the substrates at two sides of the floating gate structure to form an isolation groove. According to the invention, the floating gate is protected in the groove etching process by forming the protective layer, and the lateral line width loss of the floating gate is reduced, so that the appearance of the floating gate is improved, the process window of the subsequent process is further improved, and the performance and yield of the flash memory device are improved.
Furthermore, the thickness of the floating gate mask layer is controlled to be 60% -80% of the thickness of the floating gate, the line width uniformity of the floating gate is improved by controlling the thickness of the floating gate mask layer, and the morphology of the floating gate is further improved.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method of manufacturing a flash memory device, comprising:
providing a substrate, wherein a plurality of separated floating gate structures are formed on the surface of a storage unit area of the substrate, and each floating gate structure comprises a floating gate and a floating gate mask layer which are sequentially formed on the surface of the substrate;
forming a protective layer, wherein the protective layer covers the floating gate structure and the substrate at two sides of the floating gate structure; and the number of the first and second groups,
and etching the substrates on two sides of the floating gate structure to form an isolation groove.
2. The method of manufacturing a flash memory device according to claim 1, wherein the protective layer is formed using an atomic layer deposition process.
3. The method of manufacturing a flash memory device according to claim 1 or 2, wherein a thickness of the floating gate mask layer is 60% to 80% of a thickness of the floating gate.
4. The method of manufacturing a flash memory device according to claim 3, wherein the process of forming a plurality of floating gate structures on the surface of the memory cell region of the substrate comprises:
forming a floating gate material layer, a floating gate mask layer and an amorphous silicon layer on the substrate in sequence;
forming a side wall pattern on the amorphous silicon layer in the storage unit area;
etching the amorphous silicon layer and the floating gate mask layer by taking the side wall pattern as a mask, and transferring the pattern of the side wall pattern to the amorphous silicon layer and the floating gate mask layer; and (c) a second step of,
and etching the floating gate material layer by taking the amorphous silicon layer and the floating gate mask layer as masks to form a plurality of floating gate structures.
5. The method of manufacturing a flash memory device according to claim 4, wherein the sidewall patterns are formed using a self-aligned dual imaging process.
6. The method of manufacturing a flash memory device of claim 4, further comprising, after forming the floating gate structure:
and carrying out a wet cleaning process to remove by-products in the etching process.
7. The method of manufacturing a flash memory device according to claim 6, wherein an etchant of the wet cleaning process is diluted hydrofluoric acid.
8. The method of manufacturing a flash memory device according to claim 4, wherein the floating gate mask layer comprises a first mask layer and a second mask layer from bottom to top.
9. The method of manufacturing a flash memory device according to claim 8, wherein the first mask layer is a silicon nitride layer, and the second mask layer is a silicon oxide layer.
10. The method of manufacturing a flash memory device according to claim 1, wherein the method of manufacturing a flash memory device is used to manufacture a NAND flash memory.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211215827.5A CN115440734A (en) | 2022-09-30 | 2022-09-30 | Method for manufacturing flash memory device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211215827.5A CN115440734A (en) | 2022-09-30 | 2022-09-30 | Method for manufacturing flash memory device |
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| CN115440734A true CN115440734A (en) | 2022-12-06 |
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| CN202211215827.5A Pending CN115440734A (en) | 2022-09-30 | 2022-09-30 | Method for manufacturing flash memory device |
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