CN113875007A - 用于复杂逻辑单元的紧凑3d堆叠cfet架构 - Google Patents

用于复杂逻辑单元的紧凑3d堆叠cfet架构 Download PDF

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Publication number
CN113875007A
CN113875007A CN202080039123.XA CN202080039123A CN113875007A CN 113875007 A CN113875007 A CN 113875007A CN 202080039123 A CN202080039123 A CN 202080039123A CN 113875007 A CN113875007 A CN 113875007A
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gate
semiconductor device
stack
substrate
split
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Chinese (zh)
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拉尔斯·利布曼
杰弗里·史密斯
安东·德维利耶
丹尼尔·沙内穆加梅
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H03K19/215EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149Source or drain regions of field-effect devices
    • H10D62/151Source or drain regions of field-effect devices of IGFETs 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0186Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85Complementary IGFETs, e.g. CMOS
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85Complementary IGFETs, e.g. CMOS
    • H10D84/856Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00Three-dimensional [3D] integrated devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00Three-dimensional [3D] integrated devices
    • H10D88/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/20Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42Vias, e.g. via plugs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/427Power or ground buses
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135Manufacturing their gate conductors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172Manufacturing their gate conductors

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Geometry (AREA)
  • Logic Circuits (AREA)
CN202080039123.XA 2019-05-31 2020-05-22 用于复杂逻辑单元的紧凑3d堆叠cfet架构 Pending CN113875007A (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201962855374P 2019-05-31 2019-05-31
US62/855,374 2019-05-31
US16/849,630 US11437376B2 (en) 2019-05-31 2020-04-15 Compact 3D stacked-CFET architecture for complex logic cells
US16/849,630 2020-04-15
PCT/US2020/034134 WO2020242909A1 (en) 2019-05-31 2020-05-22 Compact 3d stacked cfet architecture for complex logic cells

Publications (1)

Publication Number Publication Date
CN113875007A true CN113875007A (zh) 2021-12-31

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US (1) US11437376B2 (https=)
JP (1) JP7680812B2 (https=)
KR (1) KR102780323B1 (https=)
CN (1) CN113875007A (https=)
TW (1) TWI861115B (https=)
WO (1) WO2020242909A1 (https=)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11469321B2 (en) 2020-02-27 2022-10-11 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device
US11714945B2 (en) 2020-04-09 2023-08-01 Tokyo Electron Limited Method for automated standard cell design
US11550985B2 (en) 2020-04-09 2023-01-10 Tokyo Electron Limited Method for automated standard cell design
US11961802B2 (en) 2020-12-04 2024-04-16 Tokyo Electron Limited Power-tap pass-through to connect a buried power rail to front-side power distribution network
US12374623B2 (en) * 2021-01-18 2025-07-29 Samsung Electronics Co., Ltd. Stacked semiconductor device architecture
US12046643B2 (en) * 2021-09-20 2024-07-23 International Business Machines Corporation Semiconductor structures with power rail disposed under active gate
EP4167275A1 (en) 2021-10-18 2023-04-19 Imec VZW A method for forming an interconnection structure
US12336294B2 (en) 2021-11-10 2025-06-17 International Business Machines Corporation Gate-cut and separation techniques for enabling independent gate control of stacked transistors
US11894436B2 (en) * 2021-12-06 2024-02-06 International Business Machines Corporation Gate-all-around monolithic stacked field effect transistors having multiple threshold voltages
KR102892844B1 (ko) 2022-01-10 2025-12-02 엘지전자 주식회사 무선 통신 시스템에서 신호 송수신 방법 및 장치
US12218135B2 (en) 2022-01-13 2025-02-04 Tokyo Electron Limited Wiring in diffusion breaks in an integrated circuit
US12588489B2 (en) 2022-02-25 2026-03-24 Samsung Electronics Co., Ltd. Integrated circuit devices including stacked elements and methods of forming the same
US12349458B2 (en) 2022-03-22 2025-07-01 International Business Machines Corporation Staggered stacked circuits with increased effective width
US12131996B2 (en) 2022-03-28 2024-10-29 Samsung Electronics Co., Ltd. Stacked device with backside power distribution network and method of manufacturing the same
US12490480B2 (en) 2022-09-16 2025-12-02 International Business Machines Corporation Stacked FETS with contact placeholder structures
KR20240167169A (ko) * 2023-05-19 2024-11-26 삼성전자주식회사 반도체 장치
WO2025083833A1 (ja) * 2023-10-19 2025-04-24 株式会社ソシオネクスト 半導体装置
WO2025083834A1 (ja) * 2023-10-19 2025-04-24 株式会社ソシオネクスト 半導体装置
WO2025083832A1 (ja) * 2023-10-19 2025-04-24 株式会社ソシオネクスト 半導体装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050184292A1 (en) * 2004-02-24 2005-08-25 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor integrated circuits using selective epitaxial growth and partial planarization techniques and semiconductor integrated circuits fabricated thereby
CN101257024A (zh) * 2006-09-14 2008-09-03 三星电子株式会社 具有三维排列的存储单元晶体管的与非型闪存器件
US20140091321A1 (en) * 2012-09-28 2014-04-03 Sony Corporation Semiconductor device, solid-state imaging device, and method of manufacturing semiconductor device
US20170345909A1 (en) * 2014-07-14 2017-11-30 Unisantis Electronics Singapore Pte. Ltd. Semiconductor device

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100663360B1 (ko) 2005-04-20 2007-01-02 삼성전자주식회사 박막 트랜지스터를 갖는 반도체 소자들 및 그 제조방법들
US8314001B2 (en) 2010-04-09 2012-11-20 International Business Machines Corporation Vertical stacking of field effect transistor structures for logic gates
JP5956736B2 (ja) 2011-10-18 2016-07-27 日本放送協会 積層型半導体装置及びその製造方法
WO2014141485A1 (ja) * 2013-03-15 2014-09-18 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Sgtを有する半導体装置の製造方法
JP2014222740A (ja) 2013-05-14 2014-11-27 株式会社東芝 半導体記憶装置
WO2015068226A1 (ja) * 2013-11-06 2015-05-14 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Sgtを有する半導体装置と、その製造方法
WO2015155656A1 (en) 2014-04-11 2015-10-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device
JP6065190B2 (ja) * 2014-09-05 2017-01-25 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. 半導体装置
US9666562B2 (en) * 2015-01-15 2017-05-30 Qualcomm Incorporated 3D integrated circuit
US9691695B2 (en) * 2015-08-31 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure
US9570395B1 (en) * 2015-11-17 2017-02-14 Samsung Electronics Co., Ltd. Semiconductor device having buried power rail
US9646989B1 (en) 2015-11-18 2017-05-09 Kabushiki Kaisha Toshiba Three-dimensional memory device
KR101855846B1 (ko) 2015-12-29 2018-05-09 포항공과대학교 산학협력단 수직적층구조의 3차원 정적램 코어 셀 및 그를 포함하는 정적램 코어 셀 어셈블리
US9941200B1 (en) 2016-09-26 2018-04-10 Stmicroelectronics (Crolles 2) Sas Contact trench between stacked semiconductor substrates
US10199409B2 (en) 2016-09-26 2019-02-05 Stmicroelectronics (Crolles 2) Sas Trench between stacked semiconductor substrates making contact with source-drain region
US10084081B2 (en) * 2017-01-23 2018-09-25 International Business Machines Corporation Vertical transistor with enhanced drive current
US10109646B1 (en) 2017-06-05 2018-10-23 Qualcomm Incorporated Selectively recessing trench isolation in three-dimensional (3D) transistors to vary channel structure exposures from trench isolation to control drive strength
US10192867B1 (en) * 2018-02-05 2019-01-29 Globalfoundries Inc. Complementary FETs with wrap around contacts and method of forming same
KR20180058673A (ko) 2018-04-24 2018-06-01 포항공과대학교 산학협력단 수직적층구조의 3차원 정적램 코어 셀 및 그를 포함하는 정적램 코어 셀 어셈블리
CN112585752B (zh) * 2018-09-05 2023-09-19 东京毅力科创株式会社 3d逻辑和存储器的配电网络
US10811415B2 (en) * 2018-10-25 2020-10-20 Samsung Electronics Co., Ltd. Semiconductor device and method for making the same
JP7426547B2 (ja) * 2018-10-29 2024-02-02 東京エレクトロン株式会社 半導体素子のモノリシック3d集積を行うためのアーキテクチャ
KR102795719B1 (ko) * 2019-07-19 2025-04-16 삼성전자주식회사 3차원 반도체 장치
US11195794B2 (en) * 2020-02-05 2021-12-07 Samsung Electronics Co., Ltd. Stacked integrated circuit devices including a routing wire

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050184292A1 (en) * 2004-02-24 2005-08-25 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor integrated circuits using selective epitaxial growth and partial planarization techniques and semiconductor integrated circuits fabricated thereby
CN101257024A (zh) * 2006-09-14 2008-09-03 三星电子株式会社 具有三维排列的存储单元晶体管的与非型闪存器件
US20140091321A1 (en) * 2012-09-28 2014-04-03 Sony Corporation Semiconductor device, solid-state imaging device, and method of manufacturing semiconductor device
US20170345909A1 (en) * 2014-07-14 2017-11-30 Unisantis Electronics Singapore Pte. Ltd. Semiconductor device

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WO2020242909A1 (en) 2020-12-03
JP2022534858A (ja) 2022-08-04
KR20220003516A (ko) 2022-01-10
US20200381430A1 (en) 2020-12-03
TWI861115B (zh) 2024-11-11
JP7680812B2 (ja) 2025-05-21
US11437376B2 (en) 2022-09-06
TW202114115A (zh) 2021-04-01
KR102780323B1 (ko) 2025-03-11

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