TWI825166B - 用於製造單晶片積體式 3d cmos 邏輯及記憶體的架構設計及製程 - Google Patents

用於製造單晶片積體式 3d cmos 邏輯及記憶體的架構設計及製程 Download PDF

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TWI825166B
TWI825166B TW108131871A TW108131871A TWI825166B TW I825166 B TWI825166 B TW I825166B TW 108131871 A TW108131871 A TW 108131871A TW 108131871 A TW108131871 A TW 108131871A TW I825166 B TWI825166 B TW I825166B
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transistor
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拉爾斯 利布曼
安東 Ｊ 德維利耶
傑佛瑞 史密斯
坎達巴拉 泰伯利
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日商東京威力科創股份有限公司
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Abstract

提出一種半導體元件。該元件包括堆疊在基板上方之複數電晶體對。複數電晶體對每一者包括堆疊於彼此上之n型電晶體及p型電晶體。該元件亦包括堆疊在基板上方且具有階梯狀結構之複數閘極電極。複數閘極電極係電耦接至複數電晶體對之閘極結構。該元件更包括堆疊在基板上方且具有階梯狀結構之複數源極∕汲極（S/D）局部內連線。複數S/D局部內連線係電耦接至複數電晶體對之源極區及汲極區。

Description

用於製造單晶片積體式3D　CMOS邏輯及記憶體的架構設計及製程
本揭示內容關於包括半導體元件、電晶體及積體電路之微電子元件，包括微製造之方法。
[相關申請案之交互參照]
本申請案主張於2018年9月5日提出之美國臨時專利申請案第62/727,097號之優先權，其完整內容係併入本申請案中之參考資料。
在半導體元件(特別是在微觀等級上)之製造中，會執行各種製造處理，例如成膜沉積、蝕刻遮罩產生、圖案化、材料蝕刻及移除、以及摻雜處理。這些處理被重複執行，以在基板上形成期望的半導體元件成分。在歷史上，利用微製造，已經製造電晶體在一平面中，且接線/金屬化係形成在主動元件平面上方，因此已經被表徵為二維(2D)電路或2D製造。在微縮上之努力已大幅增加在2D電路中每單位面積之電晶體數目，但當微縮進入個位數奈米半導體元件製造節點時，在微縮上之努力正面臨更大的挑戰。半導體元件製造者已表達了對於電晶體堆疊於彼此上之三維(3D)半導體元件之需求。
本文中之技術提出堆疊式互補型FET(場效電晶體)元件之單元架構、設計概念及相應的製造方法。互補型FET(CFET)元件為三維堆疊式邏輯標準單元，其中NMOS或PMOS電晶體位於其互補構件上方(垂直上方)。這樣的配置使得邏輯標準單元以及SRAM記憶體單元能夠縮減面積並改善佈線壅塞。儘管關鍵尺寸微縮不可避免地達到飽和，但3D積體化(3D integration)是繼續進行半導體微縮之可行選項。當接觸閘極節距由於製造變異性及靜電元件限制而達到其微縮極限時，二維電晶體密度微縮就停止了。即使實驗性的新電晶體設計，例如垂直通道環繞式閘極電晶體，有一天也許能克服這些接觸閘極節距微縮限制，也不能保證使半導體微縮回到正軌。這是因為電阻、電容及可靠度關係限制了導線節距微縮，從而限制了電晶體可接線至電路中之密度。
3D積體化，亦即，複數元件之垂直堆疊，旨在藉由在體積上而不是在面積上增加電晶體密度來克服這些微縮限制。習知的CMOS VLSI微縮，例如使用在CPU或GPU產品中，對於採用3D積體化做為推動半導體發展藍圖向前之主要手段仍然有所猶豫。除了利基型應用(例如，堆疊在用於人工智慧晶片之機器學習加速器之邏輯上方之記憶體)之外，其它任何應用不採用3D積體化之主要原因為，已知技術之固有低效率。
本文中之技術改善了單晶片(monolithically)積體式3D CMOS元件之設計及製造效率。技術包括使用共通的元件堆疊，利用該元件堆疊，所有CFET之源極(輸入端)、汲極(輸出端)及閘極連接都接線至位於標準單元之頂部CMOS層別正上方之接觸窗(contact)陣列。一系列的客製化層利用客製化的局部接線而達成期望的的單元功能。
應當注意，本文中所述之製造步驟之順序係為了清楚說明之目的而呈現。整體而言，這些製造步驟可以任何合適的順序進行。此外，雖然本文中之不同特徵、技術、配置等之每一者可能是在本揭示內容之不同處加以討論，但 應當注意，每一概念可彼此獨立執行或彼此結合執行。據此，本揭示內容可以許多不同方式實現與檢視。
應當注意，發明內容部分並未明確說明本揭露內容或所請發明之每一實施例及/或漸增的新穎實施態樣。反之，此發明內容僅提供不同實施例及勝過習知技術之相應新穎處之初步討論。對於本發明及實施例之附加細節及/或可能觀點，可參見以下進一步討論之本揭示內容之實施方式部分及對應圖式。
根據本揭示內容之一態樣，提出一種半導體元件。該元件包括：複數電晶體對，堆疊在一基板上方，其中該複數電晶體對每一者包括堆疊於彼此上之一n型電晶體及一p型電晶體。該元件亦包括：複數閘極電極，堆疊在該基板上方且具有階梯狀結構，其中該複數閘極電極係電耦接至該複數電晶體對之複數閘極結構。該元件更包括：複數源極/汲極(S/D)局部內連線，堆疊在該基板上方且具有階梯狀結構，其中該複數S/D局部內連線係電耦接至該複數電晶體對之複數源極區及複數汲極區。
在某些實施例中，該n型電晶體位於該p型電晶體上方，以形成一互補型場效電晶體(CFET)元件。在某些實施例中，該p型電晶體位於該n型電晶體上方，以形成一互補型場效電晶體元件。該n型電晶體及該p型電晶體可共享一閘極結構，該閘極結構係電耦接至該複數閘極電極其中一者。
該元件可包括：一垂直接觸窗陣列，位於該複數電晶體對上方、形成在垂直於該基板之方向上並且電耦接至該複數閘極電極及該複數S/D局部內連線。
在所揭示的元件中，一系列接線層位於該垂直接觸窗陣列上方，並且藉由連接該垂直接觸窗陣列而提供該半導體元件之功能。
該n型電晶體具有一源極區及一汲極區，該源極區及該汲極區位於一n型通道區之兩端，該n型通道區被該閘極結構所圍繞。該p型電晶體具有 一源極區及一汲極區，該源極區及該汲極區位於一p型通道區之兩端，該p型通道區被該閘極結構所圍繞。該複數S/D局部內連線每一者位於該複數閘極電極之各別閘極電極之兩側上。
根據本揭示內容之另一態樣，提出一種半導體之形成方法。在所揭示的方法中，可形成複數電晶體對。該複數電晶體對可堆疊在一基板上方，其中該複數電晶體對具有複數閘極電極及複數源極/汲極(S/D)局部內連線，該複數閘極電極係堆疊在該基板上方且電耦接至該複數電晶體對之複數閘極結構，該複數S/D局部內連線係堆疊在該基板上方且電耦接至該複數電晶體對之複數源極區及複數汲極區。隨後，可執行一序列的垂直及側向蝕刻步驟，以蝕刻該複數閘極電極及該複數S/D局部內連線，使得該複數閘極電極及該複數S/D局部內連線具有階梯狀結構。
根據本揭示內容之又一態樣，提出一種半導體元件。該半導體元件包括：複數電晶體對，堆疊在一基板上方，其中該複數電晶體對具有複數閘極電極及複數源極/汲極(S/D)局部內連線，該複數閘極電極係堆疊在該基板上方、具有階梯狀結構且電耦接至該複數電晶體對之複數閘極結構，該複數S/D局部內連線係堆疊在該基板上方、具有階梯狀結構且電耦接至該複數電晶體對之複數源極區及複數汲極區。該元件亦包括：一垂直接觸窗陣列，位於該複數電晶體對上方、配置在垂直於該基板之方向上並且電耦接至該複數閘極電極及該複數S/D局部內連線。該元件更包括：一系列接線層，位於該垂直接觸窗陣列上方，並且藉由連接該垂直接觸窗陣列而提供該半導體元件之功能。
100:及或非(AOI)單元
102:主動區
104a~104d:閘極結構
106a~106f:金屬層
108a~108d:局部內連線
110a~110d:局部內連線
112a~112e:接觸窗
200:佈局
300:電晶體組
302~308:互補型場效電晶體(CFET)元件
310:局部內連線
312:局部內連線
314:金屬層
400A~400B:電晶體堆疊
500:電晶體堆疊
500A~500B:組
502~508:CFET元件
510:局部內連線
512:局部內連線
514:第一金屬層
600:電晶體堆疊
600A~600B:組
602~608:CFET元件
610:內連線
612:內連線
700:電晶體堆疊
702~708:CFET元件
800:電晶體堆疊
802~808:CFET元件
810:接觸窗
812~826:局部內連線
900:電晶體堆疊
902~908:CFET元件
910:接觸窗
912:閘極結構
914:閘極電極
916:汲極區
918:源極區
920:源極局部內連線
922:源極區
924:汲極局部內連線
926:源極局部內連線
1000:佈局
1002:電源電壓(VDD)
1004:接地電壓(VSS)
1006:局部內連線
1008:局部內連線
1010:主動元件區
1012:多晶矽導體
1014:接觸窗
1016:接觸窗
1018:金屬層
1020:金屬層
1022:金屬層
1100:電晶體堆疊
1102~1108:CFET元件
1110:閘極結構
1112:閘極電極
1114:源極區
1116:汲極區
1118:源極區
1120:源極局部內連線
1122:汲極局部內連線
1124:源極局部內連線
1200:CFET堆疊
1202~1208:CFET元件
1210:垂直接觸窗
A~D:閘極電極
GND:接地電壓
N1~N4:n型電晶體
P1~P4:p型電晶體
VDD:電源電壓
VSS:接地電壓
Y:輸出端
根據以下的實施方式並結合附圖，可最佳地理解本揭示內容之態樣。應當注意，根據工業中之標準實務，各種特徵並未按比例繪製。實際上，為了清楚討論，可能任意地放大或縮小各種特徵之尺寸。
圖1為根據某些實施例之及或非22(And-Or-Invert 22,AOI22)單元之概要電路圖。
圖2為根據某些實施例之AOI22單元之互補型場增強電晶體(CFET)實行例之俯視佈局圖。
圖3為根據某些實施例之基於CFET元件所形成之AOI22單元之概要圖。
圖4為根據某些實施例之基於CFET元件所形成之兩個堆疊式AOI22單元之概要圖。
圖5為根據某些實施例之藉由摺疊CFET元件所形成之AOI22單元之概要圖。
圖6為根據某些實施例之使用第一垂直佈線技術所形成之AOI22單元之概要圖。
圖7為根據某些實施例之使用第二垂直佈線技術所形成之AOI22單元之概要圖。
圖8A為根據某些實施例之基於具有階梯狀的局部內連線之3D積體式CFET堆疊所形成之AOI22單元之概要圖。
圖8B為根據某些實施例之基於具有階梯狀的局部內連線之3D積體式CFET堆疊所形成之AOI22單元之概要圖。
圖8C為根據某些實施例之基於具有階梯狀的局部內連線之3D積體式CFET堆疊所形成之AOI22單元之俯視佈局圖。
圖9為根據某些實施例之用於實施AOI22單元之邏輯功能之接觸窗之洞洞板圖案之概要圖。
圖10-15為根據某些實施例之製造AOI22單元之各種示例性中間步驟之概要圖，AOI22單元係基於具有階梯狀的局部內連線之3D積體式CFET堆疊所形成。
以下揭示內容提供許多不同實施例或範例，用以實施所述標的之不同特徵。構件及配置之特定範例描述如下，以簡化本揭示內容。當然，這些僅為範例，而非受限於此。此外，在本揭示內容之各種範例中，元件符號及/或字母可能重複。此重複是為了簡化與清晰之目的，其本身並非限定所討論的各種實施例及/或配置之間之關係。
再者，為了方便說明，在本文中可能使用空間相對用語，例如「下方」、「之下」、「下部」、「之上」、「上部」等，以描述圖中所示之一元件或特徵與另一元件或特徵之間之關係。這些空間相對用語之用意為，除了圖中所示之方向外，在使用或操作中更包括設備之不同方向。設備可以其它方式定向(轉90度或其它方向)，且本文中所使用之空間相對用語可據此作類似解釋。
整篇說明書中提到的「一實施例」或「實施例」表示關於該實施例所描述之特定特徵、結構、材料、或特性係包含於至少一實施例中，但不代表其存在每一實施例中。因此，在說明書不同地方出現「在一實施例中」用語時，未必指同一實施例。再者，特定特徵、結構、材料或特性可在一或更多實施例中以任何合適方式結合。
本文中之技術改善了單晶片積體式3D CMOS元件之設計及製造效率。技術包括使用通用(均一或共通)元件堆疊，利用該元件堆疊，所有CFET之源極(輸入端)、汲極(輸出端)及閘極連接都接線至位於標準單元之頂部CMOS層別正上方之接觸窗陣列。一系列的客製化層利用客製化的局部接線而達成期望的的單元功能。
大多數邏輯晶片是由標準單元中所提供的邏輯基元(logic primitive)所產生。一個示例性標準單元可顯示在圖1中。圖1顯示出及或非(And-Or-Invert,AOI)單元100之概要電路圖。本文中之AOI單元100是中等複雜的標準單元，其電晶體被分組為在單元之p-fet側之並聯對、及在CMOS電路之n-fet側之串聯對。例如，p-fet側可包括四個p型電晶體P1-P4，其中P1及P2為並聯連接，P3及P4為並聯連接。n-fet側可包括四個n型電晶體N1-N4，其中N1及N2為串聯連接，N3及N4為串聯連接。AOI單元100電耦接至四個閘極電極A-D及一個輸出端Y。四個閘極電極A-D其中每一者均耦接至AOI單元100之各別的n型閘極及p型閘極。例如，輸入端A耦接至N型電晶體N1之n型閘極及p型電晶體P1之p型閘極。此外。AOI單元100連接至電源電壓VDD，電源電壓VDD耦接至p型電晶體P1及P2之源極區。AOI單元100更連接至接地電壓GND(也稱為VSS)，接地電壓GND耦接至n型電晶體N2及N4之源極區。
圖2是基於非3D積體式CFET提供所形成之AOI單元100之相關佈局200。圖2顯示出AOI單元100之佈局200之俯視圖。如圖2所示，佈局200可具有經由離子植入處理而進行摻雜之主動區102。佈局200可具有四個閘極結構104a-104d。佈局200亦包括複數最低層別之金屬層(例如，M0)106a-106f。佈局200可包括複數n-fet源極/汲極(S/D)局部內連線108a-108d、及複數p-fet源極/汲極(S/D)局部內連線110a-110d。n-fet源極/汲極(S/D)局部內連線108a-108d及p-fet源極/汲極(S/D)局部內連線110a-110d係藉由複數接觸窗(contact)112a-112e而連接至M0 106a-106f。此外，佈局200可包括複數閘極電極A-D，閘極電極A-D連接至閘極結構104a-104d及M0以分別存取閘極電極A-D。在電路概要圖1中顯示本文中所討論之電力輸送，為VDD及GND(亦稱為VSS)。在佈局200之俯視圖中，VDD及VSS電力軌係顯示為寬 條，位於佈局200之頂部及底部水平邊緣處。在S/D局部內連線108a-108d及110a-110d中形成之電力分接頭(未顯示)用於將電晶體之源極區連接至這些電力軌。
圖3為根據某些實施例之基於CFET元件所形成之AOI單元100之概要圖。如圖3所示，AOI單元100可由包括四個CFET元件302-308之電晶體組300形成，其中每一CFET元件耦接至各別的輸入端。例如，CFET元件302耦接至輸入端A，CFET元件304耦接至輸入端B。此外，每一CFET元件可包括n型電晶體及p型電晶體。n型電晶體及p型電晶體可具有共享的閘極結構。例如，CFET元件302包括n型電晶體N1及p型電晶體P1，如圖3所示。四個CFET元件302-308藉由複數局部內連線而連接。例如，可形成局部內連線310以連接n型電晶體N1及N2，並且可形成局部內連線312以連接p型電晶體P1及P2。四個CFET元件更經由局部內連線而耦接至電源電壓VDD、接地電壓VSS及輸出端Y。元件亦可包括用以重新分配p-fet元件訊號之第一金屬層(例如，M0)314。
實現3D積體化之一種方法是，簡單地將標準單元堆疊在彼此之上。存在各種晶圓或基板接合方式，以實現圖4中概念性所示之結果。如圖4所示，兩個AOI單元100可分別由兩個CFET電晶體堆疊400A及400B形成。電晶體堆疊400A可形成在第一晶圓中以提供頂部輸出，電晶體堆疊400B可形成在第二晶圓中以提供底部輸出。然後兩晶圓可接合在一起以形成3D積體化。儘管這樣的3D積體化方案對標準單元設計之破壞最小，但無法達成成本或製造效益之提高，而此最終為半導體微縮之目標。不是半導體製造商承擔必須先建立兩晶片、然後必須將它們接合在一起之成本，就是如果相繼地製造後續的CMOS層，則製程工程師必須解決在金屬接線存在時、與元件活化相關之具有挑戰性的熱預算問題。無論哪一種方式，連續3D積體化(不像習知2D積體化)無法提 供如許多具有相同處理成本或複雜性之電晶體兩倍之電晶體生產效益提高(如摩爾定律所述)。
或者，不是將標準單元堆疊成CMOS之連續層別，而是如圖5所示，藉由折疊整個單元(而不是如CFET中僅有電晶體)在彼此上，以實現3D積體化。如圖5所示，AOI單元100可由電晶體堆疊500形成。電晶體堆疊500可具有四個CFET元件502-508，四個CFET元件502-508沿著垂直於基板之方向而堆疊成兩組500A-500B。兩組中的每一組更可具有平行配置之兩個CFET元件。例如，組500A可具有平行配置之CFET元件506及CFET元件508。每個CFET元件可包括n型電晶體及p型電晶體。n型電晶體及p型電晶體可具有共享的閘極結構。例如，CFET元件502包括n型電晶體N1及p型電晶體P1。四個CFET元件502-508藉由複數局部內連線而連接。例如，形成局部內連線510以連接n型電晶體N3及N4，並且形成局部內連線512以連接p型電晶體P2及P4。四個CFET元件更藉由局部內連線而耦接至電源電壓VDD、接地電壓VSS及輸出端Y。此外，第一金屬層(例如，M0)514位於電晶體組500B上方，並用以重新分配p-fet元件訊號。雖然此方案因為佈局佈線工具繼續運作於單一平面中而提供了某些設計效率上之增強，但它無法解決與連續元件製造相關之低效率問題，如上所述。
令人期待的3D積體化為，堆疊式元件之單晶片積體化，亦即，使用「垂直佈線」(vertical routing)在3D空間中同時製造複數元件，如本案發明人先前所述。為了描繪此期望及突顯其餘設計及處理之複雜性，圖6顯示AOI單元100之兩個CFET高堆疊圖像。如圖6所示，AOI單元100可藉由第一垂直佈線處理由電晶體堆疊600形成。電晶體堆疊600可具有四個CFET元件602-608，其平行地堆疊成兩組600A-600B。兩組中的每一組更可具有彼此堆疊之兩個CFET元件。例如，組600A可具有堆疊在CFET元件606上方之CFET 元件602。每個CFET元件可包括n型電晶體及p型電晶體。n型電晶體及p型電晶體可具有共享的閘極結構。例如，CFET元件602包括n型電晶體N2及p型電晶體P2。四個CFET元件602-608藉由複數內連線(亦即，610及612)通過垂直佈線而連接。四個CFET元件更藉由內連線而耦接至電源電壓VDD、接地電壓VSS及輸出端Y。
藉由堆疊主動電晶體而沒有中間接線層，垂直接線技術解決3D積體化中主要的低效率問題，其中所有電晶體可同時進行圖案化及製造。應注意，仍然存在兩種低效率。一挑戰為解決複雜的電晶體層接線，如圖7所示。圖7為根據某些實施例之使用第二垂直佈線技術所形成之AOI單元100之概要圖。如圖7所示，AOI單元100可由電晶體堆疊700實現。電晶體堆疊700包括沿著垂直於基板之方向堆疊成一列之四個CFET元件702-708。四個CFET元件702-708藉由複數內連線(或電晶體層接線)通過垂直佈線而彼此連接。在3D空間中，電晶體層接線是具有挑戰性的並且容易出錯，導致設計效率下降。另一挑戰為使每一CMOS層別具有特有的局部內連線及接觸窗。此增加了遮罩數量及製造複雜性至非期望的程度。需要為CFET摩天大樓(堆疊結構)之每一層定義至少四個單獨的遮罩層。
本文中之技術改善了單晶片積體式3D CMOS元件之設計及製造效率。這樣的改善係藉由實施技術定義及設計流程來達成，該技術定義及設計流程利用由兩個特有構件所組成之架構來取代現有的標準單元邏輯流程。
一構件為通用元件(generic device)堆疊。此通用元件堆疊類似於閘極陣列，在該閘極陣列中所有CFET源極(輸入)、汲極(輸出)及閘極連接皆接線至位於對應的標準單元之頂部CMOS層別正上方之接觸窗陣列。此通用元件堆疊使整個電晶體堆疊能夠在本案發明人先前揭示之CFET積體化處理之擴展中利用主動通道及閘極導體之單一曝光來製造。利用一系列的垂直及側向 蝕刻步驟，此通用元件堆疊中之多晶矽閘極及局部內連線為階梯狀的，以允許從上方無障礙地存取每一層。從橫剖面來看，這基本上形成了台階狀的角錐結構。將元件堆疊中之每一層連接至接觸窗陣列之垂直接觸窗係位於在單一圖案化操作中形成之頂部CMOS層別正上方。這樣的結構之形成使用被設計於每一各別接觸窗目標層中之蝕刻停止物。此通用元件堆疊係配置為具有功能差異化。因此，一數量的電晶體被有效地建立，連接至洞洞板(pegboard)型式的接觸窗陣列。
另一構件為一系列的客製化層，在其中局部接線用於連接特定接觸窗以實現期望的單元功能。因此，元件堆疊之通用或可重複的洞洞板設計可用於產生許多類型的邏輯元件其中任一者。雖然本文中所述之特定實施例聚焦於使用堆疊式CFET電晶體之邏輯設計，但是對於熟悉此項技藝者而言，如何使這些技術及元件結構適用於記憶體單元及其它電晶體類型將是顯而易見的。
在一實施例中，本文中之技術提出一種架構定義，此架構定義藉由將已建立的標準單元設計流程分成以下部分以實現有效的3D單晶片積體化：(a)一數量的電晶體，連接至位於頂部CMOS層正上方之洞洞板型式的接觸窗陣列，可顯示於圖8A及8B中；及(b)一系列的接線層，藉由連接合適的輸入(源極)、輸出(汲極)及訊號(閘極接觸窗)接觸窗層別以提供所需的功能，可顯示於圖8C中。
圖8A為基於具有階梯狀的局部內連線之3D積體式CFET堆疊所形成之AOI單元100之概要圖。如圖8所示，台階狀或角錐形的電晶體係形成為具有從電晶體堆疊800之台階而延伸之垂直接觸窗810。電晶體堆疊800可包括堆疊在基板上方之四個CFET元件802-808。每一CFET元件可包括一n型電晶體及p型電晶體，耦接至一各別輸入端。例如，CFET 802可包括n型電晶體N3及p型電晶體P3，其耦接至輸入端D。電晶體堆疊800可具有複數局部內連 線812-826，其具有階梯狀結構。每一局部內連線耦接至一各別電晶體。電晶體堆疊800可更包括一組垂直接觸窗810陣列，其耦接至局部內連線812-826並從局部內連線812-826延伸。該組垂直接觸窗810陣列之頂表面可為彼此共平面，但每一垂直接觸窗或柱之長度係取決於著陸台階之高度及位置而有所不同。
圖8B為基於3D積體式電晶體堆疊900所形成之AOI單元100之概要圖。電晶體堆疊900可包括堆疊在基板(未顯示)上方之四個CFET元件902-908。四個CFET元件其中每一者可包括由n型電晶體及p型電晶體所形成之一電晶體對。例如，CFET元件902可包括一電晶體對，由n型電晶體N3及p型電晶體P3所形成，n型電晶體N3及p型電晶體P3耦接至輸入端D。n型電晶體及p型電晶體可具有共享的閘極結構。n型電晶體可位於p型電晶體上方。閘極結構可圍繞n型電晶體之n型通道區及p型電晶體之p型通道區。通道區可具有片狀、線狀或條狀構造。n型電晶體可具有分別位於n型通道區兩端之源極區及汲極區，其中閘極結構圍繞n型通道區，並且位於n型電晶體之源極區與汲極區之間。p型電晶體可具有分別位於p型通道區兩端之源極區及汲極區，其中閘極結構圍繞p型通道區，並且位於p型電晶體之源極區與汲極區之間。此外，閘極結構可電耦接至閘極電極。源極區及汲極區可分別具有源極局部內連線及汲極局部內連線。
如圖8B所示，閘極電極及源極/汲極(S/D)局部內連線具有階梯狀結構。此外，複數垂直接觸窗910耦接至S/D局部內連線或閘極電極並且從S/D局部內連線或閘極電極延伸。因此，閘極電極及S/D局部內連線之階梯狀結構提供了對於電晶體堆疊900中之每一電晶體之容易存取，並且避免如圖3-7所繪示之複雜的內連線連接。
繼續參考圖8B，n型電晶體N3及p型電晶體P3具有共享的閘極結構912。n型電晶體N3具有位於n型通道區兩端之源極區918及汲極區916。 n型通道區被閘極結構912圍繞，其中閘極結構912位於源極區918與汲極區916之間。p型電晶體P3具有源極區922及在閘極結構912後方之汲極區。源極區922及汲極區位於p型通道區之兩端。類似地，p型通道區被閘極結構912圍繞，其中閘極結構912位於p型電晶體P3之源極區922與汲極區之間。
閘極結構912可具有一或更多閘極電極914。閘極電極914可位於閘極結構912之兩端。n型電晶體N3之源極區918及汲極區916可分別具有源極局部內連線920及汲極局部內連線924。類似地，p型電晶體P3之源極區922可具有源極局部內連線926，且p型電晶體P3之汲極區可具有位於閘極結構912後方之汲極局部內連線。
應當注意，圖8B僅為一範例。電晶體堆疊900可能具有任何數量的CFET元件堆疊在基板(未顯示)上方。CFET元件可藉由複數介電層(未顯示)而彼此間隔開。CFET元件可具有n型電晶體及p型電晶體。在一些實施例中，n型電晶體可位於p型電晶體上方。在一些實施例中，p型電晶體可位於n型電晶體上方。此外，n型電晶體及p型電晶體可藉由絕緣層而分隔開。再者，應當注意，源極區及閘極結構藉由絕緣層而分隔開，且汲極區及閘極結構也藉由絕緣層而分隔開。
圖8C為基於具有階梯狀的局部內連線之3D積體式CFET堆疊所形成之AOI單元100之俯視圖。圖8C顯示出一系列的接線層，其藉由連接合適的輸入(源極)、輸出(汲極)及訊號(閘極接觸窗/閘極電極)接觸窗層別以提供所需的功能。圖8C(a)為通用單晶片元件之佈局，圖8C(b)顯示出客製化層。如圖8C(a)所示，佈局1000可具有作為輸入端之四個閘極電極A-D。佈局1000可具有VDD 1002及VSS 1004。佈局1000可具有p-fet局部內連線1006及n-fet局部內連線1008。局部內連線1006及1008分別經由n-fet源極/汲極接觸窗1014及p-fet源極/汲極接觸窗1016而耦接至主動元件區1010。佈局1000亦具有耦 接至閘極電極A-D之多晶矽導體1012。如圖8C(b)所示，形成三個金屬層(接線層)M0 1018、M1 1020及M2 1022，其配置為藉由連接合適的輸入(源極)、輸出(汲極)及訊號(閘極接觸窗)接觸窗層別以提供所需的功能。
在另一實施例中，本文中之技術提供了均勻且可客製化的、重複的3D電晶體及接觸窗存取。這樣的設計基本上提供了「洞洞板」圖案的接觸窗以實現3D邏輯。接著，概要圖可映射到3D邏輯設計，如圖9中之標準邏輯AOI功能所示。圖9(a)為AOI單元100之概要電路圖。圖9(b)為形成在AOI單元100之p-fet側之洞洞板圖案的接觸窗。圖9(c)為形成在AOI單元100之n-fet側之洞洞板圖案的接觸窗。如圖9(b)及9(c)所示，藉由一系列的接線層(例如，M0、M1、M2)連接相應的源極/汲極接觸窗及閘極接觸窗，可形成標準邏輯AOI功能。在一些實施例中，基於圖8B中所示之垂直接觸窗910，可形成洞洞板圖案的接觸窗。垂直接觸窗910可耦接至閘極電極、S/D局部接觸窗，以形成「洞洞板」圖案的接觸窗。標準邏輯AOI功能可藉由以下方式達成：藉由一系列的接線層(例如，M0、M1、M2)建立在垂直接觸窗910、電源電壓VDD、閘極電極A-D與接地電壓GND之間之對應連接，一系列的接線層係設置於垂直接觸窗陣列上方並且藉由連接垂直接觸窗陣列而提供半導體元件之功能。
應當注意，某些邏輯功能(如AOI22)恰好用掉此範例中所使用之四個CFET元件，然而其它邏輯功能(如簡單的反相器)需要較少的電晶體對。利用本文中之技術，因為接觸窗連接至一數量的通用電晶體，所以無關於給定/對應的栓(peg)指定。因此，在圖9中使用於設計暫存器之「A」及「B」栓可輕易地轉成在反相器設計中可用的「B」及「C」栓。透過擴展至現有的電子設計自動化工具及流程，此技術之簡約性及清晰性實現了產品實施。
本文中之技術提供了單晶片3D積體化流程，使得m個CFET元件(在本揭示內容中，m等於4)之堆疊能夠以一系列的層沉積來建立。接著，以角錐型形成技術依序使層凹陷，使這些元件層露出或暴露，從而從上方提供存取。一旦以此方式形成，則可藉由垂直內連線陣列而接觸所有的元件層，垂直內連線陣列係在單一曝光中被圖案化並且藉由加入對應的蝕刻停止層而被蝕刻至適當的深度。
單晶片3D積體化流程可藉由圖10-15進行說明。如圖10所示。電晶體堆疊1100可形成在基板(未顯示)上。電晶體堆疊1100之配置類似於圖8B所示之電晶體堆疊900。如圖10所示，電晶體堆疊1100可具有堆疊在基板上之複數CFET元件1102-1108。每一CFET元件可具有彼此堆疊之n型電晶體及p型電晶體。在一些實施例中，n型電晶體位於p型電晶體上方。在一些實施例中，p型電晶體位於n型電晶體上方。在圖10之範例中，n型電晶體位於p型電晶體上方。
電晶體堆疊1100可具有複數閘極電極，複數閘極電極堆疊在基板上方並且電耦接至複數CFET元件之閘極結構。例如，CFET元件1102可具有由n型電晶體N3及p型電晶體P3共享之閘極結構1110。閘極結構1110可具有位於閘極結構兩端之閘極電極1112。電晶體堆疊1100可具有複數源極/汲極(S/D)局部內連線，其堆疊在基板上方並且電耦接至CFET元件之源極區及汲極區。例如，n型電晶體N3可具有源極區1114及汲極區1116。源極區1114可具有源極局部內連線1120，汲極區1116可具有汲極局部內連線1122。類似地，p-型電晶體P3可具有源極區1118及在閘極結構1110後方之汲極區。源極區1118具有源極局部內連線1124，汲極區具有位於閘極電極1112後方之汲極局部內連線。
在圖11-13中，可執行一系列的垂直及側向蝕刻步驟，以蝕刻在電晶體堆疊1100中之複數閘極電極及複數S/D局部內連線，使得複數閘極電極 及複數S/D局部內連線具有階梯狀配置。例如，在圖11中，去除了CFET元件1102之閘極電極及S/D局部內連線之部分。在圖12中，去除了CFET元件1104之閘極電極及S/D局部內連線之部分。基於這樣的依序蝕刻處理，可在閘極電極及S/D局部內連線中形成階梯狀結構。應當注意，在垂直及側向蝕刻步驟期間，可採用微影處理。微影處理可提供遮罩層，以保護期望的區域及使需要去除的區域外露。隨後可藉由蝕刻步驟以去除外露的區域。
在圖14中，複數垂直接觸窗可形成在介電質堆疊(未顯示)中。 可基於圖案化處理及沉積處理而形成垂直接觸窗。圖案化處理可包括微影處理，微影處理在遮罩層中形成複數圖案。隨後，蝕刻處理可將圖案轉移至介電質堆疊中以形成複數接觸窗開口。可採用沉積處理，以將導電材料沉積至接觸窗開口中以形成垂直接觸窗。沉積處理可包括化學氣相沉積(CVD)、物理氣相沉積(PVD)、擴散、原子層沉積(ALD)、或其它合適的沉積處理。導電材料可包括鎢、鈷、釕、銅、鋁、或其它合適的導電材料。
在圖15中，在沉積導電材料之後，可基於具有階梯狀局部內連線之3D積體式CFET堆疊1200來形成AOI單元100。CFET堆疊1200可具有與CFET電晶體堆疊900類似之配置。例如，CFET堆疊1200包括堆疊在基板上方之四個CFET元件1202-1208。CFET堆疊1200之閘極電極及S/D局部內連線具有階梯狀結構。複數垂直接觸窗1210耦接至閘極電極及S/D局部內連線並從其延伸。
對於邏輯及記憶體設計，本文中之技術架構實現有效的堆疊式電晶體之3D單晶片積體化。此包括，在一組由微影定義的圖案上，使用依序沉積及蝕刻操作而建立通用電晶體堆疊(均一基本電晶體設計)。這種通用電晶體堆疊之閘極電極及源極/汲極局部內連線形成階梯狀(台階狀的角錐)結構，以從上方存取後續的電晶體層。接觸窗陣列係從在頂部元件層上方之平面加以蝕刻， 以著陸在該階梯狀結構之每一各別電晶體層上。接觸窗陣列可具有相同的頂表面。接著，根據預定的邏輯功能設計或記憶體設計而連接通用電晶體組。連接接觸窗陣列之圖案接著定義了通用電晶體之邏輯或記憶體功能。換言之，基板上之所有電晶體可具有相同的基本架構，垂直接觸窗陣列藉由接線圖案而提供可客製化的功能。應當注意，在某些配置中，超過一個邏輯功能可接線至給定的洞洞板。若是簡單的邏輯功能，可能僅使用一部分接觸窗及對應的電晶體。此留下了開放的接觸窗用於在同一通用元件堆疊上連接第二邏輯功能。
應當注意，雖然本文中之示例性實施例聚焦於3D邏輯結構，但是熟悉此項技藝者可理解如何將本文中之技術應用於3D記憶體結構，例如堆疊式SRAM。在本揭示內容中，AOI單元僅為範例。所揭示的階梯狀內連線結構可應用於其它邏輯結構、類比結構、記憶體結構或其它半導體元件。
於以上敘述中，已提出具體細節，例如處理系統之特定幾何結構及其中所使用之各種構件及處理之描述。然而，應當理解，本文中之技術可實施於背離這些具體細節之其它實施例中，且這樣的細節係用於說明而非用於限制之目的。本文中所揭示之實施例已參考附圖加以描述。類似地，為了說明之目的，已提出特定數目、材料及配置以提供完整的理解。僅管如此，實施例可在沒有這樣的具體細節下實施。具有實質上相同的功能性結構之元件以類似的參考符號表示，因此可省略任何冗餘的描述。
各種技術已描述為多個分離的操作，以助於理解各種實施例。描述的順序不應被解釋為暗示這些操作係必然順序相關的。事實上，這些操作不需以陳述的順序加以執行。所述的操作可以不同於所述實施例之順序來執行。在額外的實施例中，可執行各種額外操作、及/或可省略所述的操作。
本文中所使用之「基板」或「目標基板」一般意指根據本發明進行處理之物件。基板可包含元件之任何材料部分或結構，尤其是半導體或其它電 子元件，且例如可為基底基板結構，例如半導體晶圓、光罩、或在基底基板結構之上或覆蓋基底基板結構之一層，例如薄膜。因此，基板不限於任何特定的基底結構、底層或覆蓋層、圖案化或未圖案化，而是設想為包括任何這樣的層或基底結構、以及層及/或基底結構之任何組合。描述可能提及特定類型的基板，但此僅用於說明之目的。
熟悉此項技藝者亦將了解，可對上述技術之操作做出許多變化，但仍可達到本發明之相同目標。這樣的變化應被本揭露內容之範圍所涵蓋。因此，本發明實施例之以上說明並非限制性的。本發明實施例之任何限制係呈現於下列申請專利範圍中。
900:電晶體堆疊
902~908:互補型場效電晶體(CFET)元件
910:接觸窗
912:閘極結構
914:閘極電極
916:汲極區
918:源極區
920:源極局部內連線
922:源極區
924:汲極局部內連線
926:源極局部內連線

Claims (13)

  1. 一種半導體元件，包括：複數電晶體對，堆疊在一基板上方，該複數電晶體對每一者包括堆疊於彼此上之一n型電晶體及一p型電晶體；複數閘極電極，堆疊在該基板上方且具有階梯狀結構，該複數閘極電極係電耦接至該複數電晶體對之複數閘極結構；複數源極/汲極(S/D)局部內連線，堆疊在該基板上方且延伸於與該基板平行的第一方向之上且具有階梯狀結構，該複數S/D局部內連線係電耦接至該複數電晶體對之複數源極區及複數汲極區；及一垂直接觸窗陣列，自該複數閘極電極及該複數S/D局部內連線延伸於與該基板垂直的第二方向之上。
  2. 如請求項1之半導體元件，其中該n型電晶體位於該p型電晶體上方，以形成一互補型場效電晶體(CFET)元件。
  3. 如請求項1之半導體元件，其中該p型電晶體位於該n型電晶體上方，以形成一互補型場效電晶體元件。
  4. 如請求項1之半導體元件，其中：該垂直接觸窗陣列電耦接至該複數閘極電極及該複數S/D局部內連線。
  5. 如請求項4之半導體元件，更包括：一系列接線層，位於該垂直接觸窗陣列上方，並且藉由連接該垂直接觸窗陣列而提供該半導體元件之功能。
  6. 如請求項1之半導體元件，其中該n型電晶體及該p型電晶體共享一閘極結構，該閘極結構係電耦接至該複數閘極電極其中一者。
  7. 如請求項6之半導體元件，其中該n型電晶體具有一源極區及一汲極區，該源極區及該汲極區位於一n型通道區之兩端，該n型通道區被該閘極結構所圍繞，該n型電晶體之該n型通道區、該源極區及該汲極區係配置在該第一方向之上。
  8. 如請求項6之半導體元件，其中該p型電晶體具有一源極區及一汲極區，該源極區及該汲極區位於一p型通道區之兩端，該p型通道區被該閘極結構所圍繞，該p型電晶體之該p型通道區、該源極區及該汲極區係配置在該第一方向之上。
  9. 如請求項1之半導體元件，其中該複數S/D局部內連線每一者位於該複數閘極電極之各別閘極電極之兩側。
  10. 一種半導體元件，包括：複數電晶體對，堆疊在一基板上方，其中該複數電晶體對具有複數閘極電極及複數源極/汲極(S/D)局部內連線，該複數閘極電極係堆疊在該基板上方、具有階梯狀結構且電耦接至該複數電晶體對之複數閘極結構，該複數S/D局部內連線係堆疊在該基板上方、具有階梯狀結構且電耦接至該複數電晶體對之複數源極區及複數汲極區；一垂直接觸窗陣列，位於該複數電晶體對上方、配置在垂直於該基板之方向上並且電耦接至該複數閘極電極及該複數S/D局部內連線；及 一系列接線層，位於該垂直接觸窗陣列上方，並且藉由連接該垂直接觸窗陣列而提供該半導體元件之功能。
  11. 如請求項10之半導體元件，其中該複數電晶體對每一者包括堆疊於彼此上之一n型電晶體及一p型電晶體，該n型電晶體及該p型電晶體共享一閘極結構。
  12. 如請求項11之半導體元件，其中該n型電晶體位於該p型電晶體上方，以形成一互補型場效電晶體元件。
  13. 如請求項11之半導體元件，其中該p型電晶體位於該n型電晶體上方，以形成一互補型場效電晶體元件。
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