CN113824466B - Ultra-wideband radio frequency transceiving switch adopting clamping resistor - Google Patents

Ultra-wideband radio frequency transceiving switch adopting clamping resistor Download PDF

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CN113824466B
CN113824466B CN202111002829.1A CN202111002829A CN113824466B CN 113824466 B CN113824466 B CN 113824466B CN 202111002829 A CN202111002829 A CN 202111002829A CN 113824466 B CN113824466 B CN 113824466B
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nmos transistor
nmos
drain electrode
series
resistor
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CN113824466A (en
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王政
张振翼
谢倩
赵琦伟
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H04B1/401—Circuits for selecting or indicating operating mode
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H04B1/44—Transmit/receive switching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

The invention belongs to the field of radio frequency integrated circuits, relates to a receiving and transmitting switch, and particularly provides an ultra-wideband radio frequency receiving and transmitting switch adopting a clamping resistor, which is used for solving the problems that in the prior art, the clamping resistor is large in quantity and resistance value, the layout area of the radio frequency receiving and transmitting switch is overlarge, and the like. According to the invention, the clamping resistors are respectively introduced between the series stacked transistor and the parallel stacked transistor of the transmitting path and between the series stacked transistor and the parallel stacked transistor of the receiving path, so that the direct-current voltage drift phenomenon of the transceiving switch is effectively inhibited, and the isolation degree and the insertion loss of the transceiving switch are not influenced; compared with the traditional clamping mode, the invention only needs one clamping resistor in each channel, thereby greatly reducing the using amount of the clamping resistors, having simple circuit structure and obviously reducing the receiving and transmitting switch layout area.

Description

Ultra-wideband radio frequency transceiving switch adopting clamping resistor
Technical Field
The invention belongs to the field of radio frequency integrated circuits, relates to a receiving and transmitting switch, and particularly provides a 0-40GHz ultra wide band radio frequency receiving and transmitting switch adopting a novel clamping resistor.
Background
The millimeter wave band (30-300 GHz) has rich spectrum resources and can provide required frequency for 5G, so that the millimeter wave communication technology becomes one of the most important technologies for 5G realization; however, millimeter waves are easily absorbed or scattered because of their very high frequency, and lose more energy when transmitted over long distances. Among the many methods for improving the signal-to-noise ratio, a beamforming technique for changing the direction of radio waves by a phased array technique is one of the most effective methods; the phased array antenna adopts a multi-antenna element structure, and beam forming is realized by changing the phase of a signal on each antenna; the phased array technology can effectively transmit signals to a specified direction and has obvious sidelobe suppression effect.
The receiving and transmitting switch is used as a key module in the phased array transceiver and is used for switching the working state (receiving or transmitting) of the whole phased array transceiver chip; which is connected to an antenna, a low noise amplifier and a power amplifier. In order to improve the output power and the linearity, the rf transceiver switch often stacks a plurality of transistors, but the stacked transistors cause the problem of dc voltage offset; in order to solve the problem that the prior art,the conventional transceiving switch directly connects a resistor between the source and drain of the transistor to determine the dc voltage of the transistor, as shown in fig. 1, where R is 1 ～R 8 Are all clamping resistors. However, the conventional clamping method is equivalent to introducing an additional ground path, which can greatly increase loss and deteriorate isolation; if the situation is to be avoided, the clamping resistor and the equivalent resistor when the MOS transistor is turned off are required to be in the same order, that is, about several tens of megaohms, and the number of resistors is large, which finally results in an overlarge layout area of the radio frequency transceiver switch.
Disclosure of Invention
The invention aims to provide an ultra-wideband radio frequency transceiving switch adopting a novel clamping resistor aiming at the problems in the prior art; a clamping resistor is introduced between the series stacked transistors and the parallel stacked transistors of the transmitting path and the receiving path, so that the direct-current voltage drift phenomenon of the transceiving switch is effectively inhibited, and the isolation degree and the insertion loss of the transceiving switch are not influenced.
The specific technical scheme of the invention is as follows:
an ultra-wideband radio frequency transceiving switch adopting a novel clamping resistor comprises: -a transmission path and a reception path, characterized in that, starting from a receiver, said transmission path comprises: the clamp resistor R is connected between the source electrode of a first-stage NMOS transistor in the parallel three-stacked NMOS transistor and the drain electrode of a first-stage NMOS transistor in the two stacked NMOS transistors in series; from the antenna, the receiving path includes: the NMOS transistor structure comprises a serial three-stacked NMOS transistor, a parallel two-stacked NMOS transistor and a clamping resistor R which are sequentially connected, wherein the clamping resistor R is connected between the drain electrode of a third-stage NMOS transistor in the serial three-stacked NMOS transistor and the source electrode of a first-stage NMOS transistor in the parallel two-stacked NMOS transistor.
Further, in the transmitting path, the parallel triple-stacked NMOS transistor is formed by NMOS transistors M1 to M3, a drain of the NMOS transistor M1 is connected to the transceiver, and a source of the NMOS transistor M1 is connected to the sourceThe pole of the NMOS transistor M2 is connected with the drain electrode of the NMOS transistor M2, the source electrode of the NMOS transistor M2 is connected with the drain electrode of the NMOS transistor M3, and the source electrode of the NMOS transistor M3 is grounded; the two stacked NMOS transistors connected in series are composed of NMOS transistors M4 and M5, the source electrode of the NMOS transistor M4 is connected with the drain electrode of the NMOS transistor M1, the drain electrode of the NMOS transistor M4 is connected with the source electrode of the NMOS transistor M5, and the drain electrode of the NMOS transistor M5 is connected with an antenna; the gates of the NMOS transistors M1-M3 are respectively connected with a series resistor and then connected with a control signal V C1 The gates of NMOS transistors M4 and M5 are respectively connected in series with resistors and then connected with control signal V C2 The substrate terminals (Bulk) of the NMOS transistors M1-M5 are respectively connected with a series resistor and then connected with a bias voltage V B (ii) a One end of the clamp resistor R is connected between the source electrode of the NMOS transistor M1 and the drain electrode of the NMOS transistor M2, and the other end of the clamp resistor R is connected between the drain electrode of the NMOS transistor M4 and the source electrode of the NMOS transistor M5;
in the receiving path, the two parallel stacked NMOS transistors are composed of NMOS transistors M6 and M7, the drain electrode of the NMOS transistor M6 is connected with the transceiver, the source electrode of the NMOS transistor M6 is connected with the drain electrode of the NMOS transistor M7, and the source electrode of the NMOS transistor M7 is grounded; the series three-stacked NMOS transistor is composed of NMOS transistors M8-M10, the source electrode of the NMOS transistor M8 is connected with the drain electrode of the NMOS transistor M6, the drain electrode of the NMOS transistor M8 is connected with the source electrode of the NMOS transistor M9, the drain electrode of the NMOS transistor M9 is connected with the source electrode of the NMOS transistor M10, and the drain electrode of the NMOS transistor M10 is connected with an antenna; the gates of the NMOS transistors M6 and M7 are respectively connected with resistors in series and then connected with a control signal V C2 The gates of NMOS transistors M8-M10 are respectively connected with series resistors and then connected with a control signal V C1 The substrate terminals (Bulk) of the NMOS transistors M6-M10 are respectively connected with a series resistor and then connected with a bias voltage V B (ii) a One end of the clamp resistor R is connected between the source of the NMOS transistor M6 and the drain of the NMOS transistor M7, and the other end is connected between the drain of the NMOS transistor M8 and the source of the NMOS transistor M9.
Furthermore, in the ultra-wideband radio frequency transceiving switch, all the NMOS transistors have the same structure and the same size.
Furthermore, in the ultra-wideband radio frequency transceiver switch, the clamp resistor R, all resistors connected in series to the gate of the NMOS transistor, and all resistors connected in series to the substrate end of the NMOS transistor have the same resistance.
The invention has the beneficial effects that:
the invention provides an ultra-wideband radio frequency transceiving switch adopting a novel clamping resistor, which effectively inhibits the DC voltage drift phenomenon of the transceiving switch by respectively introducing the clamping resistor between a series stacked transistor and a parallel stacked transistor of a transmitting path and between a series stacked transistor and a parallel stacked transistor of a receiving path, and does not influence the isolation and insertion loss of the transceiving switch; compared with the traditional clamping mode, the invention only needs one clamping resistor in each path, has simple structure and obviously reduces the layout area of the transceiver switch.
Drawings
Fig. 1 is a circuit diagram of a conventional rf transceiver switch.
FIG. 2 is a circuit diagram of a 0-40GHz ultra-wideband radio frequency transmit-receive switch using a novel clamping resistor.
Fig. 3 is a simulation result of the 0-40GHz ultra-wideband rf transceiving switch in the receiving mode according to the embodiment of the present invention, where (a) is insertion loss and (b) is isolation.
Fig. 4 is a simulation result of the 0-40GHz ultra-wideband rf transceiving switch in the transmission mode according to the embodiment of the present invention, where (a) is insertion loss and (b) is isolation.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and examples.
The embodiment provides a 0-40GHz ultra-wideband radio frequency transceiving switch using a novel clamping resistor, as shown in fig. 2, the radio frequency transceiving switch is divided into a transmitting path and a receiving path at a connecting antenna, the other end of the transmitting path is connected to a power amplifier of a transceiver, and the other end of the receiving path is connected to a low noise amplifier of the transceiver;
the transmission path includes: a parallel three-stacked NMOS transistor, a series two-stacked NMOS transistor, and a clamp resistor R; the parallel three-stacked NMOS transistor is composed of NMOS transistors M1-M3, and the drain electrode of the NMOS transistor M1 is connected with the receiving terminalIn the power amplifier of the engine, the source electrode of an NMOS transistor M1 is connected with the drain electrode of an NMOS transistor M2, the source electrode of the NMOS transistor M2 is connected with the drain electrode of an NMOS transistor M3, and the source electrode of the NMOS transistor M3 is grounded; the two stacked NMOS transistors connected in series are composed of NMOS transistors M4 and M5, the source electrode of the NMOS transistor M4 is connected with the drain electrode of the NMOS transistor M1, the drain electrode of the NMOS transistor M4 is connected with the source electrode of the NMOS transistor M5, and the drain electrode of the NMOS transistor M5 is connected with an antenna; the gates of the NMOS transistors M1 to M3 are respectively connected with resistors in series and then connected with a control signal V C1 The gates of NMOS transistors M4 and M5 are respectively connected in series with resistors and then connected with control signal V C2 The substrate terminals (Bulk) of the NMOS transistors M1-M5 are respectively connected with a series resistor and then connected with a bias voltage V B (ii) a One end of the clamp resistor R is connected between the source electrode of the NMOS transistor M1 and the drain electrode of the NMOS transistor M2, and the other end of the clamp resistor R is connected between the drain electrode of the NMOS transistor M4 and the source electrode of the NMOS transistor M5;
the receive path includes: a parallel two-stacked NMOS transistor, a series three-stacked NMOS transistor, and a clamp resistor R; the two parallel stacked NMOS transistors are composed of NMOS transistors M6 and M7, the drain electrode of the NMOS transistor M6 is connected with a low noise amplifier of the transceiver, the source electrode of the NMOS transistor M6 is connected with the drain electrode of the NMOS transistor M7, and the source electrode of the NMOS transistor M7 is grounded; the series three-stacked NMOS transistor is composed of NMOS transistors M8-M10, the source electrode of the NMOS transistor M8 is connected with the drain electrode of the NMOS transistor M6, the drain electrode of the NMOS transistor M8 is connected with the source electrode of the NMOS transistor M9, the drain electrode of the NMOS transistor M9 is connected with the source electrode of the NMOS transistor M10, and the drain electrode of the NMOS transistor M10 is connected with an antenna; the gates of the NMOS transistors M6 and M7 are respectively connected with resistors in series and then connected with a control signal V C2 The gates of NMOS transistors M8-M10 are respectively connected with series resistors and then connected with a control signal V C1 The substrate terminals (Bulk) of the NMOS transistors M6-M10 are respectively connected in series with resistors and then connected with a bias voltage V B (ii) a One end of the clamp resistor R is connected between the source of the NMOS transistor M6 and the drain of the NMOS transistor M7, and the other end is connected between the drain of the NMOS transistor M8 and the source of the NMOS transistor M9.
The working process of the 0-40GHz ultra-wideband radio frequency transceiving switch is as follows: when controlling the voltage V C1 Is high, V C2 Is lowWhen the antenna is in a transmitting mode, the transmitting channel parallel transistor is switched off, the series transistor is switched on, the receiving channel parallel transistor is switched on, the series transistor is switched off, the designed transceiving switch works in the transmitting mode, and signals are transmitted out from the power amplifier through the transmitting channel of the transceiving switch by the antenna; when controlling the voltage V C1 Is low, V C2 When the receiving channel is high, the parallel transistor of the receiving channel is switched off, the series transistor is switched on, the parallel transistor of the transmitting channel is switched on, the series transistor is switched off, the designed transceiving switch works in a receiving mode, and signals received from the antenna enter the low-noise amplifier through the receiving channel of the designed transceiving switch. In terms of working principle:
according to the invention, a clamping resistor is introduced between the series stacked transistor and the parallel stacked transistor to effectively inhibit the DC voltage drift phenomenon of the transceiving switch; taking the example of the switch operating in the emitting mode, as shown in FIG. 2, the transistor M is now in the emitting mode 1 ～M 3 Off, transistor M 4 、M 5 Conducting; there is no very large resistance from point B to zero (ground), while point A to zero is subject to a large resistance M 2 、M 3 The voltage division of the resistor is turned off, so that the direct current offset of the point B is far smaller than that of the point A; therefore, after connecting the point A and the point B through a resistor R with proper size, the point A can bypass the M 2 、M 3 The resistor is turned off, and a low-resistance path is used together with the point B, so that the direct current drift of the point A is reduced.
In the embodiment, all the stacked NMOS transistors have the same structure, the gate length L is 60nm, and the gate width W is 138 μm; the resistance values of all the transistor grid electrode series resistors, the Bulk series resistors and the clamping resistors are the same and are as follows: 16K omega; in particular, the present embodiment employs a negative voltage technique, the control voltage V C1 And a control voltage V C2 High 1.2V, low-1.2V, bias voltage V B is-1.2V.
The 0-40GHz ultra-wideband radio frequency transceiving switch in the present embodiment is tested, and the insertion loss and the isolation of the receiving and transmitting states are respectively shown in fig. 3 and 4; as can be seen from the figure, after the novel clamping resistor is introduced, the insertion loss of the receiving mode of the embodiment is less than 2dB from 0GHz to 40GHz, and the isolation is greater than 25dB; the insertion loss of a transmitting mode is less than 1.4dB at 0-40GHz, and the isolation is greater than 32dB; compared with the traditional clamping mode, the novel clamping resistor is simpler, the number is greatly reduced, the layout area is smaller, and the isolation degree and the insertion loss of the receiving and transmitting switch can be ensured to meet the application requirement.
While the invention has been described with reference to specific embodiments, any feature disclosed in this specification may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise; all of the disclosed features, or all of the method or process steps, may be combined in any combination, except mutually exclusive features and/or steps.

Claims (4)

1. An ultra-wideband radio frequency transmit-receive switch employing a clamping resistor, comprising: a transmit path and a receive path, wherein the transmit path comprises, from a receiver: the clamp resistor R is connected between the source electrode of the first-stage NMOS transistor in the parallel three-stacked NMOS transistor and the drain electrode of the first-stage NMOS transistor in the two stacked NMOS transistors in series; from the antenna, the receiving path includes: the NMOS transistor structure comprises a serial three-stacked NMOS transistor, a parallel two-stacked NMOS transistor and a clamping resistor R which are sequentially connected, wherein the clamping resistor R is connected between the drain electrode of a third-stage NMOS transistor in the serial three-stacked NMOS transistor and the source electrode of a first-stage NMOS transistor in the parallel two-stacked NMOS transistor.
2. The switch of claim 1, wherein in the transmit path, the three NMOS transistors in parallel stack are formed by NMOS transistors M1-M3, the drain of NMOS transistor M1 is connected to the transceiver, the source of NMOS transistor M1 is connected to the drain of NMOS transistor M2, the source of NMOS transistor M2 is connected to the drain of NMOS transistor M3, and the source of NMOS transistor M3 is grounded; the two stacked NMOS transistors connected in series are composed of NMOS transistors M4 and M5, the source electrode of the NMOS transistor M4 is connected with the drain electrode of the NMOS transistor M1, and the NMOS transistorThe drain electrode of the M4 is connected with the source electrode of the NMOS transistor M5, and the drain electrode of the NMOS transistor M5 is connected with the antenna; the gates of the NMOS transistors M1 to M3 are respectively connected with resistors in series and then connected with a control signal V C1 The gates of NMOS transistors M4 and M5 are respectively connected in series with resistors and then connected with control signal V C2 The substrate terminals (Bulk) of the NMOS transistors M1-M5 are respectively connected in series with resistors and then connected with a bias voltage V B (ii) a One end of the clamp resistor R is connected between the source electrode of the NMOS transistor M1 and the drain electrode of the NMOS transistor M2, and the other end of the clamp resistor R is connected between the drain electrode of the NMOS transistor M4 and the source electrode of the NMOS transistor M5;
in the receiving path, the two parallel stacked NMOS transistors are composed of NMOS transistors M6 and M7, the drain electrode of the NMOS transistor M6 is connected with the transceiver, the source electrode of the NMOS transistor M6 is connected with the drain electrode of the NMOS transistor M7, and the source electrode of the NMOS transistor M7 is grounded; the series three-stacked NMOS transistor is composed of NMOS transistors M8-M10, the source electrode of the NMOS transistor M8 is connected with the drain electrode of the NMOS transistor M6, the drain electrode of the NMOS transistor M8 is connected with the source electrode of the NMOS transistor M9, the drain electrode of the NMOS transistor M9 is connected with the source electrode of the NMOS transistor M10, and the drain electrode of the NMOS transistor M10 is connected with an antenna; the gates of the NMOS transistors M6 and M7 are respectively connected with a series resistor and then connected with a control signal V C2 The gates of NMOS transistors M8-M10 are respectively connected with series resistors and then connected with a control signal V C1 The substrate terminals (Bulk) of the NMOS transistors M6-M10 are respectively connected with a series resistor and then connected with a bias voltage V B (ii) a One end of the clamp resistor R is connected between the source electrode of the NMOS transistor M6 and the drain electrode of the NMOS transistor M7, and the other end is connected between the drain electrode of the NMOS transistor M8 and the source electrode of the NMOS transistor M9.
3. The uwb rf transceiver switch using clamp resistors of claim 2 wherein all NMOS transistors in the uwb rf transceiver switch are identical in structure and size.
4. The uwb rf transceiver switch using clamp resistors as defined in claim 2, wherein the clamp resistor R, all resistors connected in series to the gate of the NMOS transistor, and all resistors connected in series to the substrate of the NMOS transistor have the same resistance.
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