CN112929050A - Multichannel radio frequency transceiver chip - Google Patents
Multichannel radio frequency transceiver chip Download PDFInfo
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- CN112929050A CN112929050A CN202110281768.0A CN202110281768A CN112929050A CN 112929050 A CN112929050 A CN 112929050A CN 202110281768 A CN202110281768 A CN 202110281768A CN 112929050 A CN112929050 A CN 112929050A
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- radio frequency
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/005—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges
- H04B1/0064—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges with separate antennas for the more than one band
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Transceivers (AREA)
Abstract
The invention discloses a multichannel radio frequency transceiving chip, which comprises a power division synthesis network, a radio frequency port, a plurality of radio frequency transceiving channels and radio frequency antennas in one-to-one correspondence with the radio frequency transceiving channels; the radio frequency port is respectively connected with each radio frequency transceiving channel through a power dividing and combining network, and the radio frequency transceiving channels are also connected with corresponding radio frequency antennas; each radio frequency transceiving channel comprises a numerical control attenuator, a first selector switch, an AMP amplifier, a driving amplifier DRV, a second selector switch, a digital phase shifter, a third selector switch, a limiter, a low noise amplifier LNA, a power amplifier PA and a fourth selector switch; the first change-over switch, the second change-over switch, the third change-over switch and the fourth change-over switch are all single-pole double-throw switches. The invention integrates a plurality of radio frequency receiving and transmitting channels, can adopt different radio frequency channels and corresponding radio frequency antennas to complete signal receiving and transmitting in different directions, and provides convenience for the signal receiving and transmitting work.
Description
Technical Field
The invention relates to a radio frequency chip, in particular to a multi-channel radio frequency transceiver chip.
Background
The radio frequency chip has very wide application in communication, particularly in Ka band and even higher frequency band, and an integrated chip is often needed for signal receiving and transmitting so as to reduce the volume of equipment;
however, at present, the channel resource of the rf transceiver chip is limited, and signals can be transmitted and received only in one direction, which brings some inconvenience to the signal transceiving operation.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a multi-channel radio frequency transceiving chip, which integrates a plurality of radio frequency transceiving channels, can adopt different radio frequency channels and corresponding radio frequency antennas to complete signal transceiving in different directions and provides convenience for the transceiving work of signals.
The purpose of the invention is realized by the following technical scheme: a multi-channel radio frequency transceiving chip comprises a power division synthesis network, a radio frequency port, a plurality of radio frequency transceiving channels and radio frequency antennas which are in one-to-one correspondence with the radio frequency transceiving channels; the radio frequency port is respectively connected with each radio frequency transceiving channel through a power dividing and combining network, and the radio frequency transceiving channels are also connected with corresponding radio frequency antennas;
each radio frequency transceiving channel comprises a numerical control attenuator, a first selector switch, an AMP amplifier, a driving amplifier DRV, a second selector switch, a digital phase shifter, a third selector switch, a limiter, a low noise amplifier LNA, a power amplifier PA and a fourth selector switch; the first change-over switch, the second change-over switch, the third change-over switch and the fourth change-over switch are all single-pole double-throw switches;
one end of the numerical control attenuator is connected with the power dividing and synthesizing network, the other end of the numerical control attenuator is connected with the immobile end of the first switch, the input end of the AMP amplifier is connected with the mobile end of the second switch, the output end of the AMP amplifier is connected with the mobile end of the first switch, the input end of the drive amplifier DRV is connected with the other mobile end of the first switch, the output end of the drive amplifier DRV is connected with the other mobile end of the second switch, the immobile end of the second switch is also connected with the immobile end of the third switch through a digital phase shifter, the input end of the amplitude limiter is connected with the mobile end of the fourth switch, the output end of the amplitude limiter is connected with the mobile end of the third switch through a low noise amplifier LNA, the input end of the power amplifier is connected with the other mobile end of the third switch, the output end of the power amplifier is connected with the other movable end of the fourth change-over switch, and the fixed end of the fourth change-over switch is connected with the radio-frequency antenna.
Preferably, the number of the radio frequency transceiving channels and the number of the radio frequency antennas are four, the power dividing and combining network may include a 1-to-4 power divider, a combining end of the power divider is connected to the radio frequency port, and power dividing ends of the power divider are respectively connected to the four radio frequency transceiving channels; the power dividing and combining network may also include three 1-to-2 power dividers, where a combining end of a first power divider is connected to the radio frequency port, two power dividing ends of the first power divider are connected to a combining end of a second power divider and a combining end of a third power divider, and the power dividing ends of the second power divider and the third power divider are respectively connected to two radio frequency transceiving channels.
The invention has the beneficial effects that: the invention integrates a plurality of radio frequency receiving and transmitting channels, can adopt different radio frequency channels and corresponding radio frequency antennas to complete signal receiving and transmitting in different directions, and provides convenience for the signal receiving and transmitting work.
Drawings
FIG. 1 is a schematic diagram of the principles of the present invention;
fig. 2 is a schematic diagram of a power amplifier PA;
fig. 3 is a schematic diagram of a digital phase shifter.
Detailed Description
The technical solutions of the present invention are further described in detail below with reference to the accompanying drawings, but the scope of the present invention is not limited to the following.
As shown in fig. 1, a multi-channel rf transceiver chip includes a power division/synthesis network, an rf port, a plurality of rf transceiver channels, and rf antennas corresponding to the rf transceiver channels one to one; the radio frequency port is respectively connected with each radio frequency transceiving channel through a power dividing and combining network, and the radio frequency transceiving channels are also connected with corresponding radio frequency antennas;
each radio frequency transceiving channel comprises a numerical control attenuator, a first selector switch, an AMP amplifier, a driving amplifier DRV, a second selector switch, a digital phase shifter, a third selector switch, a limiter, a low noise amplifier LNA, a power amplifier PA and a fourth selector switch; the first change-over switch, the second change-over switch, the third change-over switch and the fourth change-over switch are all single-pole double-throw switches;
one end of the numerical control attenuator is connected with the power dividing and synthesizing network, the other end of the numerical control attenuator is connected with the immobile end of the first switch, the input end of the AMP amplifier is connected with the mobile end of the second switch, the output end of the AMP amplifier is connected with the mobile end of the first switch, the input end of the drive amplifier DRV is connected with the other mobile end of the first switch, the output end of the drive amplifier DRV is connected with the other mobile end of the second switch, the immobile end of the second switch is also connected with the immobile end of the third switch through a digital phase shifter, the input end of the amplitude limiter is connected with the mobile end of the fourth switch, the output end of the amplitude limiter is connected with the mobile end of the third switch through a low noise amplifier LNA, the input end of the power amplifier is connected with the other mobile end of the third switch, the output end of the power amplifier is connected with the other movable end of the fourth change-over switch, and the fixed end of the fourth change-over switch is connected with the radio-frequency antenna.
In an embodiment of the present application, the number of the radio frequency transceiving channels and the number of the radio frequency antennas are four, the power dividing and combining network may include a 1-to-4 power divider, a combining end of the power divider is connected to the radio frequency port, and power dividing ends of the power divider are respectively connected to the four radio frequency transceiving channels; the power dividing and combining network may also include three 1-to-2 power dividers, where a combining end of a first power divider is connected to the radio frequency port, two power dividing ends of the first power divider are connected to a combining end of a second power divider and a combining end of a third power divider, and the power dividing ends of the second power divider and the third power divider are respectively connected to two radio frequency transceiving channels.
As shown in FIG. 2, in the embodiment of the present application, the power amplifier PA includes field effect transistors T1-T3, resistors R1-R3, capacitors C1-C7, an inductor Lg, an inductor Ld, a signal input port RFin and a signal output port RFout; the drain electrode of the field effect transistor T3 is connected with a VDD power supply end through an inductor Ld, the source electrode of the field effect transistor T3 is connected with the drain electrode of the field effect transistor T2, the grid electrode of the field effect transistor T3 is connected with a Vg3 port through a resistor R3, a grounded capacitor C4 is further connected between the resistor R3 and the Vg3 port, and a grounded capacitor C3 is further connected between the resistor R3 and the grid electrode of the field effect transistor T3; the source electrode of the field effect transistor T2 is connected to the drain electrode of the field effect transistor T1, the grid electrode of the field effect transistor T2 is connected to the Vg2 port through a resistor R2, a grounded capacitor C5 is further connected between the resistor R2 and the Vg2 port, and a grounded capacitor C2 is further connected between the resistor R2 and the field effect transistor T2; the source of the field-effect tube T1 is grounded, the gate of the field-effect tube T1 is connected to the signal input port RFin sequentially through an inductor Lg and a capacitor C7, one end of the resistor R1 is connected between the inductor Lg and the gate of the field-effect tube T1, the other end of the resistor R1 is grounded through a capacitor C1, a grounded capacitor C6 is further connected between the inductor Lg and the capacitor C7, and a Vg1 port is further connected between the resistor R1 and the capacitor C1; the signal output port RFout is connected with the drain electrode of the field effect transistor T3;
the field effect transistors T1-T3 are all PMOS field effect transistors; the three ports Vg1, Vg2 and Vg3 are grid voltage ports and are used for being connected with starting voltages of field effect transistors T1, T2 and T3 respectively.
In the embodiment of the present application, the power amplifier further includes an inductor Lm and a capacitor Cm, one end of the inductor Lm is connected to the source of the fet T3, and the other end of the inductor Lm is grounded through the capacitor Cm.
As shown in fig. 3, the digital phase shifter includes a coupler including a first coupling part and a second coupling part, a first end of the first coupling part being connected to the signal input port through the first LC network, and a second end of the first coupling part being connected to the first load circuit; the second coupling section has a first end connected to the signal output port and a second end connected to the second load circuit. In the embodiment of the present application, the first LC network includes an inductor Lm1 and a capacitor Cm1, one end of the inductor Lm1 is connected to the first end of the first coupling unit, the other end of the inductor Lm1 is connected to the signal input port, one end of the capacitor Cm1 is connected between the inductor Lm1 and the signal input port, and the other end of the capacitor Cm1 is grounded.
In the embodiment of the present application, the second LC network includes an inductor Lm2 and a capacitor Cm2, one end of the inductor Lm2 is connected to the first end of the second coupling portion, the other end of the inductor Lm2 is connected to the signal output port, one end of the capacitor Cm2 is connected between the inductor Lm2 and the signal output port, and the other end of the capacitor Cm2 is grounded.
In an embodiment of the present application, the first load circuit and the second load circuit comprise the same circuit structure, and the circuit structure includes an inductor L1, an inductor L2, a variable capacitor Cv1, a variable capacitor Cv2, a resistor R4, a resistor R5, a resistor R6, a capacitor C8, and a capacitor C9;
one end of the resistor R6 is connected to a Vref port, the other end of the resistor R6 is grounded through an inductor L1, a variable capacitor Cv1 and a capacitor C8 in sequence, one end of the inductor L2 is connected to a common end of the resistor R6 and the inductor L1, and the other end of the inductor L2 is grounded through a variable capacitor Cv2 and a capacitor C9 in sequence; one end of the resistor R4 is connected between the variable capacitor Cv1 and the capacitor C8, and the other end of the resistor R4 is connected with a VC1 port; one end of the resistor R5 is connected between the variable capacitor Cv2 and the capacitor C9, and the second end of the resistor R5 is connected to the port VC 2;
for a circuit configuration in the first load circuit, the common terminal of the resistor R6 and the inductor L1 is connected to the second terminal of the first coupling section; for the circuit configuration in the second load circuit, the common terminal of the resistor R6 and the inductor L1 is connected to the second terminal of the second coupling section.
The working principle of the invention is as follows: during transmission, a radio frequency signal is divided into 4 paths with equal amplitude and equal phase through a 1-division-4-power-division synthesis network, the paths are respectively transmitted to the numerical control attenuators of all channels, and are transmitted to the SPDT switch after amplitude adjustment, at the moment, each switch working mode is at a transmitting end, the radio frequency signal is transmitted to the driving amplifier, is transmitted to the switch again after amplification, is transmitted to the digital phase shifter for phase adjustment through the switch, is transmitted to a transmitting branch through the switch for power amplification, and is output through the switch.
During receiving operation, radio frequency signals are input into each receiving and transmitting channel from each branch, the receiving branch is selected through a switch, the amplitude of the large signals is firstly limited, then low-noise amplification is carried out, the large signals are output to a digital phase shifter through the switch to carry out phase adjustment, then the small signals enter the receiving branch through the switch to carry out low-noise amplification again, the small signals are output to a digital attenuator through the switch to carry out amplitude adjustment, and finally the small signals are output through a 4-in-1 combiner.
In the invention, under the condition that the PA works in a current mode and the output is linear, if the VDD is higher, the Pout is higher and a large number of field effect transistor stacks are needed to ensure the reliability of the PA, however, the large number of field effect transistor stacks can cause the increase of parasitic capacitance or the reduction of PAE due to resistance loss; after three times of stacking is selected in the application, a matching network consisting of Lm and Cm is connected to the source of the fet T3, and the network is used for matching with the source impedance of the fet T3, so as to improve the impedance and improve the PAE of the power amplifier, and simulation shows that the PAE can be improved by 6%, and the structure does not cause too high loss even if an inductor with a medium quality factor is adopted, because the structure is not connected in series on the path of a main output signal; in consideration of power loss and voltage disturbance caused by overlapping, the invention adjusts voltage and current phases through R2/C2 and R3/C3 connected with the grid of the field effect transistor during design, thereby reducing overlapping, further reducing power loss and adjusting voltage disturbance, and further improving PAE of the power amplifier due to reduced loss.
In the embodiment of the application, the Vc1 port and the Vc2 port are variable-capacitance control ports, and the Vref port is connected with a fixed voltage; in the first load circuit, the capacitance value of the variable capacitor Cv1 is controlled by the control voltage input from the Vc1 port, the capacitance value of the variable capacitor Cv2 is controlled by the control voltage input from the Vc2 port, and after the capacitance values of the variable capacitor Cv1 and the variable capacitor Cv2 are changed, the resonant frequency of the LC resonant circuit (the resonant circuit formed by the variable capacitor Cv1 and the inductor L1 and the resonant circuit formed by the variable capacitor Cv2 and the inductor L2) in which the variable capacitor Cv2 and the variable capacitor Cv2 are respectively located is also changed, and the frequency difference between the resonant frequency and the resonant frequency (from the resonant frequency of the first coupling part) input from the outside is changed correspondingly to the phase shift; similarly, in the second load circuit, the frequency difference between the LC resonance circuit resonance frequency and the resonance frequency of the external input (resonance frequency from the second coupling section) changes in accordance with the phase shift; the phase shift value can be adjusted by adjusting the frequency difference in the first load circuit or the second load circuit (or adjusting the frequency difference together); in the first load circuit or the second load circuit, the frequency difference changes depending on the capacitance values of the variable capacitor Cv1 and the variable capacitor Cv2, and the capacitance values are controlled by the voltages of the Vc1 port and the Vc2 port, so that the capacitance changes due to the voltage changes, the frequency difference changes, the phase shift changes due to the frequency difference changes, and the phase shift can be realized. In the application, an LC network consisting of Lm1 and Cm1 and an LC network consisting of Lm2 and Cm2 are applied to the input and output ports, so that impedance conversion of the input and output ports is realized, and further relatively stable input and output impedance is maintained.
It should be noted that various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention, and those changes and modifications should fall within the scope of the appended claims.
Claims (4)
1. A multi-channel radio frequency transceiver chip is characterized in that: the system comprises a power division and synthesis network, a radio frequency port, a plurality of radio frequency transceiving channels and radio frequency antennas which are in one-to-one correspondence with the radio frequency transceiving channels; the radio frequency port is respectively connected with each radio frequency transceiving channel through a power dividing and combining network, and the radio frequency transceiving channels are also connected with corresponding radio frequency antennas;
each radio frequency transceiving channel comprises a numerical control attenuator, a first selector switch, an AMP amplifier, a driving amplifier DRV, a second selector switch, a digital phase shifter, a third selector switch, a limiter, a low noise amplifier LNA, a power amplifier PA and a fourth selector switch; the first change-over switch, the second change-over switch, the third change-over switch and the fourth change-over switch are all single-pole double-throw switches;
one end of the numerical control attenuator is connected with the power dividing and synthesizing network, the other end of the numerical control attenuator is connected with the immobile end of the first switch, the input end of the AMP amplifier is connected with the mobile end of the second switch, the output end of the AMP amplifier is connected with the mobile end of the first switch, the input end of the drive amplifier DRV is connected with the other mobile end of the first switch, the output end of the drive amplifier DRV is connected with the other mobile end of the second switch, the immobile end of the second switch is also connected with the immobile end of the third switch through a digital phase shifter, the input end of the amplitude limiter is connected with the mobile end of the fourth switch, the output end of the amplitude limiter is connected with the mobile end of the third switch through a low noise amplifier LNA, the input end of the power amplifier is connected with the other mobile end of the third switch, the output end of the power amplifier is connected with the other movable end of the fourth change-over switch, and the fixed end of the fourth change-over switch is connected with the radio-frequency antenna.
2. The multi-channel radio frequency transceiver chip of claim 1, wherein: the number of the radio frequency transceiving channels and the number of the radio frequency antennas are four.
3. The multi-channel radio frequency transceiver chip of claim 2, wherein: the power dividing and combining network comprises a 1-4 power divider, a combining end of the power divider is connected with a radio frequency port, and power dividing ends of the power divider are respectively connected to four radio frequency transceiving channels.
4. The multi-channel radio frequency transceiver chip of claim 2, wherein: the power dividing and combining network comprises three 1-to-2 power dividers, wherein a combining end of a first power divider is connected with a radio frequency port, two power dividing ends of the first power divider are respectively connected to a combining end of a second power divider and a combining end of a third power divider, and the power dividing ends of the second power divider and the third power divider are respectively connected with two radio frequency transceiving channels.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110281768.0A CN112929050A (en) | 2021-03-16 | 2021-03-16 | Multichannel radio frequency transceiver chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110281768.0A CN112929050A (en) | 2021-03-16 | 2021-03-16 | Multichannel radio frequency transceiver chip |
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| CN112929050A true CN112929050A (en) | 2021-06-08 |
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| CN202110281768.0A Pending CN112929050A (en) | 2021-03-16 | 2021-03-16 | Multichannel radio frequency transceiver chip |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113824466A (en) * | 2021-08-30 | 2021-12-21 | 电子科技大学 | Ultra-wideband radio frequency transceiving switch adopting novel clamping resistor |
| CN115378456A (en) * | 2022-10-25 | 2022-11-22 | 成都嘉纳海威科技有限责任公司 | Receiving and transmitting amplifying attenuation multifunctional chip |
| CN116094536A (en) * | 2023-01-13 | 2023-05-09 | 南京燧锐科技有限公司 | Multi-channel radio frequency chip structure |
-
2021
- 2021-03-16 CN CN202110281768.0A patent/CN112929050A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113824466A (en) * | 2021-08-30 | 2021-12-21 | 电子科技大学 | Ultra-wideband radio frequency transceiving switch adopting novel clamping resistor |
| CN115378456A (en) * | 2022-10-25 | 2022-11-22 | 成都嘉纳海威科技有限责任公司 | Receiving and transmitting amplifying attenuation multifunctional chip |
| CN116094536A (en) * | 2023-01-13 | 2023-05-09 | 南京燧锐科技有限公司 | Multi-channel radio frequency chip structure |
| CN116094536B (en) * | 2023-01-13 | 2024-03-12 | 南京燧锐科技有限公司 | Multi-channel radio frequency chip structure |
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