CN116094536A

CN116094536A - Multi-channel radio frequency chip structure

Info

Publication number: CN116094536A
Application number: CN202310042579.7A
Authority: CN
Inventors: 战吉超; 李南
Original assignee: Nanjing Suirui Technology Co ltd
Current assignee: Nanjing Suirui Technology Co ltd
Priority date: 2023-01-13
Filing date: 2023-01-13
Publication date: 2023-05-09
Anticipated expiration: 2043-01-13
Also published as: CN116094536B

Abstract

The invention relates to a multichannel radio frequency chip structure. The multi-channel radio frequency chip structure comprises a radio frequency transceiver chip with a plurality of channels, wherein each channel comprises a radio frequency transmitting channel and a radio frequency receiving channel, and the channels are divided into a plurality of groups of channels; a plurality of decoupling capacitors, each of the decoupling capacitors being configured to mate with a respective set of channels and being disposed in parallel with the set of channels; the distances between the decoupling capacitors and the radio frequency transceiver chip are smaller than a set value, so that the key performance of the radio frequency transceiver chip meets the requirement. The invention sets the distance between the decoupling capacitors and the radio frequency transceiver chip to be smaller than the set value, can reduce the impedance seen from the power amplifier to the power supply network, and can reduce the interference between multiple channels on key performance so as to enable the key performance of the radio frequency transceiver chip to meet the requirement.

Description

Multi-channel radio frequency chip structure

Technical Field

The invention relates to a multichannel radio frequency chip structure.

Background

In the circuit design of a semiconductor chip, a decoupling capacitor is generally required to be added, and the decoupling capacitor is generally connected in parallel to a power supply terminal, so that the power supply can provide a relatively stable power supply signal, and meanwhile, noise of coupling each element in the semiconductor chip to the power supply terminal can be reduced, and influence of noise of other elements on the element can be reduced indirectly.

However, this decoupling capacitance in turn affects the critical performance of the semiconductor chip.

Disclosure of Invention

The object of the present invention is to provide a multi-channel radio frequency chip architecture that reduces the impedance seen from the power amplifier towards the power supply network and that reduces the interference between the multiple channels on the critical performance.

The invention discloses a multichannel radio frequency chip structure, which comprises:

a radio frequency transceiver chip having a plurality of channels, each channel comprising a radio frequency transmit path and a radio frequency receive path, the plurality of channels being divided into a plurality of groups of channels;

a plurality of decoupling capacitors, each of the decoupling capacitors being configured to mate with a respective set of channels and being disposed in parallel with the set of channels;

the distances between the decoupling capacitors and the radio frequency transceiver chip are smaller than a set value, so that the key performance of the radio frequency transceiver chip meets the requirement.

Optionally, the set value is less than or equal to 145um.

Optionally, the distances between the decoupling capacitors and the radio frequency transceiver chip are all greater than or equal to 130um.

Optionally, the radio frequency transceiver chip has a plurality of power lines, and a group of channels share one power line for electrically connecting with an external power source, so that the external power source supplies power to the group of channels;

one end of the decoupling capacitor corresponding to the group of channels is electrically connected with the shared power line, and the other end is grounded.

Optionally, the radio frequency transceiver chip and the decoupling capacitors are encapsulated on the substrate.

Optionally, the plurality of decoupling capacitors are encapsulated on a surface of the substrate or inside the substrate.

Optionally, the distances between the decoupling capacitors and the radio frequency transceiver chip are all greater than or equal to the processing dimension of the packaging process.

Optionally, the radio frequency transceiver chip and the decoupling capacitors are packaged on the substrate through a packaging process of a flip chip wire grid array or a flip chip ball grid array;

arranging a substrate wire on the first surface of the substrate, and arranging a conductive plug in the substrate so as to electrically connect the radio frequency transceiver chip and the decoupling capacitors;

and a second surface of the substrate opposite to the first surface is provided with a packaging pin electrically connected with the conductive plug and the substrate wire, so that the radio frequency transceiver chip and the decoupling capacitors are respectively electrically connected with an external power supply.

Optionally, the number of groups of the plurality of groups of channels is at least 2 and at most the number of channels.

Optionally, the radio frequency transceiver chip has 8, 16 or 32 channels, 8 channels are divided into 2 or 4 groups, 16 channels are divided into 2 or 4 or 8 groups, and 32 channels are divided into 4 or 8 or 16 groups.

Optionally, the radio frequency transmission path comprises an amplifier, a radio frequency switch, a power division network, a phase shifter, an attenuator, a power amplifier and a transmission line;

the radio frequency receiving path comprises a transmission line, a low noise amplifier, a phase shifter, an attenuator, a power division network, a radio frequency switch and an amplifier.

Optionally, the decoupling capacitor is disposed at a peripheral edge of the radio frequency transceiver chip, and the distance is a shortest distance between the decoupling capacitor and the peripheral edge of the radio frequency transceiver chip;

or the decoupling capacitor and the radio frequency receiving and transmitting chip are provided with overlapped parts, and the distance is the vertical distance between the decoupling capacitor and the opposite surface of the radio frequency receiving and transmitting chip.

Optionally, the substrate is configured to be disposed on a PCB, or the substrate is a PCB.

Compared with the prior art, the invention has the main differences and effects that:

the invention sets the distance between the decoupling capacitors and the radio frequency transceiver chip to be smaller than the set value, can reduce the impedance seen from the power amplifier to the power supply network, and can reduce the interference between multiple channels on key performance so as to enable the key performance of the radio frequency transceiver chip to meet the requirement.

Drawings

FIG. 1 is a schematic top plan view of a multi-channel radio frequency chip structure according to an embodiment of the invention;

FIG. 2 is a schematic cross-sectional view of a multi-channel RF chip structure according to an embodiment of the invention;

FIG. 3 is a schematic circuit diagram of a multi-channel RF chip structure according to an embodiment of the invention;

fig. 4 is a circuit schematic of a multi-channel rf chip structure according to a comparative example of the present invention.

Detailed Description

In order to make the purpose and technical solutions of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without creative efforts, based on the described embodiments of the present invention fall within the protection scope of the present invention.

However, the inventors of the present application have found that the key performance of semiconductor chips employing such circuit designs, such as various existing radio frequency chips and mid-low frequency chips, can be affected. For example, when the semiconductor chip is a radio frequency transceiver chip having a plurality of channels, such as when the plurality of channels are turned on, there may be an interaction in key performance between the different channels. After long-term testing, experimentation, and repeated research, the inventors have found that the decoupling capacitance is affecting the critical performance of the semiconductor chip, and more specifically, the distance between the decoupling capacitance and the semiconductor chip is affecting the critical performance of the semiconductor chip.

Based on this, the application proposes a multichannel radio frequency chip structure, including: a radio frequency transceiver chip having a plurality of channels, each channel comprising a radio frequency transmit path and a radio frequency receive path, the plurality of channels being divided into a plurality of groups of channels; a plurality of decoupling capacitors, each of the decoupling capacitors being configured to mate with a respective set of channels and being disposed in parallel with the set of channels; the distances between the decoupling capacitors and the radio frequency transceiver chip are smaller than a set value, so that the key performance of the radio frequency transceiver chip meets the requirement.

The distances between the decoupling capacitors and the radio frequency transceiver chip are set to be smaller than the set value, so that the impedance seen from the power amplifier to the power supply network can be reduced, and interference on key performance among multiple channels can be reduced, so that the key performance of the radio frequency transceiver chip meets the requirement.

Fig. 1 to 3 are a top view, a side view and a circuit diagram of a multi-channel rf chip structure according to the present invention, respectively, and embodiments of the present invention are described in detail below with reference to fig. 1 to 3.

Referring to fig. 1 and 3, the multi-channel radio frequency chip structure 100 includes a radio frequency transceiver chip 101 having a plurality of channels 1011-1014. It will be appreciated that only four channels and two decoupling capacitors are shown in the figures, but the number of channels and decoupling capacitors is not shown in full in the columns of the figures, and that the number of channels and decoupling capacitors is more than that shown in the figures.

In the embodiment of the present application, the number of channels may be 8 channels, 16 channels, or 32 channels. In the example shown in the figure, there are one set of every two channels, each set of channels matching a decoupling capacitor. The channel 1011 and the channel 1012 are a group, the decoupling capacitor 102A is matched, and the decoupling capacitor 102A is arranged in parallel with the group of channels; the

channels

1013 and 1014 are a group, matching the decoupling capacitance 102B, the decoupling capacitance 102B being arranged in parallel with the group of channels. It will be appreciated that although only two channels are shown here as an example of one group, the number of groups of channels in the present application is not limited to this division, but the number of groups of channels is at least 2 and at most one decoupling capacitor is configured for the number of channels, i.e. each channel. The division of the number of groups of specific channels may be considered according to the requirements of the chip design, and the location space in which decoupling capacitors may be able to be provided. Alternatively, the radio frequency transceiver chip 101 has 8, 16, or 32 channels, 8 channels are divided into 2 groups or 4 groups, 16 channels are divided into 2 groups or 4 groups or 8 groups, and 32 channels are divided into 4 groups or 8 groups or 16 groups.

The number of decoupling capacitors matched per set of channels is one, but may not be limited to one. These decoupling capacitors 102A-102B are connected in parallel to the power supply terminals 201A-201B, respectively, for electrical connection with an external power supply, respectively. It will be appreciated that the external power source may be the same power source or may be a different power source.

In general, the decoupling capacitors 102A-102B are all preferably located closer to the power terminals 201A-201B and farther from the RF transceiver chip 101. However, the inventors have found that the critical performance of the rf transceiver chip 101 may be affected at this time, such as when multiple channels are opened, the critical performance of the different channels may be affected. After long testing, trial and error, the present inventors have found that if the decoupling capacitors 102A-102B are located as close to the rf transceiver chip 101 as possible and far from the power supply terminals 201A-201B as opposed to the existing decoupling capacitors, i.e., when the distance d between the decoupling capacitors 102A-102B and the rf transceiver chip 101 is smaller than the set value, the key performance of the rf transceiver chip 101 is significantly improved through the testing.

Optionally, the set value is 145um or less. In addition, the distance d between the decoupling capacitors 102A-102B and the rf transceiver chip 101 should not be too small, and alternatively, the distance d is not less than 130um (micrometers), which is the minimum size of the current processing technology, and if the minimum size of the processing technology can be further reduced, the distance d can be further reduced, and is not limited to the minimum distance of 130um.

Referring to fig. 3, specifically, the radio frequency transmission paths 1011A to 1014A include AMP (amplifier), a radio frequency switch (not shown in the figure), a power division network, a phase-shift attenuation circuit (including a phase shifter and an attenuator), PA (power amplifier), and a transmission line which are connected in order in the transmission direction of the transmission path signal; the radio frequency receive paths 1011B-1014B include transmission lines, LNAs (low noise amplifiers), phase-shifting attenuation circuits (including phase shifters and attenuators), power division networks, radio frequency switches (not shown), and AMPs (amplifiers). The radio frequency transmit paths 1011A-1014A and the radio frequency receive paths 1011B-1014B share a power division network which, in a transmit state, divides signals input from the common ports CMOMH, CMOMV equally into the respective channels 1011-1014, and, in a receive state, synthesizes signals received from the respective channels 1011-1014 into the common ports CMOMH, CMOMV. Wherein the common port CMOMH, CMOMV represents the common ports for signals of different polarization directions.

In addition, the radio frequency transceiver chip 101 further includes ASPI, analog circuits analog and PAD Ring, and other functional parts.

It should be noted that the circuit schematic diagram of fig. 3 and the elements of the respective paths described in the present application are only an example of the present application, and assist understanding the present application. The elements included in each path in the present application may not be limited to the above-listed elements, and different elements and connection relationships between each other may be set according to the actual radio frequency transceiver chip.

With continued reference to fig. 1 and 3, the radio frequency transceiver chip 101 has a plurality of power lines 202A-202B. One end of the decoupling capacitor 102A-102B corresponding to the set of channels is electrically connected to the common power line 202A-202B and the other end is grounded.

Referring to fig. 2 in combination, the multi-channel rf chip structure 100 further includes a substrate 103, and the rf transceiver chip 101 and the decoupling capacitors 102 are all encapsulated in the substrate 103. Specifically, the plurality of decoupling capacitors 102 are encapsulated on the surface of the substrate 103 or inside the substrate 103. In the case of packaging, the distance d between the decoupling capacitors 102 and the rf transceiver chip 101 should be greater than or equal to the processing dimension of the packaging process.

Decoupling capacitors 102 may also be designed within rf transceiver chip 101, as the design and chip size permits.

Here, a case where a plurality of decoupling capacitors 102 are packaged on the surface of the substrate 103 is shown, the radio frequency transceiver chip 101 and the plurality of decoupling capacitors 102 are packaged on the substrate 103 by a packaging process of a flip chip wire grid array (Flip Chip Line Grid Array, FCLGA) or a flip chip ball grid array (Flip Chip Ball Grid Array, FCBGA), and are packaged in a package 104A (the material of the package may be an organic package material), wherein a ball mounting (bumping) 104B is performed on the radio frequency transceiver chip 101, the radio frequency transceiver chip 101 after ball mounting is flip-mounted on a first surface (i.e., front surface) 103A of the substrate 103 of a corresponding design, and electrical connection of corresponding wires (such as a power supply wire, a signal wire, a radio frequency wire, a ground, etc.) within the radio frequency transceiver chip 101 is achieved through the ball mounting 104B and a substrate trace 103C to be described below, and a package is covered around the radio frequency transceiver chip 101 and the plurality of decoupling capacitors 102 to form the package 104A.

A substrate trace 103C is disposed on the first surface 103A of the substrate 103, and a conductive plug 103D is disposed inside the substrate 103, so as to electrically connect the rf transceiver chip 101 and the decoupling capacitors 102 to each other. A package pin 103E electrically connected to the conductive plug 103D and the substrate trace 103C is disposed on a second surface 103B of the substrate 103 opposite to the first surface 103A, so that the radio frequency transceiver chip 101 and the decoupling capacitors 102 are electrically connected to an external power supply, respectively.

In the embodiment shown in fig. 2, the decoupling capacitor 102 is encapsulated on the first surface 103A of the substrate 103 facing the radio frequency transceiver chip 101, and in other embodiments of the present invention, the decoupling capacitor 102 may also be encapsulated inside the substrate 103, where the distance between the decoupling capacitor 102 and the radio frequency transceiver chip 101 refers to the vertical distance between the two opposite directions when the decoupling capacitor is encapsulated inside the substrate 103. The distance also needs to meet a set value, optionally less than or equal to 145um. In addition, the distance d between the decoupling capacitor 102 and the rf transceiver chip 101 should not be too small, and optionally, the distance d is greater than or equal to 130um (micrometers), which is the minimum size of the current processing technology, and if the minimum size of the processing technology can be further reduced, the distance d can be further reduced, and is not limited to the minimum distance of 130um.

When the decoupling capacitor 102 is packaged in the substrate 103, it may be set that an independent decoupling capacitor 102 is set for each channel, so that the improvement of the key performance of the radio frequency transceiver chip 101 may be better achieved.

In other embodiments of the present invention, if the second surface (i.e., the back surface) 103B of the substrate 103 does not need to be provided with another substrate (such as a PCB board 104 to be described below), the decoupling capacitor 102 may be disposed on the second surface 103B of the substrate 103, where the decoupling capacitor 102 may not have an overlapping area with the rf transceiver chip 101, or may be disposed overlapping with the rf transceiver chip 101. But it is necessary to ensure that the horizontal distance or vertical distance between the decoupling capacitor 102 and the rf transceiver chip 101, when facing up and down, satisfies the distance range described in the above embodiments, and will not be described here again.

In the embodiment of the present invention, the position of the decoupling capacitor 102 on the first surface 103A of the substrate 103 may be located at any position around the substrate 103 on the premise of meeting the set distance, and the number of the decoupling capacitors 102 may be set according to the actual situation, which is not limited to the setting of a set of channels and one decoupling capacitor in the embodiment.

In the embodiment of the present invention, after the rf transceiver chip 101 and the decoupling capacitor 102 are packaged on the substrate 103, the substrate 103 is disposed on the PCB 104; in other embodiments of the present invention, the substrate 103 and the PCB 104 may be integrated, that is, the decoupling capacitor 102 and the rf transceiver chip 101 are disposed on the PCB 104 together, and the substrate 103 in the present invention refers to the PCB 104. When the substrate 103 is a PCB 104, the decoupling capacitor 102 may be disposed on the front side, the back side, or the inside of the PCB 104. The positional relationship between the decoupling capacitor 102 and the rf transceiver chip 104 may be: the decoupling capacitor 102 is not overlapped with the rf transceiver chip 101 or is heavy up and down, so that the horizontal distance between the decoupling capacitor 102 and the rf transceiver chip 101 or the vertical distance between them meet the distance range described in the above embodiments, which is not described herein.

The principle of the invention will be described in detail with reference to fig. 3 and 4. Similar to fig. 3, referring to fig. 4, the radio frequency transceiver chip 101 has a plurality of channels 1011-1014, each including a radio frequency transmission path 1011A-1014A. Decoupling capacitors 102A-102B are each configured to match a corresponding set of channels and are disposed in parallel with the set of channels.

Specifically, the circuit of the radio frequency transceiver chip of the comparative example of fig. 4 is the same as the circuit configuration described in the embodiment of fig. 3.

The decoupling capacitors 102A-102B of fig. 3 are packaged on a substrate 103, and the substrate 103 is disposed on a PCB board 104. As a comparative example, whereas the decoupling capacitors 102A-102B of fig. 4 are packaged on a PCB board, one end is electrically connected to the common power supply line 202A-202B, and the other end is grounded, the distance between the decoupling capacitors 102A-102B and the rf transceiver chip 101 is greater in the comparative example of fig. 4 than in the embodiment of fig. 3.

Referring to fig. 4, by way of analysis, the inventors further found that when the corresponding amplifier (such as a power amplifier, etc.) in each set of channels is brought out to the power supply terminals 201A-201B, there are parasitic inductances Lh1, lv1, lhv1, lp1, where parasitic inductances Lh1 and Lv1 are parasitic inductances between different channel power access points to power supply pins on the substrate, lhv1 is a parasitic inductance between different channel power supply access points, and parasitic inductance Lp1 is a parasitic inductance between the substrate power supply pins to solder capacitance locations on the PCB board. These parasitic inductances 400 are equivalent inductances of the metal wires, and are not real devices, and can be equivalently analyzed. The larger these parasitic inductances 400, the greater the impedance from the PA (power amplifier) to the power supply network, and the greater the impact on the critical performance interference between the system channels. Therefore, there is a need to reduce the influence of the parasitic inductance 400 as much as possible.

However, there are design limits due to layout position limitations; to solve the problem that the existing channels interfere with each other, the inventors tried various schemes including:

1. the choice of different soldering locations, generally the closer the soldering locations of the decoupling capacitors 102 are to the package pins, the better;

2. the decoupling capacitor 102 is selected, so that the size is reduced as much as possible, and the parasitic inductance of the device is reduced;

3. changing the power supply wiring design scheme of the PCB 104, and reducing parasitic inductance Lp1 as much as possible;

4. changing the power supply wiring design scheme of the substrate 103, making the power supply surface large, and reducing parasitic inductance Lh1 as much as possible; the different channel power supplies are grouped to reduce mutual interference, but the more the grouping is, the larger the parasitic inductance Lh1 of each power supply line is due to layout influence.

The above solutions have a tendency to benefit, but none of them completely solve the problem.

In analysis and test, the inventor finds that the distance between the decoupling chip and the radio frequency transceiver chip has a great influence on the key performance of the device, so that the decoupling capacitor 102 is tried to be packaged on the substrate 103, and the parasitic inductance Lp1 on the PCB 104 can be shielded, so that the overall equivalent inductance is effectively reduced.

Referring back to fig. 3, when the corresponding amplifier (such as a power amplifier) in each set of channels is brought out to the power supply terminal 201A-201B, since the decoupling capacitors 102A-102B are equivalent to ground for the target frequency signal, the parasitic inductance 300 seen from the power amplifier to the power supply network is mainly the substrate parasitic inductances Lh1, lv 1.

In the present invention, the decoupling capacitor is preferably a ceramic capacitor having a large capacitance density, a small size, a low-frequency impedance, and a high withstand voltage, and the capacitance of the decoupling capacitor may be about 1 uA.

It should be noted that in the claims and the description of this patent, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

Claims

1. A multi-channel radio frequency chip structure comprising:

2. The multi-channel rf chip structure of claim 1 wherein the set value is less than or equal to 145um.

3. The multi-channel radio frequency chip structure of claim 1, wherein the distances between the plurality of decoupling capacitors and the radio frequency transceiver chip are all greater than or equal to 130um.

4. The multi-channel rf chip structure of claim 1, wherein the rf transceiver chip has a plurality of power lines, a group of channels sharing one power line for electrically connecting with an external power source, such that the external power source supplies power to the group of channels;

5. The multi-channel rf chip structure of claim 1, further comprising a substrate, the rf transceiver chip and the plurality of decoupling capacitors being encapsulated in the substrate.

6. The multi-channel radio frequency chip structure of claim 5, wherein the plurality of decoupling capacitors are encapsulated on a surface of the substrate or within the substrate.

7. The multi-channel rf chip structure of claim 5, wherein the distances between the decoupling capacitors and the rf transceiver chip are all greater than or equal to a process dimension of a packaging process.

8. The multi-channel rf chip structure of claim 5, wherein the rf transceiver chip and the plurality of decoupling capacitors are packaged on the substrate by a flip-chip wire grid array or a flip-chip ball grid array packaging process;

9. The multi-channel radio frequency chip structure of claim 1, wherein the number of groups of the plurality of groups of channels is at least 2 and at most the number of channels.

10. The multi-channel radio frequency chip structure of claim 9, wherein the radio frequency transceiver chip has 8, 16 or 32 channels, 8 channels are divided into 2 or 4 groups, 16 channels are divided into 2 or 4 or 8 groups, and 32 channels are divided into 4 or 8 or 16 groups.

11. The multi-channel radio frequency chip architecture of claim 1, wherein the radio frequency transmit path comprises an amplifier, a radio frequency switch, a power division network, a phase shifter, an attenuator, a power amplifier, and a transmission line;

12. The multi-channel radio frequency chip structure according to claim 1, wherein the decoupling capacitor is disposed at a peripheral edge of the radio frequency transceiver chip, and the distance is a shortest distance between the decoupling capacitor and the peripheral edge of the radio frequency transceiver chip;

13. The multi-channel radio frequency chip structure of claim 6, wherein the substrate is configured to be disposed on a PCB or the substrate is a PCB.