CN110380708B - Ultra-wideband amplitude-phase compensation digital switch attenuator circuit - Google Patents
Ultra-wideband amplitude-phase compensation digital switch attenuator circuit Download PDFInfo
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Abstract
本发明公开一种超宽带幅相补偿数字衰减器电路，电路由n个衰减单元通过电感匹配级联而成，所述的n个衰减单元采用简化结构的T型电路、带补偿结构的bridge‑T拓扑结构和带相位补偿结构的π型拓扑结构中的任意一种或多种。本电路拓扑结构简单，带有相位补偿结构可实现超宽带工作范围，具有低相位误差、低插入损耗、衰减精度高的特点，可以采用微波单片集成电路工艺技术进行大批量生产。
The invention discloses an ultra-wideband amplitude-phase compensation digital attenuator circuit. The circuit is formed by cascaded n attenuation units through inductance matching. Any one or more of T topology and π-type topology with phase compensation structure. The circuit has a simple topology structure, and has a phase compensation structure that can achieve an ultra-wideband operating range. It has the characteristics of low phase error, low insertion loss, and high attenuation accuracy. It can be mass-produced by microwave monolithic integrated circuit technology.
Description
技术领域technical field
本发明涉及射频集成电路领域，具体涉及一种超宽带幅相补偿数字开关衰减器电路。The invention relates to the field of radio frequency integrated circuits, in particular to an ultra-wideband amplitude and phase compensation digital switch attenuator circuit.
背景技术Background technique
衰减器是无线通信、相控阵雷达和仪器仪表系统的关键组成模块之一，其主要功能是提供幅度控制，来实现线性调整增益、增大动态范围的目的。在现有技术中，大多数步进衰减器依赖于三种基本拓扑类型：π型衰减器、T型衰减器、bridge-T型衰减器。在这些设计中，通过衰减单元的开关晶体管工作状态来确定信号是旁通还是衰减，因此这些类型的衰减器高度依赖于开关晶体管的性能，但是晶体管的寄生参数常常使得衰减状态下的附加相移变得较大，导致衰减器在使用过程中引入了不必要的相位波动。Attenuator is one of the key components of wireless communication, phased array radar and instrumentation systems. Its main function is to provide amplitude control to achieve the purpose of linearly adjusting gain and increasing dynamic range. In the prior art, most step attenuators rely on three basic topological types: pi-type attenuators, T-type attenuators, bridge-T-type attenuators. In these designs, the switching transistor operating state of the attenuation unit determines whether the signal is bypassed or attenuated, so these types of attenuators are highly dependent on the performance of the switching transistor, but the parasitics of the transistor often cause an additional phase shift in the attenuation state becomes larger, causing the attenuator to introduce unwanted phase fluctuations during use.
发明内容SUMMARY OF THE INVENTION
针对现有技术的不足，本发明提出一种超宽带幅相补偿数字开关衰减器电路，可以有效减少晶体管寄生带来的附加移相，拓宽带宽，提升精度。In view of the deficiencies of the prior art, the present invention proposes an ultra-wideband amplitude-phase compensation digital switch attenuator circuit, which can effectively reduce the additional phase shift caused by transistor parasitics, widen the bandwidth and improve the precision.
本发明的目的通过如下技术方案来实现：The object of the present invention is achieved through the following technical solutions:
一种超宽带幅相补偿数字衰减器电路，其特征在于，所述的电路由n个衰减单元通过电感匹配级联而成，所述的n个衰减单元采用简化结构的T型电路、带补偿结构的bridge-T拓扑结构和带补偿结构的π型拓扑结构中的任意一种或多种；所述的简化结构的T型电路由电阻Rb1、Rb2、晶体管Mb1组成，且有两个端口Pb1、Pb2，其中，端口Pb2接到射频信号通路上作为旁路，Pb1为控制信号输入，其连接电阻Rb1的一端，Rb1的另一端连接晶体管Mb1的栅极，Mb1的漏极连接端口Pb2，Mb1的源极连接电阻Rb2的一端，电阻Rb2的另一端接地；An ultra-wideband amplitude-phase compensation digital attenuator circuit, characterized in that the circuit is formed by cascaded n attenuation units through inductance matching, and the n attenuation units adopt a T-shaped circuit with a simplified structure, with compensation Any one or more of the bridge-T topology structure and the π-type topology structure with compensation structure; the simplified structure T-type circuit is composed of resistors Rb1, Rb2, transistor Mb1, and has two ports Pb1 , Pb2, wherein, the port Pb2 is connected to the radio frequency signal path as a bypass, Pb1 is the control signal input, it is connected to one end of the resistor Rb1, the other end of Rb1 is connected to the gate of the transistor Mb1, and the drain of Mb1 is connected to ports Pb2, Mb1 The source is connected to one end of the resistor Rb2, and the other end of the resistor Rb2 is grounded;
所述的带补偿结构的bridge-T拓扑结构由电阻Ra1、Ra2、Ra3、Ra4、Ra5、Ra6、Ra7、Ra8、晶体管Ma1、Ma2、Ma3、电容Ca1组成，且有五个端口，分别是IN、OUT、Pa1、Pa2、Pa3，其中射频信号输入从IN端口进入，从OUT端口输出，Pa1、Pa2、Pa3为晶体管的控制信号输入端口；IN端口与电阻Ra2、Ra5的一端、晶体管Ma2的漏极相接，电阻Ra2的另一端与电容Ca1的一端以及Ra3的一端相接，电容Ca1的另一端和Ma1的漏极相接，Ma1的栅极和电阻Ra1相接，晶体管Ma1的源极接地。电阻Ra1的另一端和控制端口Pa1相接，电阻Ra3另一端与Ra6的一端以及晶体管Ma2的源极都和OUT端口相接，晶体管Ma2的栅极通过电阻Ra4和控制端口Pa2相接。电阻Ra5的另一端、电阻Ra6的另一端、晶体管Ma3的漏极连接在一起，晶体管Ma3的栅极通过电阻Ra7和控制端口Pa3连接在一起。晶体管Ma3的源极通过电阻Ra8接地；The bridge-T topology with compensation structure is composed of resistors Ra1, Ra2, Ra3, Ra4, Ra5, Ra6, Ra7, Ra8, transistors Ma1, Ma2, Ma3, and capacitors Ca1, and has five ports, which are IN , OUT, Pa1, Pa2, Pa3, in which the RF signal input enters from the IN port and outputs from the OUT port, Pa1, Pa2, Pa3 are the control signal input ports of the transistor; the IN port and one end of the resistors Ra2 and Ra5, the drain of the transistor Ma2 The other end of the resistor Ra2 is connected to one end of the capacitor Ca1 and one end of Ra3, the other end of the capacitor Ca1 is connected to the drain of Ma1, the gate of Ma1 is connected to the resistor Ra1, and the source of the transistor Ma1 is connected to the ground . The other end of the resistor Ra1 is connected to the control port Pa1, the other end of the resistor Ra3 is connected to one end of Ra6 and the source of the transistor Ma2 is connected to the OUT port, and the gate of the transistor Ma2 is connected to the control port Pa2 through the resistor Ra4. The other end of the resistor Ra5, the other end of the resistor Ra6, and the drain of the transistor Ma3 are connected together, and the gate of the transistor Ma3 is connected together through the resistor Ra7 and the control port Pa3. The source of the transistor Ma3 is grounded through the resistor Ra8;
所述的带补偿结构的π型拓扑结构由电阻Rc1、Rc2、Rc3、Rc4、Rc5、Rc6、Rc7、Rc8，电容Cc1，晶体管Mc1、Mc2、Mc3、Mc4组成，且有五个端口分别是IN、OUT、Pc1、Pc2、Pc3，其中，射频信号输入从IN端口进入，从OUT端口输出，Pc1、Pc2、Pc3为晶体管的控制信号输入端口，IN端口与电阻Rc2的一端、晶体管Mc2的漏极以及晶体管Mc3的漏极相连，电阻Rc2的另一端与电容Cc1的一端以及Rc3的一端相接，电容Cc1的另一端和Mc1的漏极相接，Mc1的栅极和电阻Rc1的一端相接，晶体管Mc1的源极接地；电阻Rc1的另一端和控制端口Pc3相接，OUT端口与电阻Rc3的另一端、晶体管Mc2的源极以及晶体管Mc4的漏极相连，晶体管Mc2的栅极与电阻Rc4的一端相连，电阻Rc4的另一端与控制端Pc2相连，晶体管Mc3的栅极与电阻Rc5的一端相连，晶体管Mc4的栅极与电阻Rc6的一端相连，电阻Rc5的另一端与电阻Rc6的另一端相连并连接着控制端口Pc1，电阻Rc7的一端与晶体管Mc3的源极相连，电阻Rc7的另一端接地，电阻Rc8的一端与晶体管Mc4的源极相连，电阻Rc8的另一端接地。The π-type topology with compensation structure is composed of resistors Rc1, Rc2, Rc3, Rc4, Rc5, Rc6, Rc7, Rc8, capacitor Cc1, transistors Mc1, Mc2, Mc3, Mc4, and there are five ports that are IN , OUT, Pc1, Pc2, Pc3, wherein the RF signal input enters from the IN port and outputs from the OUT port, Pc1, Pc2, Pc3 are the control signal input ports of the transistor, the IN port and one end of the resistor Rc2, the drain of the transistor Mc2 And the drain of transistor Mc3 is connected, the other end of resistor Rc2 is connected to one end of capacitor Cc1 and one end of Rc3, the other end of capacitor Cc1 is connected to the drain of Mc1, the gate of Mc1 is connected to one end of resistor Rc1, The source of the transistor Mc1 is grounded; the other end of the resistor Rc1 is connected to the control port Pc3, the OUT port is connected to the other end of the resistor Rc3, the source of the transistor Mc2 and the drain of the transistor Mc4, and the gate of the transistor Mc2 is connected to the resistor Rc4. One end is connected, the other end of the resistor Rc4 is connected to the control terminal Pc2, the gate of the transistor Mc3 is connected to one end of the resistor Rc5, the gate of the transistor Mc4 is connected to one end of the resistor Rc6, and the other end of the resistor Rc5 is connected to the other end of the resistor Rc6 And connected to the control port Pc1, one end of the resistor Rc7 is connected to the source of the transistor Mc3, the other end of the resistor Rc7 is grounded, one end of the resistor Rc8 is connected to the source of the transistor Mc4, and the other end of the resistor Rc8 is grounded.
进一步地，所述的电路中的晶体管为N型金属-氧化物半导体场效应晶体管。Further, the transistors in the circuit are N-type metal-oxide semiconductor field effect transistors.
本发明的有益效果如下：The beneficial effects of the present invention are as follows:
本发明的超宽带幅相补偿数字开关衰减器电路通过电感匹配级联多个衰减单元，高衰减单元和低衰减单元交错排布可以有效提高衰减器的匹配性能，与现有的技术相比，附加相移小、衰减精度高、工作频带宽、输入输出匹配好。The ultra-wideband amplitude-phase compensation digital switching attenuator circuit of the present invention cascades multiple attenuation units through inductance matching, and the staggered arrangement of the high attenuation units and the low attenuation units can effectively improve the matching performance of the attenuator. Compared with the prior art, The additional phase shift is small, the attenuation precision is high, the operating frequency bandwidth is wide, and the input and output matching is good.
附图说明Description of drawings
图1为本发明的超宽带幅相补偿数字开关衰减器电路的整体结构框图。FIG. 1 is a block diagram of the overall structure of the ultra-wideband amplitude and phase compensation digital switch attenuator circuit of the present invention.
图2为本发明的超宽带幅相补偿数字开关衰减器中Bridge-T型衰减单元的电路拓扑结构图。2 is a circuit topology diagram of a Bridge-T type attenuation unit in an ultra-wideband amplitude-phase compensation digital switch attenuator of the present invention.
图3为本发明的超宽带幅相补偿数字开关衰减器中简化式T型衰减单元的电路拓扑结构图。3 is a circuit topology diagram of a simplified T-type attenuator unit in the ultra-wideband amplitude-phase compensation digital switch attenuator of the present invention.
图4为本发明的超宽带幅相补偿数字开关衰减器中π型衰减单元的电路拓扑结构图。4 is a circuit topology diagram of a π-type attenuation unit in the ultra-wideband amplitude-phase compensation digital switching attenuator of the present invention.
图5为本发明的超宽带幅相补偿数字开关衰减器集成电路具体实施图。FIG. 5 is a specific implementation diagram of the ultra-wideband amplitude and phase compensation digital switch attenuator integrated circuit of the present invention.
图6为本发明的超宽带幅相补偿数字开关衰减器的衰减仿真结果图。FIG. 6 is a graph showing the attenuation simulation result of the ultra-wideband amplitude-phase compensation digital switch attenuator of the present invention.
图7为本发明的超宽带幅相补偿数字开关衰减器的附加相移仿真结果图。FIG. 7 is a simulation result diagram of the additional phase shift of the ultra-wideband amplitude and phase compensation digital switch attenuator of the present invention.
具体实施方式Detailed ways
下面根据附图和优选实施例详细描述本发明，本发明的目的和效果将变得更加明白，以下结合附图和实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。The present invention will be described in detail below according to the accompanying drawings and preferred embodiments, and the purpose and effects of the present invention will become clearer. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.
如图1所示，本发明的超宽带幅相补偿数字开关衰减器电路由n个衰减单元通过电感匹配级联而成，n个衰减单元采用简化结构的T型电路、带补偿结构的bridge-T拓扑结构和带补偿结构的π型拓扑结构中的任意一种或多种。其中低衰减单元的结构益采用简化结构的T型电路，中低衰减单元益采用带补偿结构的bridge-T拓扑结构，高衰减单元益采用带补偿结构的π型拓扑结构。As shown in FIG. 1 , the ultra-wideband amplitude-phase compensation digital switching attenuator circuit of the present invention is formed by cascaded n attenuation units through inductance matching. Any one or more of T topology and π-type topology with compensation structure. Among them, the structure of the low-attenuation unit is preferably a T-type circuit with a simplified structure, the middle-low attenuation unit is a bridge-T topology with a compensation structure, and the high-attenuation unit is a π-type topology with a compensation structure.
下面针对一个具体的实施例，对该电路进行说明。The circuit will be described below with respect to a specific embodiment.
作为其中一个实施例，如图5所示，该电路由0.25dB、0.5dB、1dB、2dB、4dB、8dB衰减单元通过电感L1、L2、L3、L4、L5、L6匹配级联而成。其中0.25dB采用简化结构的T型电路，将此电路结构中的信号端口Pb2接入到信号通路并与电感L1相连。0.5dB、1dB、2dB、4dB采用带补偿结构的bridge-T拓扑结构，将此电路结构中的输入信号IN端和输入信号OUT端接入电路中并分别和电感相连。8dB采用带补偿结构的π型拓扑结构，将此电路结构中的输入信号IN端和输入信号OUT端接入电路中并分别和电感相连。衰减单元级联顺序为0.25dB、0.5dB、8dB、2dB、4dB、1dB。本发明的衰减器中高衰减单元和低衰减单元交错排布，可以有效提高衰减器的匹配性能。该衰减器的工作频率范围为dc～20GHz，以0.25dB为步进值，衰减范围在0dB～15.75dB实现64种衰减状态。As one example, as shown in FIG. 5 , the circuit is composed of 0.25dB, 0.5dB, 1dB, 2dB, 4dB, and 8dB attenuation units that are matched and cascaded through inductors L1, L2, L3, L4, L5, and L6. Among them, 0.25dB adopts a T-type circuit with a simplified structure, and the signal port Pb2 in this circuit structure is connected to the signal path and connected to the inductor L1. 0.5dB, 1dB, 2dB, 4dB adopt bridge-T topology structure with compensation structure, the input signal IN terminal and input signal OUT terminal in this circuit structure are connected to the circuit and connected to the inductor respectively. 8dB adopts the π-type topology structure with compensation structure, and the input signal IN terminal and the input signal OUT terminal in this circuit structure are connected to the circuit and connected to the inductor respectively. The cascade order of attenuation units is 0.25dB, 0.5dB, 8dB, 2dB, 4dB, 1dB. In the attenuator of the present invention, the high-attenuation units and the low-attenuation units are alternately arranged, which can effectively improve the matching performance of the attenuator. The working frequency range of the attenuator is dc～20GHz, with a step value of 0.25dB, and the attenuation range is 0dB～15.75dB to realize 64 attenuation states.
结合图2，0.5dB、1dB、2dB、4dB采用带补偿结构的bridge-T拓扑结构，该结构由电阻Ra1、Ra2、Ra3、Ra4、Ra5、Ra6、Ra7、Ra8，N型金属-氧化物半导体场效应晶体管Ma1、Ma2、Ma3，电容Ca1组成。有五个端口分别是IN、OUT、Pa1、Pa2、Pa3。其中射频信号输入从IN端口进入，从OUT端口输出。Pa1、Pa2、Pa3为晶体管的控制信号输入端口。IN端口与电阻Ra2、Ra5的一端、晶体管Ma2的漏端相接，电阻Ra2的另一端与电容Ca1的一端以及Ra3的一端相接，电容Ca1的另一端和Ma1的漏极相接，Ma1的栅极和电阻Ra1相接，晶体管Ma1的源极接地。电阻Ra1的另一端和控制端口Pa1相接，电阻Ra3另一端与Ra6的一端以及晶体管Ma2的源极都和OUT端口相接，晶体管Ma2通过电阻Ra4和控制端口Pa2相接。电阻Ra5的另一端、电阻Ra6的另一端、晶体管Ma3的漏极连接在一起，晶体管Ma3的栅极通过电阻Ra7和控制端口Pa3连接在一起。晶体管Ma3的源极通过电阻Ra8连接到地。所述的衰减器包括两种工作状态，一种是旁路状态，其中控制端Pa1和Pa3输入控制信号使得晶体管Ma1和Ma3处于关断状态，控制端Pa2输入控制信号使得晶体管Ma2处于导通状态。另一种状态为衰减状态，控制端Pa1和Pa3输入控制信号使得晶体管Ma1和Ma3处于导通状态，控制端Pa2输入控制信号使得晶体管Ma2处于关断状态。两种状态下，射频输出信号幅度相差0.5dB/1dB/2dB/4dB等固定值，输出信号相位几乎不变。Combined with Figure 2, 0.5dB, 1dB, 2dB, 4dB adopts bridge-T topology with compensation structure, which consists of resistors Ra1, Ra2, Ra3, Ra4, Ra5, Ra6, Ra7, Ra8, N-type metal-oxide semiconductor Field effect transistors Ma1, Ma2, Ma3, capacitor Ca1 composition. There are five ports are IN, OUT, Pa1, Pa2, Pa3. The RF signal input enters from the IN port and outputs from the OUT port. Pa1, Pa2, and Pa3 are the control signal input ports of the transistor. The IN port is connected to one end of the resistors Ra2 and Ra5 and the drain end of the transistor Ma2, the other end of the resistor Ra2 is connected to one end of the capacitor Ca1 and one end of Ra3, the other end of the capacitor Ca1 is connected to the drain of Ma1, and the other end of the capacitor Ca1 is connected to the drain of Ma1. The gate is connected to the resistor Ra1, and the source of the transistor Ma1 is grounded. The other end of the resistor Ra1 is connected to the control port Pa1, the other end of the resistor Ra3 is connected to one end of Ra6 and the source of the transistor Ma2 is connected to the OUT port, and the transistor Ma2 is connected to the control port Pa2 through the resistor Ra4. The other end of the resistor Ra5, the other end of the resistor Ra6, and the drain of the transistor Ma3 are connected together, and the gate of the transistor Ma3 is connected together through the resistor Ra7 and the control port Pa3. The source of the transistor Ma3 is connected to ground through a resistor Ra8. The attenuator includes two working states, one is a bypass state, wherein the control terminals Pa1 and Pa3 input control signals to make the transistors Ma1 and Ma3 be in an off state, and the control terminal Pa2 inputs a control signal to make the transistor Ma2 be in an on state. . The other state is the decay state, the control terminal Pa1 and Pa3 input control signals to make the transistors Ma1 and Ma3 in the on state, and the control terminal Pa2 inputs the control signal to make the transistor Ma2 in the off state. In the two states, the amplitude of the RF output signal differs by a fixed value such as 0.5dB/1dB/2dB/4dB, and the phase of the output signal is almost unchanged.
结合图3，0.25dB采用简化的T型电路，该结构由电阻Rb1、Rb2，以及N型金属-氧化物半导体场效应晶体管Mb1组成，有两个端口分别是Pb1和Pb2，其中端口Pb2接到射频信号通路上作为旁路，Pb1为控制信号输入，其连接电阻Rb1，Rb1的另一端连接晶体管Mb1的栅端，Mb1的漏极连接端口Pb2，Mb1的源极连接电阻Rb2，电阻Rb2的另一端和地相连。所述的衰减器包括两种工作状态，一种是旁路状态，此时，在端口Pb1输入控制信号使晶体管Mb1处于关断状态。另一种状态为衰减状态，控制端Pb1输入控制信号使晶体管Mb1处于导通状态。两种状态下，射频输出信号幅度相差0.25dB固定值，输出信号相位几乎不变。Combined with Figure 3, 0.25dB adopts a simplified T-type circuit. The structure consists of resistors Rb1, Rb2, and N-type metal-oxide semiconductor field effect transistor Mb1. There are two ports, Pb1 and Pb2, where port Pb2 is connected to As a bypass on the RF signal path, Pb1 is the control signal input, which is connected to resistor Rb1, the other end of Rb1 is connected to the gate terminal of transistor Mb1, the drain of Mb1 is connected to port Pb2, the source of Mb1 is connected to resistor Rb2, and the other end of resistor Rb2 is connected. One end is connected to ground. The attenuator includes two working states, one is the bypass state, at this time, the transistor Mb1 is turned off by inputting a control signal at the port Pb1. The other state is the attenuation state, and the control terminal Pb1 inputs a control signal to make the transistor Mb1 in the conducting state. In the two states, the amplitude of the RF output signal differs by a fixed value of 0.25dB, and the phase of the output signal is almost unchanged.
结合图4，8dB采用带补偿结构的π型拓扑结构，由电阻Rc1、Rc2、Rc3、Rc4、Rc5、Rc6、Rc7、Rc8，电容Cc1，N型金属-氧化物半导体场效应晶体管Mc1、Mc2、Mc3、Mc4组成。该结构有五个端口分别是IN、OUT、Pc1、Pc2、Pc3。其中射频信号输入从IN端口进入，从OUT端口输出。Pc1、Pc2、Pc3为晶体管的控制信号输入端口。IN端口与电阻Rc2的一端、晶体管Mc2的漏极以及晶体管Mc3的漏极相连，电阻Rc2的另一端与电容Cc1的一端以及Rc3的一端相接，电容Cc1的另一端和Mc1的漏极相接，Mc1的栅极和电阻Rc1的一端相接，晶体管Mc1的源极接地。电阻Rc1的另一端和控制端口Pc3相接，OUT端口与电阻Rc3的另一端、晶体管Mc2的源极以及晶体管Mc4的漏极相连，晶体管Mc2的栅极与电阻Rc4的一端相连，电阻Rc4的另一端与控制端Pc2相连，晶体管Mc3的栅极与电阻Rc5的一端相连，晶体管Mc4的栅极与电阻Rc6的一端相连，电阻Rc5的另一端与电阻Rc6的另一端相连并连接着控制端口Pc1，电阻Rc7的一端与晶体管Mc3的源极相连，电阻Rc7的另一端接地，电阻Rc8的一端与晶体管Mc4的源极相连，电阻Rc8的另一端接地。所述的衰减器包括两种工作状态，一种是旁路状态，其中控制端Pc1、Pc3输入控制信号使得晶体管Mc1、Mc3和Mc4处于关断状态，控制端Pc2输入控制信号使得晶体管Mc2处于导通状态。另一种状态为衰减状态，控制端Pc1和Pc3输入信号使得晶体管Mc1、Mc3和Mc4处于导通状态，控制端Pc2输入控制信号使得晶体管Mc2处于关断状态。两种状态下，射频输出信号幅度相差8dB固定值，输出信号相位几乎不变。Combined with Figure 4, 8dB adopts a π-type topology with a compensation structure, consisting of resistors Rc1, Rc2, Rc3, Rc4, Rc5, Rc6, Rc7, Rc8, capacitors Cc1, N-type metal-oxide semiconductor field effect transistors Mc1, Mc2, It is composed of Mc3 and Mc4. The structure has five ports, namely IN, OUT, Pc1, Pc2, and Pc3. The RF signal input enters from the IN port and outputs from the OUT port. Pc1, Pc2, and Pc3 are control signal input ports of the transistors. The IN port is connected to one end of resistor Rc2, the drain of transistor Mc2 and the drain of transistor Mc3, the other end of resistor Rc2 is connected to one end of capacitor Cc1 and one end of Rc3, the other end of capacitor Cc1 is connected to the drain of Mc1 , the gate of Mc1 is connected to one end of the resistor Rc1, and the source of the transistor Mc1 is grounded. The other end of the resistor Rc1 is connected to the control port Pc3, the OUT port is connected to the other end of the resistor Rc3, the source of the transistor Mc2 and the drain of the transistor Mc4, the gate of the transistor Mc2 is connected to one end of the resistor Rc4, and the other end of the resistor Rc4 is connected. One end is connected to the control terminal Pc2, the gate of the transistor Mc3 is connected to one end of the resistor Rc5, the gate of the transistor Mc4 is connected to one end of the resistor Rc6, the other end of the resistor Rc5 is connected to the other end of the resistor Rc6 and connected to the control port Pc1, One end of the resistor Rc7 is connected to the source of the transistor Mc3, the other end of the resistor Rc7 is grounded, one end of the resistor Rc8 is connected to the source of the transistor Mc4, and the other end of the resistor Rc8 is grounded. The attenuator includes two working states, one is a bypass state, wherein the control terminals Pc1 and Pc3 input control signals to make the transistors Mc1, Mc3 and Mc4 in an off state, and the control terminal Pc2 inputs a control signal to make the transistor Mc2 in conduction. pass status. The other state is the decay state. The control terminals Pc1 and Pc3 input signals to make the transistors Mc1, Mc3 and Mc4 in the on state, and the control terminal Pc2 inputs the control signal to turn off the transistor Mc2. In the two states, the amplitude of the RF output signal differs by a fixed value of 8dB, and the phase of the output signal is almost unchanged.
本发明的一种超宽带幅相补偿数字开关衰减器的衰减结果如图6所示，仿真结果表明，在dc-20GHz频率范围内，本发明的各个衰减状态的衰减精度较为理想。本发明的一种超宽带相位补偿数字开关衰减器的各衰减状态的附加相移仿真结果如图7所示，附加相移最大为-0.65°/+0.35°，使得该衰减器在使用时引入的相位影响很小。The attenuation result of an ultra-wideband amplitude-phase compensation digital switch attenuator of the present invention is shown in FIG. 6 . The simulation results show that in the frequency range of dc-20GHz, the attenuation accuracy of each attenuation state of the present invention is ideal. Figure 7 shows the additional phase shift simulation results of each attenuation state of an ultra-wideband phase-compensated digital switching attenuator of the present invention, the maximum additional phase shift is -0.65°/+0.35°, so that the attenuator introduces phase has little effect.
本领域普通技术人员可以理解，以上所述仅为发明的优选实例而已，并不用于限制发明，尽管参照前述实例对发明进行了详细的说明，对于本领域的技术人员来说，其依然可以对前述各实例记载的技术方案进行修改，或者对其中部分技术特征进行等同替换。凡在发明的精神和原则之内，所做的修改、等同替换等均应包含在发明的保护范围之内。Those of ordinary skill in the art can understand that the above are only preferred examples of the invention and are not intended to limit the invention. Although the invention has been described in detail with reference to the foregoing examples, those skilled in the art can still understand the Modifications are made to the technical solutions described in the foregoing examples, or equivalent replacements are made to some of the technical features. All modifications and equivalent replacements made within the spirit and principle of the invention shall be included within the protection scope of the invention.
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| CN113114162A (en) * | 2021-03-24 | 2021-07-13 | 中国电子科技集团公司第三十八研究所 | Attenuator circuit for CMOS broadband amplitude-phase multifunctional chip |
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