WO2023130765A1

WO2023130765A1 - Silicon-based time modulation phased array feed network unit and time modulation phased array system

Info

Publication number: WO2023130765A1
Application number: PCT/CN2022/119754
Authority: WO
Inventors: 黄同德; 曹瀚璋; 曹帅; 朱玺成; 吴文
Original assignee: 南京理工大学
Priority date: 2022-01-10
Filing date: 2022-09-20
Publication date: 2023-07-13
Also published as: CN114512811A

Abstract

Disclosed is a silicon-based time modulation phased array feed network unit, characterized in comprising a power division module, a time modulation module, an orthogonal synthesis module, and an amplifier module. In a signal transmission process, a transmitted signal enters the time modulation module by means of the power division module, or directly enters the time modulation module. After signal phase shifting is completed in the time modulation module, in-phase/orthogonal transformation and power synthesis are carried out on the phase-shifted signal by the orthogonal synthesis module, and the signal is then amplified by the amplifier module and outputted. In a signal reception process, after a radio-frequency signal has been amplified by the amplifier module, the radio-frequency signal is subjected to power division and in-phase/orthogonal transformation by the orthogonal synthesis module, and then enters the time modulation module to carry out signal phase shifting, and the phase-shifted signal is synthesized and outputted by the power division module or is directly outputted. The present invention is simple in structure, improves the phase shift precision of the system, and reduces the loss of the system.

Description

Silicon-based time-modulated phased array feed network unit and time-modulated phased array system

technical field

The invention relates to a microwave monolithic integrated circuit and microelectronic technology, in particular to a silicon-based time-modulated phased array feeding network unit and a time-modulated phased array system.

Background technique

With the rapid development of wireless communication systems, phased array systems are widely used in various fields, especially in aerospace, precision guidance, short-range detection and other fields. The radiation characteristics of the traditional phased array system are realized by controlling the amplitude and phase in the feed network, and the control accuracy of the phase depends on the design of a high-precision phase shifter. With the continuous improvement of the communication rate, the design of the phased array system has entered the millimeter wave frequency band, while in the microwave/millimeter wave frequency band, the design of the phase shifter is complicated and the phase shifting accuracy is not high. Therefore, the time-modulated phased array system has a very wide application prospect.

The time modulation phased array system is a design that introduces the time dimension into the traditional phased array antenna system. The switch is periodically turned on and off by an external control signal to achieve high-precision phase shifting; in addition, by designing the waveform of the time pulse modulation function And the introduction of quadrature modulation can suppress the aliasing of sideband signals, but the realization of the structure often depends on the introduction of multiple radio frequency switches in the path. Chinese patent application CN109037972 proposes a feed network based on dual time-modulated antenna complex weights, which needs to introduce two single-pole double-throw switches on a single signal path; Chinese patent application CN113675623A proposes a time-modulated phased array feed For network chips, one single-pole three-throw switch and two single-pole double-throw switches need to be introduced on a single channel. In the microwave/millimeter wave frequency band, the insertion loss of a typical SPDT switch is 2-3dB, which will increase the loss of the system and greatly reduce the gain and efficiency of the system. In addition, in the waveform design of the time pulse modulation function and the design of the power divider/combiner required by the quadrature modulation, the existing schemes are basically based on the design of the Wilkinson power divider. However, in the silicon-based integrated circuit In the design, the area of the Wilkinson power divider is huge, so it is not suitable for application in the integrated design.

Contents of the invention

The object of the present invention is to propose a silicon-based time-modulated phased array feed network unit and a time-modulated phased array system.

The technical solution to realize the object of the present invention is: a silicon-based time-modulated phased array feed network unit, including a power division module, a time modulation module, an orthogonal synthesis module, and an amplifier module. Sub-modules enter the time modulation module, or directly enter the time modulation module. After the signal phase shift is completed in the time modulation module, the quadrature synthesis module performs in-phase/orthogonal conversion and power synthesis on the phase-shifted signal, and then the amplifier module Carry out signal amplification and output; in the process of signal reception, after the RF signal is amplified by the amplifier module, the quadrature synthesis module performs power division and in-phase/orthogonal conversion, and then enters the time modulation module for signal phase shifting, and the phase-shifted signal undergoes power Sub-module synthesis output, or direct output;

The time modulation module is composed of multiple sets of switches and 0/π phase shifters, by changing the state of the switches to control the access of the power division module, the switch behind the 0/π phase shifter directly connected to the power division module is turned on, When the switch behind the 0/π phase shifter not connected to the hybrid power divider is turned off, the power dividing module is connected to the link, and the signal enters the link through the power dividing module and the 0/π phase shifter directly connected to it or Output from the link; when the switch after the 0/π phase shifter directly connected to the power dividing module is turned off, and the switch after the 0/π phase shifter not connected to the hybrid power divider is turned on, the power dividing module is not connected Link, the signal enters the link or outputs from the link through the 0/π phase shifter not connected to the power dividing module.

Further, the power dividing module is composed of a hybrid power divider based on a transformer, the center tap of the primary coil of the transformer is connected to the center tap of the secondary coil, and is grounded through a capacitor; the two ports of the secondary coil are connected to the in-phase channel of the time modulation module And the quadrature channel, and a resistor is connected in series between the two ports, which is used to isolate the ports.

Further, the time modulation module is composed of first to eighth switches and four sets of 0/π phase shifters with a phase difference of 180°, wherein:

The first switch and the second switch are respectively located at the π phase shift branch and the 0 phase shift branch of the first phase shifter, and the third switch and the fourth switch are respectively located at the π phase shift branch and the 0 phase shift branch of the second phase shifter. In the phase branch, the fifth switch and the sixth switch are respectively located in the π phase shift branch and the 0 phase shift branch of the third phase shifter, and the seventh switch and the eighth switch are respectively located in the π phase shift branch of the fourth phase shifter Road and 0 phase shift branch;

One end of the first phase shifter and the fourth phase shifter are directly connected to the output port of the received signal or the input port of the transmitted signal, one end of the second phase shifter and the third phase shifter are connected to the power division module, and the first phase shifter and the second phase shifter are connected to each other. The other end of the second phase shifter is connected to the in-phase channel of the quadrature synthesis module through a switch, and the other ends of the third phase shifter and the fourth phase shifter are connected to the quadrature channel of the quadrature synthesis module through a switch.

Further, the first to eighth switches use deep N-well NMOS transistors.

Further, the control logic of the first to eighth switches is:

The first switch in a relative period T _p of the first

open to

The rest of the time is in the off state; the second switch is in the first relative period T _p

open to

The rest of the time is in the off state; the third switch is in the first relative period T _p

open to

No.

open to

The rest of the time is in the off state; the fourth switch is in the first relative period T _p

open to

No.

open to

The rest of the time is in the off state; the first switch is in the first phase of a relative period T _p

open to

No.

open to

The rest of the time is in the off state; the sixth switch is in the first relative period T _p

open to

No.

open to

The rest of the time is in the off state; the seventh switch is in the first relative period T _p

open to

The rest of the time is in the off state; the eighth switch is in the first phase of a relative period T _p

open to

The rest of the time is in the off state; T _p is the period of the time-modulated pulse waveform.

Further, the timing of the time modulation pulses of the time modulation module satisfies the following relationship:

In the above formula, τ' and τ" are the conduction time in the conduction state and the single-channel state respectively,

and

Respectively represent the start time of the two-way state on the same phase path,

and

Respectively represent the starting time of the two-way state on the normal traffic road,

and

Respectively represent the start time of the single-channel state on the same-phase channel,

and

Respectively denote the start time of the one-way state on the orthogonal road.

Further, the phase shift function of the time modulation module adjusts the starting time point of the pulse

To achieve this, if the pointing angle of the beam is θ ₀ , the relationship between it and the pulse start time point is:

Continuously adjust the start time of the pulse, that is, realize the continuous phase change of the time modulation module in the range of 0-2π.

Further, the quadrature synthesis module is composed of a transformer-based quadrature synthesis network, port 1 of the primary coil is a synthesis port, port 2 is a through port, port 3 of the secondary coil is a coupling port, the other end is grounded, and port 2 is a through port. Port 3 and port 3 are respectively grounded through the first parallel capacitor and the second parallel capacitor to realize a 90° phase difference between port 2 and port 3 to form an in-phase/orthogonal path to complete quadrature time modulation.

Further, the amplifier module is composed of a power amplifier, a low-noise amplifier and a single-pole double-throw switch, wherein the power amplifier is used to amplify the transmitted signal; the low-noise amplifier is used to amplify the signal received by the antenna; the single-pole double-throw switch is used It is used to select a power amplifier or a low noise amplifier to work according to the scene of signal transmission or reception.

A time-modulated phased array system, including N said time-modulated phased array feeding network units, and a 1-N power divider, FPGA control circuit or silicon-based logic circuit, N antenna array elements, and integrated Among the monolithic silicon-based chips, among them:

N time-modulated phased array feed network units are used to feed antenna array elements to realize signal transmission and reception, as well as phase shifting functions; 1-N power dividers are used to distribute power to N feed network units /Synthesis; FPGA control circuit or silicon-based logic circuit sends periodic on-off signals to change the working state of the switch in the chip to realize phase weighting of time-modulated phased array system; N antenna array elements are used for RF signal to receive or transmit.

Compared with the prior art, the present invention has significant advantages as follows: 1) The structure of the time-modulated phased array feed network is simplified, so that the number of switches on each signal path is reduced to one, thus reducing the insertion of switches The impact of loss on the efficiency and gain of the system; 2) The introduction of a transformer-based hybrid power divider and a transformer-based orthogonal synthesis network greatly reduces the area of the power division module and orthogonal synthesis module, saving layout area, It is beneficial to the integrated design; 3) the chip with integrated design can greatly reduce the volume of the time modulation radio frequency system, and greatly improve the integration degree of the system.

Description of drawings

Fig. 1 is the topological structure diagram of silicon-based time modulation phased array feed network unit of the present invention;

Fig. 2 is the equivalent circuit diagram and layout of the hybrid power divider of the present invention;

Fig. 3 is a structural schematic diagram of a silicon-based switch of the present invention;

Fig. 4 is the equivalent circuit diagram and layout of the orthogonal synthesis network of the present invention;

Fig. 5 is the control logic diagram of switch control signal of the present invention;

Fig. 6 is the time-modulated pulse waveform diagram of the present invention, wherein (a) is the time-modulated pulse waveform diagram of the in-phase channel; (b) is the time-modulated pulse waveform diagram of the quadrature channel; (c) is the time-modulated pulse waveform diagram of the total circuit.

Fig. 7 is a topological structure diagram of the time modulation phased array system of the present invention;

FIG. 8 is a normalized spectrum distribution diagram of the output signal of the time-modulated phased array system of the present invention.

Detailed ways

In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, not to limit the present application.

Figure 1 is the silicon-based time-modulated phased array feed network chip topology. The silicon-based time modulation phased array feed network unit includes a power division module 101, a time modulation module 102, a quadrature synthesis module 103, and an amplifier module 104 from left to right. The power division module 101 is used to realize the reconfigurable power division function with the time modulation module 102; the time modulation module 102 is used to apply the pulse modulation function to realize the waveform of low sideband level and realize high-precision phase shifting at the same time; quadrature synthesis Module 103 is used to form an in-phase/orthogonal path to realize quadrature time modulation; the amplifier module 104 is composed of a power amplifier and a low-noise amplifier, and is used to amplify the transmitted or received radio frequency signal, so that the system can compare the transmitted signal with the The power requirements of the received signal; all modules are integrated in a single silicon-based time-modulated phased array feed network chip, and each module is well matched.

During the signal transmission process, the transmitted signal enters the time modulation module through the power division module, or directly enters the time modulation module. After the signal phase shift is completed in the 0/π phase shifter, the phase-shifted signal is synchronized by the quadrature synthesis module. /orthogonal conversion and power synthesis, and then the amplifier module performs signal amplification and output; in the process of signal reception, after the radio frequency signal is amplified by the amplifier module, the quadrature synthesis module performs power division and in-phase/orthogonal conversion, and then enters the time modulation module , the signal is phase-shifted by a 0/π phase shifter, and the phase-shifted signal is synthesized and output by a power division module, or output directly. Please refer to 101, which is a power dividing module, and its basic structure is a transformer-based hybrid power divider. Referring to 102, it is a time modulation module, which is composed of switches SW1-SW8, and four sets of 0/π phase shifters PS1-PS4 with a phase difference of 180°. Among them, SW1 and SW2 are respectively located in the π phase shift branch and 0 phase shift branch in PS1, SW3 and SW4 are respectively located in the π phase shift branch and 0 phase shift branch in PS2, and SW5 and SW6 are respectively located in π phase shift branch in PS3 The phase shift branch and the 0 phase shift branch, SW7 and SW8 are respectively located in the π phase shift branch and the 0 phase shift branch of PS4; the two switches corresponding to each group of phase shifters will not be turned on at the same time. When the switch SW1 or SW2 is turned on and the other switches are turned off, the power dividing module is not connected to the link, and the signal is not divided by power, and directly enters the time modulation module; when the switch SW7 or SW8 is turned on and the other switches are turned off, The power dividing module is not connected to the link, the signal is not divided by power, and directly enters the time modulation module; when the switch SW3 or SW4 or SW5 or SW6 is turned on, and the switches SW1, SW2, SW7, SW8 are turned off, the power dividing module is connected In the link; one end of the first phase shifter and the fourth phase shifter PS1, PS4 is directly connected to the output port of the received signal or the input port of the transmitted signal, and one end of the second phase shifter and the third phase shifter PS2, PS3 is connected to the power Sub-module, the other ends of the first phase shifter and the second phase shifter PS1, PS2 are connected to the in-phase channel of the quadrature synthesis module through a switch, and the other ends of the third phase shifter and the fourth phase shifter PS3, PS4 are connected to the positive channel through a switch. Orthogonal channels for intersection synthesis modules.

See 103, which is the quadrature synthesis module, whose basic structure is a transformer-based quadrature synthesis network; the transformer-based quadrature synthesis network can realize a low-loss, wide-bandwidth quadrature generation network on the premise of only occupying one transformer layout area . See 104, which is an amplifier module, which is composed of a power amplifier PA, a low-noise amplifier LNA, and a single-pole double-throw switch SW9; wherein the function of the power amplifier PA is to amplify the transmitted signal; the function of the low-noise amplifier LNA is to amplify the signal received by the antenna ; The function of the switch SW9 is to select the power amplifier or the low noise amplifier to work according to the scene of signal transmission or reception.

Figure 2 is the equivalent circuit diagram and layout of the hybrid power divider. The center tap of the primary coil T1 of the transformer TF1 is connected to the center tap of the secondary coil T2, and is grounded through the capacitor C1; one end of T1 is connected to the chip transmitting link input signal/receiving link output signal, and the other end is grounded; the middle series impedance of both ends of T2 is 2 The resistance of ×Z0, Z0 is the characteristic impedance of the circuit, which is used to isolate the 2/3 ports; the two ends of T2 are respectively connected to the time modulation module part of the synchronous channel I and the quadrature channel Q.

Figure 3 is a silicon-based switch structure. The switch is designed with a deep N-well (DNW) NMOS transistor. The deep N-well structure tube isolates the P-well body to reduce capacitive coupling and signal leakage. At the same time, DNW is connected to a high level to form A pair of reversely connected PN junctions, thus shielding the phase delay caused by noise interference and parasitic effects caused by common substrate coupling, so that the switch has good isolation; the body terminal is connected to R _sub , and the value of R _sub is 10kΩ Resistor, which isolates the source and drain from the substrate parasitic capacitance, thereby reducing the leakage of the signal to the ground, and reducing the swing of the signal on the parasitic capacitance and inductance, thereby reducing the insertion loss and improving the linearity ; An external control signal is applied to the gate of the DNWNMOS. When the control signal V _ctrl is greater than the transistor turn-on voltage V _th , the switch is turned on; when the control signal V _ctrl is lower than the transistor turn-on voltage V _th , the switch is turned off.

Figure 4 is the equivalent circuit diagram and layout of the orthogonal synthesis network. Port 1 on the primary coil is the synthesis port, port 2 is the through port; one end of the secondary coil is port 3, which is the coupling port, and the other end is grounded. Port 2 and port 3 are respectively connected in parallel with a capacitor to ground to realize a phase difference of 90° between port 2 and port 3 to form an in-phase/orthogonal path to realize an orthogonal time-modulated phased array system.

Figure 5 shows the control logic of the switch control signal. When the normalized level is 1, the switch is turned on; when the normalized level is 0, the switch is turned off;

The control logic of the switch is as follows: the switch SW1 in a relative period T _p

open to

The rest of the time is in the off state; the switch SW2 is in a relative period T _p of the first

open to

The rest of the time is in the off state; the switch SW3 is in the first relative period T _p

open to

No.

open to

The rest of the time is in the off state; SW4 is in a relative period T _p of the first

open to

No.

open to

The rest of the time is in the off state; SW5 is in the first relative period T _p

open to

No.

open to

The rest of the time is in the off state; SW6 is in a relative period T _p of the first

open to

No.

open to

The rest of the time is in the off state; the switch SW7 is in a relative period T _p of the first

open to

The rest of the time is in the off state; the switch SW8 is in the first relative period T _p

open to

The rest of the time is in the off state; T _p is the period of the time-modulated pulse waveform. The control logic of its complete control signal is shown in Figure 6. By applying the periodic pulse signal shown in Figure 6 to the switch, the time-modulated pulse waveform shown in Figure 6 can be realized;

Fig. 6 is the time-modulated pulse waveform, (a) is the time-modulated pulse waveform on the in-phase channel; (b) is the time-modulated pulse waveform on the quadrature channel; (c) is the time-modulated pulse waveform on the total circuit; where the pulse The modulation waveform is generated by the periodic switch control signal generated by the FPGA control circuit, which is applied to the switch in the time-modulated feed network unit through the drive circuit; please refer to Figure 7, the timing of the pulse modulation function shown in the figure satisfies the following relationship Mode:

and

Respectively represent the initial moment of the single-way state on the orthogonal road, and T _p is the period of the time-modulated pulse waveform.

When the above formula is satisfied, the time-modulated radio frequency system in this embodiment can output a +1 order sideband signal, and the alias-free signal bandwidth is 8f _p . Where, f _p is the frequency of the time-modulated pulse waveform.

By adjusting the start time point of the pulse

The free phase change of the time modulation circuit in 0-2π can be realized. If the pointing angle of the beam is θ ₀ , the time point of the pulse start is:

Figure 7 is the topology of the time-modulated phased array system. In this example, the time-modulated phased array system consists of 4 time-modulated phased array feed network units, 1-4 power dividers, FPGA control circuit or silicon-based logic circuit, and 4 antenna array elements, which are integrated in a single chip Among silicon chips;

4 time-modulated phased array feed network units 801 are used to feed the antenna elements so that the system can realize signal transmission and reception, as well as the function of phase shifting; 1-4 power divider 802 is used to feed the 4 feeders The electrical network unit performs power distribution/synthesis; the FPGA control circuit or the silicon-based logic circuit 803 sends out periodic on-off signals to periodically change the working status of the switches in the chip, so as to realize the phase weighting of the time-modulated phased array system; N Antenna elements 804 are used to receive or transmit radio frequency signals;

Fig. 8 is an example diagram of the normalized distribution of the frequency spectrum of the output signal of the time-modulated radio frequency system. It can be seen that the maximum unwanted sideband of the output signal spectrum of the time-modulated radio frequency system is the +7th order sideband, and the maximum unwanted sideband level is lower than -16.5dB.

The technical features of the above embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be It is considered to be within the range described in this specification.

The above-mentioned embodiments only represent several implementation modes of the present application, and the description thereof is relatively specific and detailed, but it should not be construed as limiting the scope of the patent for the invention. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the scope of protection of the patent application should be based on the appended claims.

Claims

A silicon-based time-modulated phased array feed network unit, characterized in that it includes a power division module, a time modulation module, an orthogonal synthesis module, and an amplifier module. During signal transmission, the transmitted signal enters the time modulation module through the power division module , or directly enter the time modulation module. After the signal phase shift is completed in the time modulation module, the quadrature synthesis module performs in-phase/orthogonal conversion and power synthesis on the phase-shifted signal, and then the signal is amplified and output by the amplifier module; During the receiving process, after the RF signal is amplified by the amplifier module, the quadrature synthesis module performs power division and in-phase/orthogonal conversion, and then enters the time modulation module for signal phase shifting, and the phase-shifted signal is synthesized and output by the power division module, or direct output;

The time modulation module is composed of multiple sets of switches and 0/π phase shifters, by changing the state of the switches to control the access of the power division module, the switch behind the 0/π phase shifter directly connected to the power division module is turned on, When the switch behind the 0/π phase shifter not connected to the hybrid power divider is turned off, the power dividing module is connected to the link, and the signal enters the link through the power dividing module and the 0/π phase shifter directly connected to it or Output from the link; when the switch after the 0/π phase shifter directly connected to the power dividing module is turned off, and the switch after the 0/π phase shifter not connected to the hybrid power divider is turned on, the power dividing module is not connected Link, the signal enters the link or outputs from the link through the 0/π phase shifter not connected to the power dividing module.
The silicon-based time-modulated phased-array feed network unit according to claim 1, wherein the power dividing module is composed of a hybrid power divider based on a transformer, and the center tap of the primary coil of the transformer and the center tap of the secondary coil Connected, and grounded through a capacitor (C1); the two ports of the secondary coil are connected to the in-phase channel and quadrature channel of the time modulation module, and a resistor is connected in series between the two ports to isolate the ports.
The silicon-based time modulation phased array feed network unit according to claim 1, wherein the time modulation module consists of the first to eighth switches (SW1-SW8) and four groups of 0 with a phase difference of 180°. /π phase shifter (PS1-PS4) constitutes, wherein:

The first switch and the second switch (SW1, SW2) are respectively located in the π phase shift branch and the 0 phase shift branch of the first phase shifter (PS1), and the third switch and the fourth switch (SW3, SW4) are respectively located in the first phase shifter (PS1). The π phase-shifting branch of the second phase shifter (PS2) and the 0 phase-shifting branch, the fifth switch and the sixth switch (SW5, SW6) are respectively located at the π-phase shifting branch of the third phase shifter (PS3) and 0 In the phase shifting branch, the seventh switch and the eighth switch (SW7, SW8) are respectively located in the π phase shifting branch and the 0 phase shifting branch of the fourth phase shifter (PS4);

One end of the first phase shifter and the fourth phase shifter (PS1, PS4) is directly connected to the output port of the received signal or the input port of the transmitted signal, and one end of the second phase shifter and the third phase shifter (PS2, PS3) is connected to the power Sub-module, the other end of the first phase shifter and the second phase shifter (PS1, PS2) are connected to the same phase channel of the quadrature synthesis module through a switch, and the other end of the third phase shifter and the fourth phase shifter (PS3, PS4) Connect the quadrature channel of the quadrature synthesis module through a switch.
The silicon-based time-modulated phased array feeding network unit according to claim 3, characterized in that the first to eighth switches (SW1-SW8) use deep N-well NMOS transistors.
The silicon-based time-modulated phased array feed network unit according to claim 3, wherein the control logic of the first to eighth switches (SW1-SW8) is:

The first switch (SW1) at the first switch of a relative period T p
open to
The rest of the time is in the off state; the second switch (SW2) is in a relative period T p of the first
open to
The rest of the time is in the off state; the third switch (SW3) is in the first relative period T p
open to
No.
open to
The rest of the time is in the off state; the fourth switch (SW4) is in the first relative period T p
open to
No.
open to
The rest of the time is in the off state; the first switch (SW5) is in the first relative period T p
open to
No.
open to
The rest of the time is in the off state; the sixth switch (SW6) is in the first relative period T p
open to
No.
open to
The rest of the time is in the off state; the seventh switch (SW7) is in the first phase of a relative period T p
open to
The rest of the time is in the off state; the eighth switch (SW8) is in the first phase of a relative period T p
open to
The rest of the time is in the off state; T p is the period of the time-modulated pulse waveform.
The silicon-based time-modulated phased array feed network unit according to claim 3, wherein the time-modulated pulse sequence of the time-modulated module satisfies the following relational expression:

In the above formula, τ' and τ" are the conduction time in the conduction state and the single-channel state respectively,
and
Respectively represent the start time of the two-way state on the same phase path,
and
Respectively represent the starting time of the two-way state on the normal traffic road,
and
Respectively represent the start time of the single-channel state on the same-phase channel,
and
Respectively denote the start time of the one-way state on the orthogonal road.
The silicon-based time modulation phased array feed network unit according to claim 6, wherein the phase shift function of the time modulation module adjusts the starting time point of the pulse
To achieve this, if the pointing angle of the beam is θ 0 , the relationship between it and the pulse start time point is:
Continuously adjust the start time of the pulse, that is, realize the continuous phase change of the time modulation module in the range of 0-2π.
The silicon-based time-modulated phased array feed network unit according to claim 1, wherein the quadrature synthesis module is composed of a transformer-based quadrature synthesis network, the port 1 of the primary coil is a synthesis port, and the port 2 It is a through port, the port 3 of the secondary coil is a coupling port, and the other end is grounded, and the port 2 and port 3 are respectively grounded through the first parallel capacitor and the second parallel capacitor (C2, C3) to realize the connection between port 2 and port 3. 90° phase difference to form an in-phase/orthogonal path to complete quadrature time modulation.
The silicon-based time-modulated phased array feeding network unit according to claim 1, wherein the amplifier module is composed of a power amplifier (PA), a low-noise amplifier (LNA) and a single-pole double-throw switch (SW9), Among them, the power amplifier (PA) is used to amplify the transmitted signal; the low-noise amplifier (LNA) is used to amplify the signal received by the antenna; the single-pole double-throw switch (SW9) is used to select the power amplifier or The low noise amplifier works.
A time-modulated phased array system, characterized in that it comprises N time-modulated phased array feed network units according to any one of claims 1-9, and 1-N power dividers, FPGA control circuits or silicon Basic logic circuit, N antenna array elements, and integrated in a single silicon chip, where:

N time-modulated phased array feed network units are used to feed antenna array elements to realize signal transmission and reception, as well as phase shifting functions; 1-N power dividers are used to distribute power to N feed network units /Synthesis; FPGA control circuit or silicon-based logic circuit sends periodic on-off signals to change the working state of the switch in the chip to realize phase weighting of time-modulated phased array system; N antenna array elements are used for RF signal to receive or transmit.