CN113745364A - 光电二极管和/或pin二极管结构 - Google Patents

光电二极管和/或pin二极管结构 Download PDF

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CN113745364A
CN113745364A CN202110564834.5A CN202110564834A CN113745364A CN 113745364 A CN113745364 A CN 113745364A CN 202110564834 A CN202110564834 A CN 202110564834A CN 113745364 A CN113745364 A CN 113745364A
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semiconductor material
fin
trench
photosensitive
substrate
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CN113745364B (zh
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S·P·埃杜苏米利
J·J·埃利斯-莫纳甘
M·D·莱维
V·贾因
A·斯特姆
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GlobalFoundries US Inc
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Abstract

本公开涉及半导体结构，更具体地涉及光电二极管和/或PIN二极管结构及制造方法。该结构包括：至少一个鳍，其包括衬底材料，至少一个鳍包括侧壁和顶面；沟槽，其位于至少一个鳍的相反两侧；第一半导体材料，其给至少一个鳍的侧壁和顶面以及沟槽的底面加衬里；光敏半导体材料，其位于第一半导体材料上并且至少部分地填充沟槽；以及第三半导体材料，其位于光敏半导体材料上。

Description

光电二极管和/或PIN二极管结构
技术领域
本公开涉及半导体结构，更具体地涉及光电二极管和/或PIN二极管结构及制造方法。
背景技术
雪崩光电二极管(APD)是一种高度敏感的半导体光电二极管，它利用光电效应将光转换为电。从功能的角度来看，雪崩光电二极管可以被视为光电倍增管的半导体模拟。雪崩光电二极管的典型应用是长距离光纤远程通信以及用于控制算法的量子感测。较新的应用包括正电子发射断层扫描和粒子物理学。
雪崩光电二极管的适用性和有效性取决于许多参数。例如，其中两个因素是量子效率和总泄漏。量子效率指示入射光子以多高的程度被吸收然后被用于产生初级载流子；而总泄漏电流是暗电流、光电流和噪声的总和。
光电二极管的灵敏度取决于通过光敏材料的光的路径长度以及所生成的载流子对到达电极/接触部/阴极的能力。在常规结构中，载流子沿二维路径(例如，垂直地或横向地)行进，这导致路径较长。由于常规雪崩光电二极管的路径较长，因此光敏材料内的光子复合频率很高，导致信号丢失或信号本身减弱。此外，光敏材料本身需要非常厚，这使得生长成本高且耗时长，并且可能使得与其他电路元件的集成更具挑战性。
发明内容
在本公开的一方面，一种结构包括：至少一个鳍(fin)，其包括衬底材料，所述至少一个鳍包括侧壁和顶面；沟槽，其位于所述至少一个鳍的相反两侧；第一半导体材料，其给所述至少一个鳍的所述侧壁和所述顶面以及所述沟槽的底面加衬里(line)；光敏半导体材料，其位于所述第一半导体材料上并且至少部分地填充所述沟槽；以及第三半导体材料，其位于所述光敏半导体材料上。
在本公开的一方面，一种结构包括：单晶半导体材料的至少一个鳍；至少一个沟槽，其位于所述至少一个鳍的相反两侧，所述沟槽具有所述单晶半导体材料的底面；具有第一掺杂剂类型的半导体材料，其给所述至少一个鳍的侧壁和顶面以及所述至少一个沟槽的所述底面加衬里；光敏半导体材料，其位于所述半导体材料的上方并且部分地填充所述至少一个沟槽；以及具有所述第一掺杂剂类型的第二半导体材料，其填充所述至少一个沟槽的剩余部分，并且与所述至少一个鳍上方的所述光敏半导体材料接触。
在本公开的一方面，一种方法包括：形成包括衬底材料的至少一个鳍；在所述至少一个鳍的相反两侧形成沟槽；形成第一半导体材料，所述第一半导体材料给所述至少一个鳍以及所述沟槽的底面加衬里；在所述第一半导体材料上形成光敏半导体材料，所述光敏半导体材料至少部分地填充所述沟槽；以及在所述光敏半导体材料上形成第三半导体材料。
附图说明
在下面的详细描述中，借助本公开的示例性实施例的非限制性示例，参考所提到的多个附图来描述本公开。
图1示出了根据本公开的方面的除其他特征之外的具有沟槽的衬底以及相应的制造工艺。
图2示出了根据本公开的方面的除其他特征之外的由衬底形成的一个或多个鳍以及相应的制造工艺。
图3A示出了根据本公开的方面的除其他特征之外的填充鳍之间的空间的光电二极管材料以及相应的制造工艺的截面图。
图3B至图3D示出了根据本公开的方面的除其他特征之外的具有光电二极管材料的鳍的不同构造以及相应的制造工艺的俯视图。
图4示出了根据本公开的另外的方面的光电二极管。
图5示出了根据本公开的方面的除其他特征之外的到光电二极管的接触形成以及相应的制造工艺。
图6示出了根据本公开的另外的方面的光电二极管。
图7示出了根据本公开的进一步另外的方面的光电二极管。
图8示出了根据本公开的方面的在单个芯片上与CMOS结构集成的光电二极管。
图9示出了根据本公开的方面的PIN二极管。
具体实施方式
本公开涉及半导体结构，更具体地涉及光电二极管和/或PIN二极管结构及制造方法。更具体地，本公开涉及具有(由鳍构成的)多个垂直和水平表面的光电二极管和/或pin二极管结构。有利地，本公开通过提供增大的半导体籽晶表面积来缩短光电二极管材料(例如Ge)的生长时间，同时还允许吸收光所需的更薄的光电二极管材料(例如Ge)区域。另外，本文描述的结构提供了从载流子生成部位到收集部位的较短路径，从而提高了光电二极管的效率。
在实施例中，本公开包括由形成在衬底材料的鳍上的光电探测器材料(例如Ge)构成的光电二极管。鳍可以形成为同心嵌套形状(例如，圆形、矩形、正方形、八边形等)或螺旋形状以及其他形状的俘获区域。如本文将要描述的，鳍的较大表面积有助于光电探测器材料(例如Ge)的生长。另外，Ge探测器区域内的Si鳍将通过增大表面俘获区域来提供提高的效率。例如，与同心嵌套形状(例如，圆形、矩形、正方形、八边形等)相比，螺旋形状俘获区域可以具有更大的表面积。因此，与同心圆构造相比，螺旋形光电二极管可通过增大表面积来提供提高的效率。
本公开的结构可以使用多种不同的工具，以多种方式来制造。然而，一般地，方法和工具被用来形成具有微米和纳米级尺寸的结构。已经根据集成电路(IC)技术采用了用于制造本公开的结构的方法(即，技术)。例如，这些结构建立在晶片上，并在借助晶片顶部上的光刻工艺而图案化的材料膜中实现。具体地，结构的制造使用三个基本构造块：(i)在衬底上沉积材料薄膜；(ii)通过光刻成像在膜顶部上施加图案化掩模；以及(iii)对掩模有选择性地蚀刻膜。
图1示出了根据本公开的方面的除其他特征之外的衬底以及相应的制造工艺。更具体地，结构10包括衬底12。衬底12可以代表例如CMOS芯片。在实施例中，衬底12优选地是单晶Si材料；但本文构想了其他半导体材料。例如，衬底12可以由包括SiC、GaAs、InAs、InP和其他III/V或II/VI族化合物半导体的任何合适的材料组成。在优选的实施例中，衬底12是由单一半导体材料(例如体硅)构成的N型衬底。
一个或多个沟槽14使用本领域技术人员公知的常规光刻和蚀刻工艺在衬底12中形成。在一个非限制性示例中，沟槽14可具有约2.5μm的深度(尽管本文构想了其他尺寸)。在实施例中，沟槽14可以是以螺旋模式形成的单个沟槽，或者以同心圆或其他嵌套形状(例如，同心嵌套的圆形、矩形、正方形、八边形等)形成的多个沟槽。例如，如图6所示，沟槽14可以是可选的。
在形成一个或多个沟槽14时，形成在衬底12上方的抗蚀剂被暴露于能量(光)下以形成图案(开口)。将使用具有选择性化学作用的蚀刻工艺(例如反应离子蚀刻(RIE))在衬底12中形成一个或多个沟槽14。在蚀刻工艺之后，可以执行HF清洁以从沟槽14的表面去除污染物，从而确保沟槽14的底面和侧壁的暴露半导体材料的清洁表面。可通过常规的氧灰化工艺或其他已知的剥离剂去除抗蚀剂。
仍参考图1，在衬底12上沉积硬掩模16。在实施例中，硬掩模16可以是氮化物或本领域中公知的其他硬掩模材料，因此无需进一步解释便可完全理解本公开。可通过已知的沉积方法(例如，化学气相沉积(CVD)工艺)来沉积硬掩模16。在实施例中，硬掩模16被图案化以暴露沟槽14和衬底12的围绕沟槽的部分。以此方式，硬掩模16将防止半导体材料在后续工艺中在衬底12的部分上发生外延生长。
在图2中，在衬底12中形成一个或多个鳍18。在实施例中，鳍18也可以是衬底材料和电介质材料(例如氧化物)的组合。在后一实施方式中，在形成鳍18之前，可以在衬底的顶面上沉积可选的电介质材料，如参考标号15所表示的。
在实施例中，除其他形状之外，多个鳍18可以形成为多个同心形状(例如，同心嵌套的圆形、矩形、正方形、八边形等)，或者单个鳍可在螺旋形状俘获区域中形成。鳍18与沟槽14对准，使得每个鳍18沿其中线(例如长度)与沟槽14相关联。在实施例中，每个鳍18的沟槽14将用作隔离特征，其可用于隔离光电二极管单元内的光。
鳍18可通过包括侧壁成像技术(SIT)的常规蚀刻工艺形成。在SIT技术中，例如，使用常规的沉积、光刻和蚀刻工艺在暴露的衬底12上形成芯轴(mandrel)。例如，使用常规CVD工艺将芯轴材料(例如SiO2)沉积在衬底12上。抗蚀剂形成在芯轴材料上，并暴露于光下以形成图案(开口)。通过开口执行反应离子蚀刻以形成芯轴。在实施例中，取决于窄鳍结构18之间的期望尺寸，芯轴可具有不同的宽度和/或间隔。在芯轴的侧壁上形成间隔物(spacer)，间隔物优选地具有不同于芯轴的材料，并且使用本领域技术人员公知的常规沉积工艺来形成。间隔物的宽度例如可以与鳍结构18的尺寸匹配。使用常规的蚀刻工艺对芯轴材料选择性地去除或剥离芯轴。然后在间隔物的间隔内执行蚀刻以形成亚光刻特征，例如其间具有空间或沟槽19的鳍18。在实施例中，沟槽19可以是任何形状，包括但不限于条形、正方形或椭圆形。然后可以剥离侧壁间隔物。
图3A示出了鳍18之间的沟槽19的侧视截面图，沟槽19被填充有光电二极管材料，例如具有可选衬里(liner)20的基于Ge的材料22。如图3A代表性地示出的，衬里20生长在衬底12的暴露表面上，例如鳍18的侧壁和顶面上。本领域普通技术人员应当理解，硬掩模16将防止半导体材料在鳍18外部且邻接沟槽19的衬底12的表面上生长。在实施例中，衬里20可以是外延生长的半导体材料，例如P型半导体材料，优选地由与衬底12相同的材料(例如Si)构成。
如图3A进一步示出的，在半导体材料20上选择性地生长附加的半导体材料22。在实施例中，半导体材料22是在衬里20上(例如在衬底12和鳍18的表面上方)外延生长的本征光敏半导体材料(未掺杂)。半导体材料22优选是提供优异响应性的Ge材料。在替代实施例中，半导体材料22可以是Si、SiGe等。半导体材料22优选地比衬里20厚。
在实施例中，衬里20和附加的半导体材料22将有效地密封沟槽14，从而形成由空气组成的隔离特征。在替代实施例中，在沉积衬里20和附加的半导体材料22之前，可以在沟槽14内沉积电介质材料。电介质材料将有效地导致电介质填充的鳍结构。
在优选的实施方式中，半导体材料22的外延生长不会导致夹断现象，从而在半导体材料22中留下与鳍18相邻的开口或沟槽24。在替代实施例中，可通过本领域公知的光刻和蚀刻工艺来形成开口或沟槽24，因此无需进一步解释便可完全理解本公开。
图3B至图3D示出了图3A的结构的不同构造的俯视图。例如，图3B示出了圆形模式(需要多个鳍结构18)；而图3C示出了螺旋模式(需要单个螺旋鳍结构18)。图3D示出了螺旋八边形模式(需要单个螺旋鳍结构18)。应当理解，本文还预期其他形状，例如嵌套的矩形、嵌套的正方形等。在实施例中，例如与同心圆形状相比，螺旋形状可以具有更大的表面积。另外，本领域技术人员应当理解，鳍18将为光电二极管材料(例如Ge)的生长提供增大的半导体籽晶表面积。这样，除了允许吸收光所需的更薄的光电二极管材料(例如Ge)区域，还缩短了光电二极管材料(例如Ge)的生长时间。此外，鳍18的使用提供了从载流子生成部位(例如Ge材料22)到收集部位(例如衬底12或衬里20)的较短路径，从而提高了光电二极管的效率。与同心圆相比，螺旋形光电二极管还通过增加表面积来提供提高的效率。
在图4中，半导体材料26在光电二极管材料(例如Ge)22的直接上方的开口24中外延生长。在实施例中，半导体材料26也将在光电二极管材料(例如Ge)22的上暴露表面上生长。半导体材料26优选地是与衬里20相同的材料。例如，半导体材料26是P+型半导体材料或多晶硅。在图4中，在生长半导体材料26之后，通过选择性蚀刻工艺去除硬掩模16。
在实施例中，半导体材料26是P+插塞，用于为雪崩光电二极管25的操作提供偏置。以此方式，可以形成N-P-I-P光电二极管25。更具体地，P+材料(例如半导体材料26)和位于Ge材料(例如半导体材料22)的侧面和底部上的P+材料(例如衬里20)形成雪崩光电二极管25，该雪崩光电二极管在三个维度上被偏置，从而增加了在载流子复合之前拾取信号的可能性。
图5示出了除其他特征之外的到光电二极管25的接触形成以及相应的制造工艺。在图5中，半导体材料28(例如多晶硅)被形成在光电二极管25的顶侧上，更具体地，与半导体材料26接触。半导体材料28将用作到半导体材料26(例如，光电二极管25的P+插塞)的顶部的接触。更具体地，半导体材料28将驱动电流引入光电二极管25以使插塞(例如，半导体材料26)偏置，并将载流子从光电二极管25的中心(例如，半导体材料22)驱动到光电二极管25的外侧(例如，半导体材料的衬里20)。以此方式，驱动电流将有效地放大信号。
膜30(例如氮化物或其他硬掩模材料)将覆盖或隔离半导体材料28，以防止在光电二极管25的顶部上形成硅化物。膜30可通过常规的沉积工艺(例如，CVD)沉积，然后执行图案化工艺以暴露位于光电二极管25一侧的衬底12的部分。未硅化的顶面将在光电二极管25的正面照射下提供最佳性能。
在位于光电二极管25的一侧的衬底12的暴露表面上形成硅化物接触32。本领域技术人员应当理解，硅化工艺开始于在衬底12的半导体材料上方沉积并图案化薄过渡金属层(例如，镍、钴或钛)。在沉积和图案化材料之后，加热结构，从而使过渡金属与暴露的硅(或本文所述的其他半导体材料)发生反应，从而形成低电阻过渡金属硅化物。反应之后，通过化学蚀刻去除任何剩余的过渡金属，从而留下硅化物接触30。
仍参考图5，在结构上方沉积层级间电介质材料(例如，氧化物)34。在层级间电介质材料(例如，氧化物)34中形成沟槽，该沟槽与硅化物接触32的上表面对齐并暴露出该上表面。沟槽通过本文已经描述的常规光刻和蚀刻工艺形成。沟槽填充有金属材料(例如钨)以形成接触36。本领域技术人员应当理解，接触36用于检测由光子撞击光电二极管25产生的电流。
图6示出了根据本公开的另外方面的光电二极管25a。更具体地，在图6的结构10a中，提供了不具有与鳍18相关联的沟槽14(例如，隔离特征)的光电二极管25a。以此方式，每个鳍18仅由半导体材料构成。图6的光电二极管25a的剩余结构和制造方法与参考图2至图5所述的类似。
图7示出了根据本公开的另外方面的光电二极管25b。更具体地，在图7的结构10b中，光电二极管25b包括直接在光电二极管25b的顶面(例如半导体材料28)上形成的硅化物接触32a。这种布置适合于背面照射。此后，如参考图5所述，形成到硅化物接触32a、32的接触36。还应当理解，沟槽14的使用也是可选的。
图8示出了包括集成到单个芯片中的光电二极管25和CMOS结构50的结构10c。在该实施例中，光电二极管25类似于图5中描述的光电二极管；但是本文所述的光电二极管中的任何光电二极管均可与CMOS结构50一起使用。CMOS结构50通过浅沟槽隔离区42与光电二极管25隔开，该浅沟槽隔离区42使用已知的光刻、蚀刻和沉积工艺制造，因此无需进一步解释便可完全理解本公开。
在该实施方式中，CMOS结构50包括具有源区和漏区40的栅极结构38。在实施例中，源区和漏区40可以是抬升的外延区或掺杂(例如，掺杂剂或离子注入的)区域。硅化物接触32和接触36被设置成与源区和漏区40接触。在金属栅极实施方式中，接触36与栅极结构38直接接触。此外，CMOS结构50可以直接在体晶片或绝缘体上半导体(SOI)技术上制造。
图9示出了根据本公开的方面的PIN二极管。在该结构10d中，鳍18以交替模式掺杂以提供短P-I-N光电二极管路径长度。例如，鳍18可通过离子注入被掺杂，该离子注入例如在鳍形成之前或之后将一定浓度的掺杂剂引入鳍18中。可通过在鳍中引入一定浓度的导电类型相反的不同掺杂剂，同时使用注入掩模保护其他交替的鳍的方式来掺杂交替的鳍18。每个注入掩模具有足以阻挡掩模区域接收一定剂量的注入离子的厚度和停止能力。例如，注入掩模可以包括光敏材料层，例如有机光致抗蚀剂层，其通过旋涂工艺施加，然后被执行预烘烤，暴露于通过光掩模投射的光下，曝光后烘烤，并用化学显影剂进行显影。除了其他合适的示例之外，交替的鳍可以被掺杂有p型掺杂剂(例如硼(B))和n型掺杂剂(例如砷(As)、磷(P)和Sb)。
可以在片上系统(SoC)技术中利用这些结构。本领域技术人员应当理解，SoC是将电子系统的所有组件集成在单个芯片或衬底上的集成电路(也称为“芯片”)。由于组件集成在单个衬底上，因此与具有等效功能的多芯片设计相比，SoC消耗的功率少得多，占用的面积也小得多。因此，SoC正成为移动计算(例如智能手机)和边缘计算市场中的主导力量。SoC也常用于嵌入式系统和物联网。
上述方法用于集成电路芯片的制造。所得到的集成电路芯片可以由制造商以原始晶片形式(即，作为具有多个未封装芯片的单个晶片)，作为裸芯或以封装形式分发。在后一种情况下，芯片以单芯片封装(例如塑料载体，其引线固定到主板或其它更高级别的载体)或多芯片封装(例如陶瓷载体，其具有表面互连和/或掩埋互连)的形式被安装。在任何情况下，芯片然后与其它芯片、分立电路元件和/或其它信号处理器件集成，作为(a)中间产品(例如主板)或(b)最终产品的一部分。最终产品可以是包括集成电路芯片的任何产品，从玩具和其它低端应用到具有显示器、键盘或其它输入设备以及中央处理器的高级计算机产品。
本公开的各种实施例的描述已经出于说明的目的给出，但并非旨在是穷举的或限于所公开的实施例。在不脱离所描述的实施例的范围和精神的情况下，许多修改和变化对于本领域普通技术人员将是显而易见的。本文中所用术语的选择旨在最好地解释各实施例的原理、实际应用或对市场中发现的技术的技术改进，或者使本技术领域的其他普通技术人员能够理解本文公开的实施例。

Claims (20)

1.一种结构，包括：
至少一个鳍，其包括衬底材料，所述至少一个鳍包括侧壁和顶面；
沟槽，其位于所述至少一个鳍的相反两侧；
第一半导体材料，其给所述至少一个鳍的所述侧壁和所述顶面以及所述沟槽的底面加衬里；
光敏半导体材料，其位于所述第一半导体材料上并且至少部分地填充所述沟槽；以及
第三半导体材料，其位于所述光敏半导体材料上。
2.根据权利要求1所述的结构，其中，所述衬底材料包括单晶半导体材料，并且所述至少一个鳍以螺旋构造设置。
3.根据权利要求1所述的结构，其中，所述衬底材料包括单晶半导体材料，并且所述至少一个鳍包括呈同心嵌套形状的多个鳍，每个鳍被多个沟槽围绕。
4.根据权利要求3所述的结构，其中，所述多个鳍被交替地掺杂不同的掺杂剂类型。
5.根据权利要求1所述的结构，进一步包括通过隔离结构与所述至少一个鳍隔开的晶体管。
6.根据权利要求1所述的结构，其中，所述光敏半导体材料包括本征半导体材料。
7.根据权利要求6所述的结构，其中，所述本征半导体材料包括未掺杂的Ge材料。
8.根据权利要求6所述的结构，其中，所述衬底材料包括N型半导体材料，并且所述第一半导体材料和所述第三半导体材料包括P型半导体材料。
9.根据权利要求6所述的结构，其中，所述第三半导体材料位于沟槽内以及所述光敏半导体材料的顶面上，在所述至少一个鳍的上方，以偏置雪崩光电二极管的操作。
10.根据权利要求6所述的结构，进一步包括位于所述第三半导体材料上的未硅化的半导体材料、位于所述未硅化的半导体材料上方的掩蔽材料，以及电接触所述衬底材料的接触。
11.根据权利要求6所述的结构，进一步包括位于所述第三半导体材料上的硅化的半导体材料、接触所述硅化的半导体材料的第一接触，以及电接触所述衬底材料的第二接触。
12.根据权利要求1所述的结构，进一步包括由所述至少一个鳍内的空气或电介质材料构成的隔离结构。
13.一种结构，包括：
单晶半导体材料的至少一个鳍；
至少一个沟槽，其位于所述至少一个鳍的相反两侧，所述沟槽具有由所述单晶半导体材料构成的底面；
具有第一掺杂剂类型的半导体材料，其给所述至少一个鳍的侧壁和顶面以及所述至少一个沟槽的所述底面加衬里；
光敏半导体材料，其位于所述半导体材料上方并且部分地填充所述至少一个沟槽；以及
具有所述第一掺杂剂类型的第二半导体材料，其填充所述至少一个沟槽的剩余部分，并且与所述至少一个鳍上方的所述光敏半导体材料接触。
14.根据权利要求13所述的结构，其中，所述单晶半导体材料包括N型材料，所述第一掺杂剂类型包括P型材料，并且所述光敏半导体是不同于所述单晶半导体材料的未掺杂的材料。
15.根据权利要求13所述的结构，进一步包括位于所述第二半导体材料上的硅化物接触。
16.根据权利要求13所述的结构，进一步包括位于所述第二半导体材料上的未硅化的半导体材料。
17.根据权利要求13所述的结构，其中，所述本征光敏半导体材料包括未掺杂的Ge材料。
18.根据权利要求13所述的结构，其中，所述单晶半导体材料的至少一个鳍是呈嵌套构造的多个鳍。
19.根据权利要求13所述的结构，其中，所述单晶半导体材料的至少一个鳍呈螺旋构造。
20.一种方法，包括：
形成包括衬底材料的至少一个鳍；
在所述至少一个鳍的相反两侧形成沟槽；
形成第一半导体材料，所述第一半导体材料给所述至少一个鳍以及所述沟槽的底面加衬里；
在所述第一半导体材料上形成光敏半导体材料，所述光敏半导体材料至少部分地填充所述沟槽；以及
在所述光敏半导体材料上形成第三半导体材料。
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