CN113707706A - Power semiconductor device and method for manufacturing the same - Google Patents

Power semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN113707706A
CN113707706A CN202010626538.9A CN202010626538A CN113707706A CN 113707706 A CN113707706 A CN 113707706A CN 202010626538 A CN202010626538 A CN 202010626538A CN 113707706 A CN113707706 A CN 113707706A
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substrate
semiconductor device
power semiconductor
region
stop layer
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刘鹏飞
王波
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Huada Semiconductor Co ltd
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Huada Semiconductor Co ltd
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

The invention provides a power semiconductor device and a preparation method thereof, wherein the device comprises: a substrate of a first conductivity type; a well region of a second conductivity type disposed on the first major surface of the substrate; the trench gate structure is arranged on the first main surface of the substrate and penetrates through the well region to the substrate; the source electrode of the first conduction type is arranged in the well region and is positioned on the side face of the trench gate structure; a collector of the second conductivity type provided on the second main surface of the substrate; the field stop layer of the first conduction type is arranged on the second main surface of the substrate and is positioned between the collector and the substrate; and the low-lifetime region is arranged on the second main surface of the substrate and is positioned in the field stop layer and close to the collector, and the low-lifetime region contains defects so as to reduce the lifetime of minority carriers. The invention can effectively reduce the trailing current of the device, further reduce the turn-off loss of the device, improve the switching frequency of the device and reduce the risk of cross conduction.

Description

Power semiconductor device and method for manufacturing the same
Technical Field
The invention belongs to the field of semiconductor design and manufacture, and particularly relates to a power semiconductor device and a preparation method thereof.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a composite fully-controlled voltage-driven power semiconductor device consisting of a Bipolar Junction Transistor (BJT) and an insulated Gate field effect transistor (MOS), and has the advantages of high input impedance of the MOSFET and low conduction voltage drop of the GTR. The GTR saturation voltage is reduced, the current density is high, but the driving current is high; the MOSFET has small driving power, high switching speed, large conduction voltage drop and small current density. The IGBT integrates the advantages of the two devices, and has small driving power and reduced saturation voltage. Therefore, the application of the semiconductor is more and more extensive, and the semiconductor is an important power semiconductor device.
IGBTs are devices that operate with dual carriers, and two different current topologies can temporarily appear in the device body: one electron current (MOSFET current) and the other hole current (bipolar). In the existing FS IGBT (field stop) technology, when a negative bias is applied to the gate or the gate voltage is lower than a threshold value, the channel is inhibited and no holes are injected into the N-type drift region. In any case, the MOSFET current drops rapidly during the switching phase and the collector current gradually decreases, because after the turn-off has started there are still minority carriers (minority carriers) in the N-type drift region, forming a tail current. The rate of decrease of this tail current depends on the density of charge at turn-off and the lifetime of the carriers. The slow decay of minority carriers can increase the tailing current of the collector, and the tailing time is prolonged.
The collector tail current causes the following problems: 1) turn-off loss increases: turn-off loss is VCEAnd ICEThe product is integrated over time, when VCEHas risen to VCCThe voltage is higher, so the power loss is larger, and the turn-off loss is increased more; 2) the cross-conduction problem is more pronounced, particularly in devices that use freewheeling diodes.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a power semiconductor device and a method for manufacturing the same, which are used to solve the problems of the prior art that the collector tail current is large and the time is long in the power semiconductor device.
To achieve the above and other related objects, the present invention provides a power semiconductor device including: a substrate of a first conductivity type including opposing first and second major faces; a well region of a second conductivity type disposed on the first major surface of the substrate; the trench gate structure is arranged on the first main surface of the substrate and penetrates through the well region to the substrate; the source electrode of the first conduction type is arranged in the well region and is positioned on the side face of the trench gate structure; a collector of a second conductivity type provided on a second main surface of the substrate; the field stop layer is arranged on the second main surface of the substrate and is positioned between the collector and the substrate; and the low-lifetime region is arranged on the second main surface of the substrate and is positioned in the field stop layer and close to the collector, and the low-lifetime region contains defects so as to reduce the lifetime of minority carriers.
Optionally, the low lifetime region comprises He implantation to form the defect.
Optionally, the low lifetime region comprises an H implant to form the defect.
Optionally, the low lifetime region comprises a defect density of 1E 12-1E 19/cm3In the meantime.
Optionally, the thickness of the low lifetime region ranges from 3 to 20 microns.
Optionally, the doping ions of the field stop layer comprise H, and the doping concentration of the field stop layer ranges from 1E13 to 1E16/cm3The thickness of the field stop layer ranges from 5 microns to 40 microns.
Optionally, the power semiconductor device further includes a termination structure located at a periphery of the power semiconductor device, the termination structure including a termination field oxide region and a termination field limiting ring region of the first conductivity type.
Optionally, the first conductivity type is an N-type conductivity type, and the second conductivity type is a P-type conductivity type; or: the first conductivity type is a P-type conductivity type, and the second conductivity type is an N-type conductivity type.
The present invention also provides a method for manufacturing a power semiconductor device, the method comprising: 1) providing a substrate of a first conductivity type, wherein the substrate of the first conductivity type comprises a first main surface and a second main surface which are opposite; 2) arranging a well region of a second conduction type, a trench gate structure and a source electrode of a first conduction type on a first main surface of the substrate, wherein the trench gate structure penetrates through the well region to the substrate, and the source electrode of the first conduction type is arranged in the well region and is positioned on the side surface of the trench gate structure; 3) forming a field stop layer of a first conductivity type and a low lifetime region in a second main surface of the substrate, the low lifetime region being located at a bottom of the field stop layer, the low lifetime region including defects to reduce a lifetime of minority carriers; 4) and forming a collector of the second conductivity type on the second main surface of the substrate.
Optionally, the step 3) of forming a field stop layer of the first conductivity type and a low lifetime region in the second main surface of the substrate includes: 3-1) performing H implantation on the substrate; 3-2) annealing and activating at 350-470 ℃ to form the field stop layer in the substrate; 3-3) performing He injection on the substrate, wherein the injection energy range is between 200Kev and 5 Mkev; 3-4) annealing to form defects in the substrate to form the low-lifetime region in the substrate.
Optionally, the step 3) of forming a field stop layer of the first conductivity type and a low lifetime region in the second main surface of the substrate includes: 3-1) performing H implantation on the substrate, wherein the implantation energy range is between 200Kev and 5 Mkev; 3-2) annealing at not less than 500 ℃ to form defects in the substrate to form the low lifetime region in the substrate; 3-3) carrying out H implantation on the substrate; 3-4) annealing and activating at 350-470 ℃ to form the field stop layer in the substrate
Optionally, in step 3), the low lifetime region comprisesThe defect density of (a) is 1E 12-1E 19/cm3In the meantime.
Optionally, in step 3), the thickness of the low lifetime region ranges from 3 to 20 μm.
Optionally, the doping concentration of the field stop layer ranges from 1E13 to 1E16/cm3The thickness of the field stop layer ranges from 5 microns to 40 microns.
Optionally, the preparation method further comprises: a termination structure is formed at a periphery of the power semiconductor device, the termination structure including a termination field oxide region and a termination field limiting ring region of a first conductivity type.
Optionally, the first conductivity type is an N-type conductivity type, and the second conductivity type is a P-type conductivity type; or: the first conductivity type is a P-type conductivity type, and the second conductivity type is an N-type conductivity type.
As described above, the power semiconductor device and the method for manufacturing the same according to the present invention have the following advantageous effects:
according to the invention, the service life of the minority carrier in the region is reduced by controlling the service life of the field stop layer (FS layer) close to the collector and introducing defects into the field stop layer, so that the minority carrier is rapidly compounded in the later stage of the turn-off process of the power semiconductor device, the trailing current of the device is reduced, the turn-off loss of the device is further reduced, the switching frequency of the device can be improved, and the risk of cross conduction is reduced.
Drawings
Fig. 1 to 8 are schematic structural diagrams of steps of a method for manufacturing a power semiconductor device according to the present invention, wherein fig. 8 is a schematic structural diagram of a power semiconductor device according to the present invention.
Fig. 9 is a graph showing a comparison between waveforms of tail currents of a power semiconductor device according to the prior art and a power semiconductor device according to the present invention.
Description of the element reference numerals
101 substrate
101a first main surface
101b second main surface
102 well region
103 trench gate structure
104 source electrode
105 electrode metal layer
106 terminal field limiting ring region
107 terminal field oxide region
107' isolation region
108 field stop layer
109 low lifetime region
110 collector electrode
111 metal electrode
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1 to 7, the present embodiment provides a method for manufacturing a power semiconductor device, the method including the steps of:
as shown in fig. 1, step 1) is first performed to provide a substrate 101 of a first conductivity type, where the substrate 101 of the first conductivity type includes a first main surface 101a and a second main surface 101b opposite to each other.
The substrate 101 may be a semiconductor substrate 101, such as a silicon substrate 101, a germanium substrate 101, a silicon carbide substrate 101, or a gallium arsenide substrate 101, and is not limited to the examples listed herein. The substrate 101 may be an N-type doped substrate 101 or a P-type doped substrate 101, in this embodiment, the substrate 101 is an N-type doped silicon substrate 101, and the doped ions may be phosphorus, etc., of course, in other embodiments, the substrate 101 may also be a P-type doped substrate, for example, the doped ions may be boron, etc., which may be selected according to the actual requirements of the device.
As shown in fig. 2 to 4, step 2) is then performed to dispose a well region 102 of a second conductivity type, a trench gate structure 103 and a source 104 of a first conductivity type on the first main surface 101a of the substrate 101, where the trench gate structure 103 penetrates through the well region 102 to the substrate 101, and the source 104 of the first conductivity type is disposed in the well region 102 and located on a side surface of the trench gate structure 103.
Specifically, the following steps may be included:
as shown in fig. 2, step 2-1) is performed to perform ion implantation on the first main surface 101a of the substrate 101, in this embodiment, P-type ion implantation is performed on the substrate 101, the implanted ions may be boron, and then annealing activation is performed to form a P-type well region 102 on the first main surface 101a of the substrate 101.
As shown in fig. 3, step 2-2) is performed to form a trench penetrating through the well region 102 to the substrate 101 in the substrate 101 through a photolithography process and an etching process, form a gate oxide layer or a high-K dielectric layer on a sidewall of the trench, and then fill a gate material, such as polysilicon or a metal material, in the trench to form the trench gate structure 103.
As shown in fig. 4, performing step 2-3), forming an N-type source 104 in the well region 102 by an ion implantation process and an annealing process, where the N-type source 104 is located on a side surface of the trench gate structure 103; then, forming a P-type terminal field limiting ring region 106 at the periphery of the power semiconductor device through an ion implantation process and an annealing process, where the P-type terminal field limiting ring region 106 includes a plurality of P-type doped regions arranged at intervals, as shown in fig. 4, and forming a terminal field oxide region 107 on the terminal region through a thermal oxidation or deposition process to form a terminal structure of the semiconductor device, and simultaneously forming an isolation region 107' above the trench gate structure 103 for isolating the trench gate structure 103 from the electrode metal layer 105; next, an electrode metal layer 105 is formed on the source 104 and the trench gate structure 103 as a metal electrode 111 of the source 104.
As shown in fig. 5 to 7, step 3) is performed to form a field stop layer 108 of the first conductivity type and a low lifetime region 109 in the second main surface 101b of the substrate 101, wherein the low lifetime region 109 is located at the bottom of the field stop layer 108, and the low lifetime region 109 includes defects to reduce the lifetime of minority carriers. In this embodiment, the field stop layer 108 is doped N-type.
In one embodiment, step 3) comprises: first, the substrate 101 is thinned to a desired thickness to reduce the on-resistance of the semiconductor device and reduce the on-voltage drop. Then, H implantation is carried out on the substrate 101, and annealing activation is carried out at 350-470 ℃ so as to form the field stop layer 108 in the substrate 101. For example, the conditions for annealing activation may be 400 ℃. Then, performing He injection on the substrate 101, wherein the injection energy range is between 200Kev and 5 Mkev; finally, annealing is performed to form defects in the substrate 101 to form the low lifetime region 109 in the substrate 101.
In the above step, He is injected to form a defect in the substrate 101, and the defect can enable minority carriers to be rapidly recombined at the later stage of the turn-off process of the power semiconductor device, so that the trailing current of the device is reduced, the turn-off loss of the device is further reduced, the switching frequency of the device can be improved, and the risk of cross conduction is reduced, wherein He is easy to form a defect in the substrate 101, the condition of He annealing is wide, and only the front structure needs to be ensured not to be damaged.
In the embodiment, the doping concentration range of the field stop layer 108 is 1E 13-1E 16/cm3The thickness of the field stop layer 108 is in the range of 20-40 μm.
In the present embodiment, the low lifetime region 109 comprises a defect density of 1E 12-1E 19/cm3The thickness of the low lifetime region 109 is in the range of 3 to 20 μm.
In another embodiment, step 3) comprises: first, the substrate 101 is thinned to a desired thickness to reduce the on-resistance of the semiconductor device and reduce the on-voltage drop. Then, performing He injection on the substrate 101, wherein the injection energy range is between 200Kev and 5 Mkev; next, annealing is performed at a temperature of not less than 500 ℃ to form defects in the substrate 101 to form the low lifetime region 109 in the substrate 101; and finally, performing H implantation on the substrate 101, and performing annealing activation at 350-470 ℃ to form the field stop layer 108 in the substrate 101. In the implementation process, since the temperature for forming the low lifetime region 109 is higher than that for forming the field stop layer 108, the field stop layer 108 needs to be formed after the low lifetime region 109 is formed, so as to avoid the defect of the field stop layer 108 caused by high temperature annealing, and improve the performance and stability of the device.
In the above steps, unlike the preparation process of the field stop layer 108, in this embodiment, a defect may be formed in the substrate 101 by injecting H and annealing at a temperature not lower than 500 ℃, and the defect may enable minority carriers to be rapidly recombined at a later stage of a turn-off process of the power semiconductor device, so as to reduce a trailing current of a device, thereby reducing turn-off loss of the device, and at the same time, improving a switching frequency of the device, and reducing a risk of cross conduction.
As shown in fig. 8, step 4) is finally performed to form a collector 110 of the second conductivity type on the second main surface 101b of the substrate 101.
Specifically, the method comprises the following steps: a collector 110 of the second conductivity type is formed on the second main surface 101b of the substrate 101 through an ion implantation and annealing process, in this embodiment, the implanted ions may be boron, and the collector 110 is doped P-type. Then, a metal electrode 111 is formed on the surface of the collector 110 and ohmic contact is formed with the collector 110 to reduce contact resistance.
With the semiconductor device of the above embodiment, the first conductivity type is an N-type conductivity type, and the second conductivity type is a P-type conductivity type; of course, in other embodiments, the first conductive type may also be a P-type conductive type, and the second conductive type may also be an N-type conductive type.
As shown in fig. 8, the present embodiment also provides a power semiconductor device including: a substrate 101 of a first conductivity type including a first main face 101a and a second main face 101b opposed to each other; a well region 102 of a second conductivity type provided on the first main surface 101a of the substrate 101; a trench gate structure 103 disposed on the first main surface 101a of the substrate 101 and penetrating through the well region 102 into the substrate 101; a source 104 of the first conductivity type disposed in the well region 102 and located on a side surface of the trench gate structure 103; a collector 110 of the second conductivity type provided on the second main surface 101b of the substrate 101; a field stop layer 108 of the first conductivity type disposed on the second main surface 101b of the substrate 101 and between the collector 110 and the substrate 101; and a low lifetime region 109 disposed on the second main surface 101b of the substrate 101 and located in the field stop layer 108 near the collector 110, wherein the low lifetime region 109 includes defects to reduce the lifetime of minority carriers. Preferably, the low lifetime region 109 may be located in the field stop layer 108 and connected to the collector; of course, the low lifetime region 109 may also be located in the field stop layer 108 and have a distance from the collector, which may be no greater than 5 μm. Such as the pitch may be 2 microns or 3 microns, and is not limited to the examples listed herein.
The substrate 101 may be a semiconductor substrate 101, such as a silicon substrate 101, a germanium substrate 101, a silicon carbide substrate 101, or a gallium arsenide substrate 101, and is not limited to the examples listed herein. The substrate 101 may be an N-type doped substrate 101 or a P-type doped substrate 101, in this embodiment, the substrate 101 is an N-type doped silicon substrate 101, and the doped ions may be phosphorus, etc., of course, in other embodiments, the substrate 101 may also be a P-type doped substrate, for example, the doped ions may be boron, etc., which may be selected according to the actual requirements of the device.
The trench gate structure 103 includes a trench penetrating through the well region 102 to the substrate 101, a gate oxide layer or a high-K dielectric layer located on a sidewall of the trench, and a gate material filled in the trench, such as polysilicon or a metal material, and an isolation region 107' is formed above the trench gate structure 103 for isolating the trench gate structure 103 from the electrode metal layer 105.
The doped ions of the field stop layer 108 comprise H, and the doping concentration of the field stop layer 108 ranges from 1E13 to 1E16/cm3The thickness of the field stop layer 108 is in the range of 5-40 μm.
The low lifetime region 109 has a defect density of 1E 12-1E 19/cm3The thickness of the low lifetime region 109 is in the range of 3 to 20 μm.
In a particular embodiment, the low lifetime region 109 may include He implantation to form the defect. The implantation of He can form defects in the substrate 101, and the defects can enable minority carriers to be quickly recombined at the later stage of the turn-off process of the power semiconductor device, so that the trailing current of a device is reduced, the turn-off loss of the device is further reduced, the switching frequency of the device can be improved, and the risk of cross conduction is reduced.
In another embodiment, the low lifetime region 109 may also include an H implant to form the defects. Unlike the preparation process of the field stop layer 108, in this embodiment, a defect may be formed in the substrate 101 by injecting H and annealing at a temperature not lower than 500 ℃, and the defect may enable minority carriers to be rapidly recombined at a later stage of a turn-off process of the power semiconductor device, thereby reducing a tail current of the device, further reducing turn-off loss of the device, and simultaneously improving a switching frequency of the device and reducing a risk of cross conduction.
As shown in fig. 8, in the present embodiment, the power semiconductor device further includes a terminal structure located at the periphery of the power semiconductor device, the terminal structure includes a terminal field oxide region 107 and a terminal field limiting ring region 106 of the first conductivity type, and the terminal field limiting ring region 106 of the first conductivity type includes a plurality of P-type doped regions arranged at intervals.
With the semiconductor device of the above embodiment, the first conductivity type is an N-type conductivity type, and the second conductivity type is a P-type conductivity type; of course, in other embodiments, the first conductive type may also be a P-type conductive type, and the second conductive type may also be an N-type conductive type. As described above, the power semiconductor device and the method for manufacturing the same according to the present invention have the following advantageous effects:
fig. 9 is a graph showing a comparison between the waveforms of tail currents of the power semiconductor device (a) of the related art of the present invention and the power semiconductor device (B) of the present invention. According to the invention, by controlling the service life of the field stop layer 108(FS layer) close to the collector 110 and introducing defects into the field stop layer 108, the service life of minority carriers in the region is reduced, so that the minority carriers are quickly combined in the later stage of the turn-off process of the power semiconductor device, the trailing current of a device is reduced, the turn-off loss of the device is further reduced, the switching frequency of the device can be improved, and the risk of cross conduction is reduced.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (14)

1. A power semiconductor device, characterized in that the power semiconductor device comprises:
a substrate of a first conductivity type including opposing first and second major faces;
a well region of a second conductivity type disposed on the first major surface of the substrate;
the trench gate structure is arranged on the first main surface of the substrate and penetrates through the well region to the substrate;
the source electrode of the first conduction type is arranged in the well region and is positioned on the side face of the trench gate structure;
a collector of a second conductivity type provided on a second main surface of the substrate;
the field stop layer is arranged on the second main surface of the substrate and is positioned between the collector and the substrate;
and the low-lifetime region is arranged on the second main surface of the substrate and is positioned in the field stop layer and close to the collector, and the low-lifetime region contains defects so as to reduce the lifetime of minority carriers.
2. The power semiconductor device of claim 1, wherein: the low-lifetime region includes He implantation to form the defect.
3. The power semiconductor device of claim 1, wherein: the low lifetime region includes an H implant to form the defects.
4. The power semiconductor device of claim 1, wherein: the low lifetime region has a defect density of 1E 12-1E 19/cm3In the meantime.
5. The power semiconductor device of claim 1, wherein: the thickness of the low-life region ranges from 3 microns to 20 microns.
6. The power semiconductor device of claim 1, wherein: the doped ions of the field stop layer comprise H, and the doping concentration range of the field stop layer is 1E 13-1E 16/cm3The thickness of the field stop layer ranges from 5 microns to 40 microns.
7. The power semiconductor device of claim 1, wherein: the power semiconductor device further includes a termination structure located at a periphery of the power semiconductor device, the termination structure including a termination field oxide region and a termination field limiting ring region of the first conductivity type.
8. A method of fabricating a power semiconductor device, the method comprising:
1) providing a substrate of a first conductivity type, wherein the substrate of the first conductivity type comprises a first main surface and a second main surface which are opposite;
2) arranging a well region of a second conduction type, a trench gate structure and a source electrode of a first conduction type on a first main surface of the substrate, wherein the trench gate structure penetrates through the well region to the substrate, and the source electrode of the first conduction type is arranged in the well region and is positioned on the side surface of the trench gate structure;
3) forming a field stop layer of a first conductivity type and a low lifetime region in a second main surface of the substrate, the low lifetime region being located at a bottom of the field stop layer, the low lifetime region including defects to reduce a lifetime of minority carriers;
4) and forming a collector of the second conductivity type on the second main surface of the substrate.
9. The method for manufacturing a power semiconductor device according to claim 8, wherein: step 3) forming a field stop layer of the first conductivity type and a low lifetime region in the second main surface of the substrate, including:
3-1) performing H implantation on the substrate;
3-2) annealing and activating at 350-470 ℃ to form the field stop layer in the substrate;
3-3) performing He injection on the substrate, wherein the injection energy range is between 200Kev and 5 Mkev;
3-4) annealing to form defects in the substrate to form the low-lifetime region in the substrate.
10. The method for manufacturing a power semiconductor device according to claim 8, wherein: step 3) forming a field stop layer of the first conductivity type and a low lifetime region in the second main surface of the substrate, including:
3-1) performing H implantation on the substrate, wherein the implantation energy range is between 200Kev and 5 Mkev;
3-2) annealing at not less than 500 ℃ to form defects in the substrate to form the low lifetime region in the substrate;
3-3) carrying out H implantation on the substrate;
3-4) annealing and activating at 350-470 ℃ to form the field stop layer in the substrate.
11. The method for manufacturing a power semiconductor device according to claim 8, wherein: in the step 3), the defect density in the low-lifetime region is 1E 12-1E 19/cm3In the meantime.
12. The method for manufacturing a power semiconductor device according to claim 8, wherein: in the step 3), the thickness range of the low-service-life area is between 3 and 20 micrometers.
13. The method for manufacturing a power semiconductor device according to claim 8, wherein: the doping concentration range of the field stop layer is 1E 13-1E 16/cm3The thickness of the field stop layer ranges from 5 microns to 40 microns.
14. The method for manufacturing a power semiconductor device according to claim 8, wherein: the preparation method further comprises the following steps: a termination structure is formed at a periphery of the power semiconductor device, the termination structure including a termination field oxide region and a termination field limiting ring region of a first conductivity type.
CN202010626538.9A 2020-05-21 2020-07-01 Power semiconductor device and method for manufacturing the same Pending CN113707706A (en)

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