CN113632222A - 用于集成电路中的裸片到裸片通信的间隔件 - Google Patents

用于集成电路中的裸片到裸片通信的间隔件 Download PDF

Info

Publication number
CN113632222A
CN113632222A CN202080023404.6A CN202080023404A CN113632222A CN 113632222 A CN113632222 A CN 113632222A CN 202080023404 A CN202080023404 A CN 202080023404A CN 113632222 A CN113632222 A CN 113632222A
Authority
CN
China
Prior art keywords
spacer
dies
die
fabricating
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202080023404.6A
Other languages
English (en)
Inventor
C·L·阿文
B·辛格
R·F·因戴克
S·P·奥斯特朗德
T·魏斯
M·W·卡普哈默
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN113632222A publication Critical patent/CN113632222A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种多裸片集成电路器件及制造所述多裸片集成电路器件的方法涉及衬底。两个或多个裸片包括实现多裸片集成电路的功能的部件。这些部件包括逻辑门。多裸片集成电路器件还包括设置在衬底与两个或多个裸片中的每一个裸片之间的间隔件。两个或多个裸片中的每一个裸片与衬底直接电接触，而不与间隔件通过间隔件中的孔进行直接电接触。

Description

用于集成电路中的裸片到裸片通信的间隔件
背景技术
本发明涉及集成电路，并且更具体地涉及用于集成电路中的裸片(die)到裸片通信的间隔件。
典型地，集成电路是通过光刻工艺在单个晶片上生产的。晶片被切割(即，切成裸片)成许多片，每个片被称为裸片(die)。每个裸片通常是电路的副本。随着裸片继续变得更复杂并且尺寸增加，裸片产量减小。这是因为，对于给定的缺陷密度，裸片的增加的密度导致随机缺陷的更高机会。减少产量损失的方法涉及分裂裸片以减少密度且因此减少缺陷。然而，将单个裸片的部件分割成两个或更多个裸片需要在裸片之间以足够高的速率进行更大的通信。硅(Si)桥已经用于互连裸片，但是在组装时已经导致显著的挑战。互连裸片的Si中介层需要穿硅过孔(TSV)工艺，并且还导致组装挑战。此外，Si中介层还可能存在功率递送和信号完整性问题。
发明内容
本发明的实施例涉及多裸片集成电路器件和制造多裸片集成电路器件的方法，该多裸片集成电路器件涉及衬底和包括实现多裸片集成电路的功能的部件的两个或多个裸片。这些部件包括逻辑门。多裸片集成电路器件还包括设置在衬底与两个或多个裸片中的每一个裸片之间的间隔件。两个或多个裸片中的每一个裸片与衬底直接电接触，而不与间隔件通过间隔件中的孔直接电接触。
附图说明
参考以下附图和描述将更好地理解贯穿本文件所描述的实例。附图中的部件不一定是按比例的。此外，在附图中，贯穿不同视图，相同参考标号指代对应部分。
图1示出了根据本发明的实施例的用于裸片到裸片通信的间隔件；
图2示出了有助于裸片到裸片通信的间隔件的细节；
图3详述了有助于裸片到裸片通信的间隔件的各方面；
图4示出了根据本发明实施方式的具有用于裸片到裸片通信的间隔件的集成电路的截面图；
图5示出了根据本发明的实施例的包括电容器的用于裸片到裸片通信的间隔件的截面图；
图6是根据本发明的实施例的用于执行集成电路开发的系统的框图，该集成电路开发包括使用间隔件实现裸片到裸片的通信；并且
图7是根据本发明的实施例的制造包括间隔件的多裸片集成电路的方法的工艺流程。
具体实施方式
如前所述，将集成电路的部件从一个裸片分布到两个或更多个裸片可以减少每个裸片上的缺陷，并且因此减少产量损失。将集成电路功能分布到两个或更多个裸片上需要以足够高的速率进行裸片到裸片的通信。Si桥是裸片到裸片通信的现有方法。Si将一个裸片直接桥接到另一个裸片，并且在裸片接合的同一侧上。桥不与衬底电连接。内插器是另一种现有方法并且促进多个裸片之间的互连。电通路(例如，TSV)是内插器的一部分并且通过内插器形成电连接，并且内插器与衬底形成电连接。如前所述，Si桥和内插器存在组装挑战。本文中详述的本发明的实施例涉及用于集成电路中的裸片到裸片通信的间隔件。与内插器不同，根据本文详述的本发明的一个或多个实施例制造的间隔件不需要电通路。每一裸片具有导电柱，所述导电柱穿过间隔件的孔以在间隔件的与裸片的另一侧上直接接触衬底。
图1示出了用于裸片到裸片通信的间隔件110。集成电路100被细分成四个裸片130a、130b、130c、130d(通常称为130)。在本发明的替代实施例中，集成电路100可以被细分为两个或更多个裸片130，并且不限于四个。间隔件110的周边大于包围裸片130的组合的周边。在本发明的替代实施例中，如图3所示，间隔件110的周边可以小于包围裸片130的组合的周边，或者间隔件110的周边和包围裸片130的周边可以是相同的尺寸。每个裸片130包括多个部件135a至135n(通常称为135)。每个裸片130内的部件135(例如，逻辑门、缓冲器、锁存器)以常规方式互连以实现集成电路100的功能。此外，基于根据本文详述的本发明的实施例设计和制造的间隔件110，每个裸片130的部件135可以基于间隔件110的引线115与多裸片集成电路100的另一个裸片130的部件135通信。裸片130在通过引线115互连的同一侧(即，根据图1中的视图，在每个裸片130下方)接合。
例如，根据图1所示的示例，引线115促进裸片130a与裸片130b和130c之间的通信，但不促进裸片130a与裸片130d之间的通信。如果需要的话，间隔件110中可以包括对角引线115以促进例如裸片130a和裸片130d之间或者裸片130b和裸片130c之间的通信。图1中所示的示例性引线115旨在是说明性的而非排他性的，并且不限制根据引线115的替代布置的附加的裸片到裸片通信。引线115可以促进50至500千兆赫(GHz)范围内的通信速度。包括有助于裸片到裸片通信的引线115的间隔件110被设置在裸片130和衬底120(例如，有机层压体)之间。间隔件110的特征参见图2进一步详述。
图2示出了有助于裸片到裸片通信的间隔件110的细节。制造间隔件110的材料可以是玻璃、Si、陶瓷或有机低热膨胀系数(CTE)材料。示出了促进裸片到裸片通信的引线115。可以存在许多层(例如，大约4-10层)导线，其中间距(即，导线之间的距离)大约15-20微米，使用双镶嵌工艺形成。
焊盘113用于将间隔件110机械地连接至裸片130。焊盘113在图2中被示出在间隔件110上。具体地，焊盘113可以是间隔件110的钝化氧化物层520(图5)内的铜(Cu)微焊盘。根据本发明的另一个实施例，焊盘113可以在裸片130上并且具有焊料帽盖430的微柱420可以在间隔件110上，如图4所示。Si间隔件110可以包括形成为间隔件110内的层的电容器510(图5)。有机物、玻璃或陶瓷间隔件110可包括薄膜电容器。在这种情况下，焊盘113还充当裸片130与电容器之间的电连接。引线115的端部处的焊盘114形成由引线115互连的裸片130之间的电连接。例如，可存在约3500-5000个焊盘114以促进裸片到裸片通信。焊盘113、114可与图2中所示不同地成形。Spar(加强元件)可添加至间隔件110的与衬底120相同的一侧。间隔件110还包括将参见图3进一步讨论的孔117。
图3示出了用于裸片到裸片通信的间隔件110。间隔件110的周边小于包围裸片130的组合的周边。不同于图1，其示出了示例性间隔件110的视图，其中，衬底120在下方，并且裸片130在上方，出于说明的目的，图3示出了间隔件110下方的裸片130。因此，在图3中所示的视图中将裸片130互连的间隔件110的高密度引线115是不可见的。此外，未示出根据图3中的视图将位于间隔件110上方的衬底120。在裸片130上示出了支柱310。间隔件110中的孔117中的一些孔促进裸片130的这些导电柱310的穿过，裸片130的这些导电柱310将在间隔件110的相对侧上直接接触衬底120。因为根据图3所示的实施例，间隔件110的周边小于包围裸片130的周边，所以裸片130也具有在间隔件110的周边外部的导电柱310。这些导电柱310将接触衬底120而不穿过间隔件110中的孔117。
虽然根据示范性实施例将孔117展示为圆形，但孔117可为促进导电柱410穿过而不接触间隔件110的任何形状。即，举例来说，圆形孔117的直径可大于穿过孔117的导电柱310的直径约20微米。孔117的直径约为100微米。如果间隔件110的材料为Si，那么可钝化孔117以防止与导电柱310短路。孔117经形成以与导电柱310对准，使得导电柱310实质上以孔117为中心。在裸片130与间隔件110之间存在比导电柱310更多的孔117(尽管在间隔件110的周边之外可以存在额外的柱310，如在图3中示出的本发明的实施例中)。如参考图4所论述，不充当导电柱310的通孔的孔117和导电柱310外部的孔117的部分可具有分配于其中的底部填充物410(图4)。
图4示出了具有用于裸片到裸片通信的间隔件110的集成电路100的横截面视图。该截面图示出了与间隔件110的引线115互连的两个裸片130。图4中所示的示范性间隔件110的周边与包围裸片130的周边相同。作为裸片130的一部分的导电柱310被示出为延伸以将每个裸片130连接到衬底120。导电柱410可以是例如Cu。如前所述，导电柱310不填充间隔件110中的孔117(图2和3)。而是，导电柱310的直径小于孔117的直径，使得导电柱310穿过但不接触间隔件110。例如，导电柱310的直径可在80微米的量级，而如先前所述，孔117的直径可在100微米的量级。导电柱310的高度(必须至少与间隔件110的厚度相同以到达衬底120)可为约150微米到200微米的量级。还注意到，所有孔不用于通过导电柱310。其他孔117便于从间隔件110的任一侧分配底部填充410。
示出了间隔件110与裸片130之间的焊盘113。由于底部填充420，引线115与裸片130之间的焊盘114以及引线115的方面在图4中是不可见的。如前所述，存在比导电柱310更多的孔117。底部填充物410可分配于隔离件孔117中的导电柱410周围的开放区中，如所展示。底部填充物410是分配在衬底120上的聚合物质。毛细管作用将底部填充物410吸引到每个裸片130与衬底120之间(到间隔件110的孔117中)。热固化导致裸片130和衬底120的机械耦合。底部填充物410包封如引线115的互连结构并且在整个裸片130上均匀地分布应力而不是将应力集中在焊料接合处。由此，底部填充410充当应力缓冲器，其吸收每个裸片130与衬底120之间的CTE失配并保护焊料接合和互连免受过早失效。根据图4中所示的本发明的示范性实施例，焊盘113在裸片130上。如裸片130与间隔件110之间的一个连接的详细视图所示，间隔件110的具有焊料帽盖430的微柱420可以与裸片130的焊盘113连接。微柱420可约为10微米深。
图5示出了包括电容器510的用于裸片到裸片通信的间隔件110的横截面视图。在电容器510上方示出钝化氧化物520。展开图显示氧化物520内的焊盘113。可以使用深沟槽(DT)形成或金属-绝缘体-金属(MIM)配置来形成电容器510。根据MIM配置，电容器可占据间隔件110的横截面面积的高达95％。DT电容器510可以是大约20至100微米宽，而MIM电容器510可以是大约0.5至10微米宽。如图5所示，电容器510围绕间隔件110的孔117形成。
图6是用于执行集成电路开发的系统600的框图，该集成电路开发包括实现具有间隔件110的裸片到裸片通信。系统600包括处理电路610和用于生成最终被制造到多裸片集成电路100中的设计的存储器615。在开发设计以满足功能、功率和时序要求时涉及的阶段(例如，逻辑设计、逻辑合成、物理合成)不是新的并且在此不详述。确实注意到，物理合成和布局阶段可以考虑集成电路100将最终被分成多个裸片130。最终化的物理布局被提供给半导体制造商(例如，铸造厂)。基于最终化的物理布局，为集成电路100的每个裸片130的每个层生成掩模。然后，按照掩模命令的顺序处理晶片。该处理包括光刻和蚀刻。参考图7进一步讨论制造。
图7是制造包括间隔件110的多裸片集成电路100的方法的工艺流程。通常，制造并切割(即，切成裸片)具有最终设计的多个副本的晶片，使得每个裸片是集成电路100的一个副本。在多裸片配置的情况下，每个裸片被进一步细分成经由间隔件110彼此通信的裸片130。在框710处，工艺包括基于最终化的物理布局来制造用于光刻的掩模。在框720，制造晶片包括使用掩模来执行光刻和蚀刻。一旦晶片被切割成裸片130，则在框730处对每个裸片执行测试和分类以滤除任何有缺陷的裸片。如前所述，将器件细分成多个裸片130的原因之一是减少故障。在框740处，如先前所讨论的，将根据本发明的一个或多个实施例的间隔件110耦合在裸片130与衬底之间，以产生具有裸片到裸片通信的集成电路100。
在此所使用的术语仅用于描述具体实施例的目的并且不旨在限制本发明。如在此使用的，单数形式“一个”、“一种”和“该”旨在也包括复数形式，除非上下文另外清楚地指示。将进一步理解的是，当在本说明书中使用术语“包括”和/或“包含”时，其指定所陈述的特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或多个其他特征、整数、步骤、操作、元件部件和/或其组的存在或添加。
以下权利要求书中的所有装置或步骤加上功能元件的相应结构、材料、动作和等效物旨在包括用于结合如具体要求保护的其他要求保护的元件来执行功能的任何结构、材料或动作。已经出于说明的目的呈现了本发明的描述，但并非旨在是穷尽性的或局限于本发明的所公开的形式。在不脱离本发明的范围和精神的情况下，许多修改和变化对本领域的普通技术人员将是显而易见的。选择和描述实施例以便最好地解释本发明的原理和实际应用，并且使得本领域普通技术人员能够针对具有适合于所设想的特定用途的不同修改的不同实施例理解本发明。
在此所描绘的流程图仅是一个实例。在不背离本发明的精神的情况下，可以对该图或其中描述的步骤(或操作)进行许多变化。例如，这些步骤可以按不同的顺序执行，或者步骤可以被添加、删除或修改。所有这些变化都被认为是所要求保护的发明的一部分。
虽然已经描述了本发明的优选实施例，但应理解的是，本领域技术人员现在和将来都可以做出落入所附权利要求书的范围内的不同改进和增强。这些权利要求应被解释为保持对首先描述的本发明的适当保护。
已经出于说明的目的呈现了本发明的不同实施例的描述，但并不旨在是穷尽性的或局限于所公开的实施例。在不背离所描述的实施例的范围和精神的情况下，许多修改和变化对本领域的普通技术人员而言将是显而易见的。选择在此使用的术语以最佳地解释实施例的原理、实际应用或在市场上找到的技术上的技术改进，或使得本领域普通技术人员能够理解在此公开的实施例。
本发明可以是任何可能的集成技术细节水平的系统、方法、和/或计算机程序产品。所述计算机程序产品可包含上面具有计算机可读程序指令的计算机可读存储介质(或多个介质)，所述计算机可读程序指令用于致使处理器执行本发明的各方面。
计算机可读存储介质可以是可以保留和存储指令以供指令执行设备使用的有形设备。计算机可读存储介质可以是例如但不限于电子存储设备、磁存储设备、光存储设备、电磁存储设备、半导体存储设备或前述各项的任何合适的组合。计算机可读存储介质的更具体例子的非穷举列表包括以下：便携式计算机盘，硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦除可编程只读存储器(EPROM或闪存)，静态随机存取存储器(SRAM)、便携式致密盘只读存储器(CD-ROM)，数字通用盘(DVD)、记忆棒、软盘、机械编码设备(诸如穿孔卡片)或具有记录在其上的指令的凹槽中的凸起结构)，以及上述的任意合适的组合。如本文中所使用的计算机可读存储介质不应被解释为瞬态信号本身，诸如无线电波或其他自由传播的电磁波、通过波导或其他传输介质传播的电磁波(例如，通过光纤电缆的光脉冲)、或通过导线传输的电信号。
在此所描述的计算机可读程序指令可以从计算机可读存储介质下载到相应的计算/处理设备或经由网络(例如，互联网、局域网、广域网和/或无线网络)下载到外部计算机或外部存储设备。网络可以包括铜传输电缆、光传输光纤、无线传输、路由器、防火墙、交换机、网关计算机和/或边缘服务器。每个计算/处理设备中的网络适配器卡或网络接口从网络接收计算机可读程序指令，并转发计算机可读程序指令以存储在相应计算/处理设备内的计算机可读存储介质中。
用于执行本发明的操作的计算机可读程序指令可以是汇编程序指令，指令集架构(ISA)指令、机器指令、机器相关指令、微代码、固件指令、状态设置数据，集成电路的配置数据，或以一种或多种编程语言的任何组合编写的源代码或目标代码，包括面向对象的Smalltalk、C++等编程语言，以及过程式编程语言，如“C”编程语言或类似的编程语言。计算机可读程序指令可以完全在用户计算机上执行、部分在用户计算机上执行、作为独立软件包执行、部分在用户计算机上部分在远程计算机上执行、或者完全在远程计算机或服务器上执行。在后一种情形中，远程计算机可以通过任何类型的网络(包括局域网(LAN)或广域网(WAN))连接到用户的计算机，或者可以连接到外部计算机(例如，使用互联网服务提供商通过互联网)。在一些实施例中，电子电路(包括例如可编程逻辑电路、现场可编程门阵列(FPGA)或可编程逻辑阵列(PLA))可以通过利用计算机可读程序指令的状态信息来执行计算机可读程序指令以使电子电路个性化，以便执行本发明的各各方面。
在此参照根据本发明的实施例的方法、装置(系统)和计算机程序产品的流程图展示和/或框图描述本发明的多个方面。应当理解，流程图和/或框图的每个方框以及流程图和/或框图中各方框的组合，都可以由计算机可读程序指令来实现。
这些计算机可读程序指令可以被提供给通用计算机的处理器、专用计算机或其他可编程数据处理装置，以产生机器，其通过计算机或其他可编程数据处理装置的处理器执行，创建用于实现在流程图和/或方框图的一个或多个方框中指定的功能/动作的装置。这些计算机可读程序指令还可存储在可指导计算机的计算机可读存储介质中、可编程数据处理装置，和/或以特定方式起作用的其他设备，使得具有存储在其中的指令的计算机可读存储介质包括制品，该制品包括实现流程图和/或框图中的一个或多个方框中规定的功能/动作的各方面的指令。
计算机可读程序指令还可以加载到计算机、其他可编程数据处理装置或其他设备上，或使得一系列操作步骤在计算机、其他可编程装置、或其他装置上执行，以产生计算机实现的过程，使得在计算机，其他可编程装置或其他设备上执行的指令实现流程图和/或框图中的一个或多个方框中规定的功能/动作。
附图中的流程图和框图示出了根据本发明的不同实施例的系统、方法和计算机程序产品的可能实现方式的架构、功能和操作。对此，流程图或框图中的每个方框可以代表模块、段或指令的一部分，其包括用于实现规定的逻辑功能的一个或多个可执行指令。在一些替代实施例中，框中所标注的功能可以不以图中所标注的次序发生。例如，取决于所涉及的功能，连续示出的两个框实际上可以基本上同时执行，或者这些框有时可以以相反的顺序执行。还将注意的是，框图和/或流程图中的每个框、以及框图和/或流程图中的框的组合可以由基于专用硬件的系统来实现，所述基于专用硬件的系统执行指定的功能或动作或执行专用硬件与计算机指令的组合。

Claims (20)

1.一种多裸片集成电路器件，包括：
衬底；
两个或多个裸片，包括实现所述多个裸片的集成电路的功能的部件，其中所述部件包括逻辑门；
间隔件，所述间隔件被布置在所述衬底与所述两个或多个裸片中的每一个裸片之间，其中，所述两个或多个裸片中的每一个裸片与所述衬底进行直接电接触而不与所述间隔件通过所述间隔件中的孔进行直接电接触。
2.如权利要求1所述的器件，其中，所述间隔件包括布线，所述布线用于将所述两个或多个裸片中的一个裸片连接至所述两个或多个裸片中的另一个裸片。
3.如权利要求2所述的器件，其中，所述布线包括多个焊盘，所述多个焊盘用于将所述布线的每个端部电连接至所述两个或多个裸片中的所述一个或另一个裸片。
4.如权利要求1所述的器件，其中，所述间隔件包括机械焊盘，所述机械焊盘用于将所述间隔件机械地连接至所述两个或多个裸片中的一个裸片。
5.如权利要求1所述的器件，其中，所述两个或多个裸片中的每一个裸片经由分别穿过所述间隔件中的所述孔的导电柱与所述衬底电接触。
6.如权利要求5所述的器件，其中，所述导电柱是铜。
7.如权利要求1所述的器件，其中，所述间隔件包括第二组孔，并且将聚合物质分配到所述第二组孔中。
8.如权利要求1所述的器件，其中，所述间隔件包括电容器，并且所述间隔件包括所述电容器上方的氧化物。
9.如权利要求1所述的器件，其中，所述间隔件是硅、玻璃、陶瓷或有机低热膨胀系数(CTE)材料。
10.如权利要求1所述的器件，其中，所述间隔件中的所述孔被钝化。
11.一种制造多裸片集成电路的方法，所述方法包括：
制造包括实现所述多裸片集成电路的功能的部件的两个或多个裸片，其中所述部件包括逻辑门；
制造间隔件并且将所述间隔件布置在衬底与所述两个或多个裸片中的每一个裸片之间，从而使得所述两个或多个裸片中的每一个裸片与所述衬底直接电接触而不与所述间隔件通过所述间隔件中的孔进行直接电接触。
12.如权利要求11所述的方法，其中，制造所述间隔件包括：将引线设置在所述间隔件的与所述两个或多个裸片相同的侧上，以将所述两个或更多个裸片中的一个连接到所述两个或更多个裸片中的另一个。
13.如权利要求12所述的方法，进一步包括设置电焊盘以将所述布线的每个端部电连接至所述两个或更个裸片中的所述一个或另一个裸片。
14.如权利要求11所述的方法，其中，制造所述间隔件包括在所述间隔件的与所述两个或多个裸片相同的侧上设置机械焊盘，以将所述间隔件机械地连接到所述两个或多个裸片中的一个。
15.如权利要求11所述的方法，其中，制造所述间隔件包括：定位所述孔，使得所述两个或多个裸片中的每一个裸片经由分别穿过所述间隔件中的所述孔的导电柱与所述衬底电接触。
16.如权利要求15所述的方法，其中，制造所述间隔件包括将所述孔的尺寸设定成大于所述导电柱的直径。
17.如权利要求11所述的方法，其中，制造所述间隔件包括形成第二组孔。
18.如权利要求11所述的方法，其中，制造所述间隔件包括使用深沟槽形成或金属-绝缘体-金属配置或作为薄膜形成电容器，并且形成所述电容器包括在所述电容器上形成氧化物层。
19.如权利要求11所述的方法，其中，制造所述间隔件包括使用硅、玻璃、陶瓷或有机低热膨胀系数CTE材料作为所述间隔件的材料。
20.如权利要求11所述的方法，其中，制造所述间隔件包括钝化所述间隔件的所述孔。
CN202080023404.6A 2019-03-29 2020-03-18 用于集成电路中的裸片到裸片通信的间隔件 Pending CN113632222A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/369,532 US11031373B2 (en) 2019-03-29 2019-03-29 Spacer for die-to-die communication in an integrated circuit
US16/369,532 2019-03-29
PCT/IB2020/052464 WO2020201872A1 (en) 2019-03-29 2020-03-18 Spacer for die-to-die communication in an integrated circuit

Publications (1)

Publication Number Publication Date
CN113632222A true CN113632222A (zh) 2021-11-09

Family

ID=72604814

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202080023404.6A Pending CN113632222A (zh) 2019-03-29 2020-03-18 用于集成电路中的裸片到裸片通信的间隔件

Country Status (6)

Country Link
US (2) US11031373B2 (zh)
JP (1) JP7386887B2 (zh)
CN (1) CN113632222A (zh)
DE (1) DE112020000571B4 (zh)
GB (1) GB2596693B (zh)
WO (1) WO2020201872A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11031373B2 (en) * 2019-03-29 2021-06-08 International Business Machines Corporation Spacer for die-to-die communication in an integrated circuit
US11201136B2 (en) 2020-03-10 2021-12-14 International Business Machines Corporation High bandwidth module

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5182632A (en) 1989-11-22 1993-01-26 Tactical Fabs, Inc. High density multichip package with interconnect structure and heatsink
US5648890A (en) 1993-07-30 1997-07-15 Sun Microsystems, Inc. Upgradable multi-chip module
JP4581768B2 (ja) 2005-03-16 2010-11-17 ソニー株式会社 半導体装置の製造方法
EP1965615A4 (en) * 2005-12-22 2009-11-11 Murata Manufacturing Co MODULE HAVING AN INTEGRATED COMPONENT AND METHOD FOR MANUFACTURING SUCH A MODULE
US7787254B2 (en) 2006-03-08 2010-08-31 Microelectronics Assembly Technologies, Inc. Thin multichip flex-module
JP4912992B2 (ja) 2007-09-12 2012-04-11 新光電気工業株式会社 キャパシタ内蔵基板及びその製造方法
US8080445B1 (en) 2010-09-07 2011-12-20 Stats Chippac, Ltd. Semiconductor device and method of forming WLP with semiconductor die embedded within penetrable encapsulant between TSV interposers
JP5561190B2 (ja) 2011-01-31 2014-07-30 富士通株式会社 半導体装置、半導体装置の製造方法及び電子装置
CN202423279U (zh) 2011-12-29 2012-09-05 日月光半导体制造股份有限公司 多芯片晶圆级半导体封装构造
US8519543B1 (en) 2012-07-17 2013-08-27 Futurewei Technologies, Inc. Large sized silicon interposers overcoming the reticle area limitations
US9040349B2 (en) 2012-11-15 2015-05-26 Amkor Technology, Inc. Method and system for a semiconductor device package with a die to interposer wafer first bond
US20140151895A1 (en) * 2012-12-05 2014-06-05 Texas Instruments Incorporated Die having through-substrate vias with deformation protected tips
US8957525B2 (en) 2012-12-06 2015-02-17 Texas Instruments Incorporated 3D semiconductor interposer for heterogeneous integration of standard memory and split-architecture processor
US9000490B2 (en) * 2013-04-19 2015-04-07 Xilinx, Inc. Semiconductor package having IC dice and voltage tuners
US10134972B2 (en) * 2015-07-23 2018-11-20 Massachusetts Institute Of Technology Qubit and coupler circuit structures and coupling techniques
CN205621722U (zh) 2016-02-19 2016-10-05 茂丞科技股份有限公司 指纹感测模组
US10943869B2 (en) * 2017-06-09 2021-03-09 Apple Inc. High density interconnection using fanout interposer chiplet
US11538758B2 (en) * 2018-03-19 2022-12-27 Intel Corporation Waveguide interconnect bridges
US11031373B2 (en) 2019-03-29 2021-06-08 International Business Machines Corporation Spacer for die-to-die communication in an integrated circuit

Also Published As

Publication number Publication date
DE112020000571B4 (de) 2022-03-17
GB2596693B (en) 2023-07-19
GB2596693A (en) 2022-01-05
US20210175207A1 (en) 2021-06-10
DE112020000571T5 (de) 2021-10-28
US11031373B2 (en) 2021-06-08
US20200312812A1 (en) 2020-10-01
JP7386887B2 (ja) 2023-11-27
JP2022525367A (ja) 2022-05-12
GB202114025D0 (en) 2021-11-17
US11521952B2 (en) 2022-12-06
WO2020201872A1 (en) 2020-10-08

Similar Documents

Publication Publication Date Title
KR102541861B1 (ko) 리소-에칭가능 층에 브리지를 포함하는 통합 디바이스 패키지
TWI732123B (zh) 具有打線結合的多晶粒堆疊的積體電路封裝
US8236606B2 (en) Method and system for providing a low-profile semiconductor assembly
US10586780B2 (en) Semiconductor device modules including a die electrically connected to posts and related methods
US20130154112A1 (en) Method for Forming Isolation Trenches in Micro-Bump Interconnect Structures and Devices Obtained Thereof
CN109599380A (zh) 具有坝体结构的中介层上管芯组件及其制造方法
US11521952B2 (en) Spacer for die-to-die communication in an integrated circuit and method for fabricating the same
JP2018530160A (ja) 集積回路（ＩＣ）パッケージの間にギャップコントローラを備えるパッケージオンパッケージ（ＰｏＰ）デバイス
TW201803073A (zh) 電氣互連橋接技術
TW201705401A (zh) 多層封裝技術
JP2021093516A (ja) 集積回路パッケージのためのコンポジットブリッジダイツーダイ相互接続
US20150108642A1 (en) Structure to prevent solder extrusion
KR101697421B1 (ko) 집적 회로 패키지
US9490225B2 (en) Package structure and fabrication method thereof
JP2009141092A (ja) 半導体装置を実装した回路装置及びこれに用いる半導体装置の製造方法
US11756911B2 (en) Metal pad modification
US20140145348A1 (en) Rf (radio frequency) module and method of maufacturing the same
DE102020103504A1 (de) Strukturierbare Die-Anbringungs-Materialien und Strukturierungsprozesse
US8492267B1 (en) Pillar interconnect chip to package and global wiring structure
US11735529B2 (en) Side pad anchored by next adjacent via
JP2018152537A (ja) 半導体装置および半導体装置の製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination