CN113629148A - 一种双栅极增强型氧化镓mesfet器件及其制作方法 - Google Patents
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Abstract
本发明公开了一种双栅极增强型氧化镓MESFET器件，包括衬底，衬底底部固定有漏极电极，衬底顶部两侧凹陷形成凹槽，凹槽底部固定有双栅极电极；两个凹槽之间为鳍型结构，鳍型结构顶部固定有源极电极。本发明使用Ga2O3作为晶圆衬底材料制作氧化镓垂直型MESFET，并结合鳍型结构形成鳍型Ga2O3MESFET，通过优化器件结构获得高击穿电压的长关型器件，实现高击穿电压的增强型Ga2O3MESFET。
Description
技术领域
本发明属于机械领域，尤其涉及一种双栅极增强型氧化镓MESFET器件及方法。
背景技术
21世纪以来，电力电子技术已得到了长久的发展，在电力系统、新能源、通信、计算机系统、航空航天等领域有着广泛的应用。电力电子技术的发展对于推动我国建设新型节约型和可持续型发展社会具有重要作用。自上个世纪50年代以来，以硅(Si)为基础的功率器件已广泛的应用到我们日常生活中。然而，由于材料本身限制，对于一些领域如远洋运输、超高压电能传输、机车牵引系统、太空探索、深井勘探等已无法满足要求。此外，硅基功率器件在阻断电压、导通电阻、导通压降上已经接近其理论极限，在高功率密度、高频、高效的要求下，已凸显出其本身的局限性。在新基建时代下，新型基建产业如5G基站、新能源汽车、特高压、人工智能、物联网、大数据、轨道交通将得到迅速发展，这将为电力电子相关产业带来空前的发展机遇。以第三代半导体材料碳化硅(SiC)和氮化镓(GaN)为核心的功率器件在晶圆生长、工艺制备上已相对成熟，近些年已逐渐投入到市场中。
第四代宽禁带半导体材料氧化镓(Ga2O3)，相对于第三代半导体材料(SiC，GaN)来说，具有更宽的禁带宽度，更高的理论击穿电场，更好的抗辐射能力，在高温高压领域有着更为广泛的应用。Ga2O3具有4.7-4.9eV的禁带宽度(SiC 3.25eV，GaN 3.4eV)，高达8MV/cm的理论击穿电场，3444的巴利伽优值(约是碳化硅的10倍，氮化镓的4倍)，Ga2O3还具有其在GHz区域高频切换期间低功率损耗的潜力。这些优异的性能极大的促进了Ga2O3在下一代功率器件中的应用。而推动Ga2O3基功率器件快速发展的另一个重要的因素是氧化镓能以经济的熔体法生长，得到大面积和高质量的单晶衬底，器件的制备工艺也和Si基功率器件相兼容，这也是SiC、GaN、Diamond等半导体材料目前存在的问题，这在一定程度上严重限制了他们的产业化。因此，对于Ga2O3功率器件的研究受到了世界各国政府、企业和研究机构的重视。目前n型有效掺杂的β-Ga2O3技术已经较为成熟，通过Sn、Si、Ge、Mg等精确掺杂可以实现1016-1019cm-3的n型有效掺杂浓度，但是p型有效掺杂还暂未实现，所以目前研究人员进行研究的氧化镓功率器件主要是肖特基势垒二极管(SBD)、金属半导体场效应晶体管(MESFET)、金属氧化物半导体场效应晶体管(MOSFET)等功率器件。MESFET是一种在结构上与结型场效应管类似但未使用PN结作为其栅极，而是采用金属与半导体接触形成肖特基结的方式构成栅极进行栅控。金属半导体场效应管通常由化合物半导体构成，它的速度比由硅制造的结型场效应管或MOSFET更快，但是造价相对更高。MESFET的工作频率一般较高，最高可以达到45GHz，在微波频段的通信、雷达等设备中有着广泛应用。Si MESFET由于本身材料及结构限制，在远洋运输、超高压电能传输、机车牵引系统、太空探索、深井勘探等高温高压高频的复杂应用领域下无法很好的实现器件性能，具有较大的局限性；其次Ga2O3MESFET器件只有n型有效掺杂，对于实现增强型器件具有一定的难度。
发明内容
为解决上述问题，本发明提供了一种双栅极增强型氧化镓MESFET器件及其制作方法。本发明使用Ga2O3作为晶圆衬底材料制作氧化镓垂直型MESFET，并结合鳍型结构形成鳍型Ga2O3 MESFET，通过优化器件结构获得高击穿电压的长关型器件，实现高击穿电压的增强型Ga2O3 MESFET。
为达到上述技术效果，本发明的技术方案是：
一种双栅极增强型氧化镓MESFET器件，包括衬底1，衬底1底部固定有漏极电极2，衬底1顶部两侧凹陷形成凹槽3，凹槽3底部和/或侧壁固定有双栅极电极4；两个凹槽3之间为鳍型结构5，鳍型结构5顶部固定有源极电极6。
进一步的改进，所述衬底1包括处于下层的衬底区域7和处于上层的外延区域8，衬底区域7为采用2x1018cm-3掺杂浓度的Sn掺杂形成的n型高掺杂衬底区域；外延区域8为采用6x1015cm-3-2x1016cm掺杂浓度的Si掺杂形成的n型低掺杂区域。
进一步的改进，所述鳍型结构5为垂直鳍型结构。
进一步的改进，所述衬底1为Ga2O3外延片制作形成。
进一步的改进，所述鳍型结构5的宽度为0.6-1.6μm。
进一步的改进，所述鳍型结构5的的长度为0.6-1.6μm。
进一步的改进，所述双栅极电极4由Pt金属制成。
一种双栅极增强型氧化镓MESFET器件的制作方法，包括如下步骤：
步骤一、使用Ga2O3外延片作为衬底1，衬底1包括外延区域8和衬底区域7；外延区域8处于衬底区域7正上方；
步骤二、在外延区域8顶部做双边刻蚀形成两个凹槽3，两个凹槽3之间形成鳍型结构5；
步骤三、在两个凹槽3底部沉积金属形成双栅极电极4，在鳍型结构5顶部沉积金属形成源极电极6，衬底区域7底部沉积金属形成漏极电极2。
进一步的改进，所述衬底区域7为采用2x1018cm-3掺杂浓度的Sn掺杂形成的n型高掺杂衬底区域；外延区域8为采用6x1015cm-3-2x1016cm掺杂浓度的Si掺杂形成的n型低掺杂区域。
本发明的优点如下：
本发明使用Ga2O3作为晶圆衬底材料制作氧化镓垂直型MESFET，并结合鳍型结构形成鳍型Ga2O3 MESFET，通过优化器件结构实现长关型器件并提高器件击穿电压，实现高击穿电压的增强型Ga2O3 MESFET。
附图说明
图1为双栅极增强型氧化镓MESFET器件的结构示意图；
图2为鳍型结构宽度与外延层掺杂浓度对阈值电压的影响图；
图3为鳍型结构宽度分别为0.6、0.8和1.0μm时外延区域掺杂浓度变化的Id-Vd、Id-Vg曲线图；
图4为为鳍型结构宽度分别为1.2、1.4和1.6μm时外延区域掺杂浓度变化的Id-Vd、Id-Vg曲线图。
具体实施方式
以下通过具体实施方式并且结合附图对本发明的技术方案作具体说明。
实施例1
器件基本结构如图1所示，使用Ga2O3外延片作为器件材料，使用2x1018cm-3的n型掺杂衬底，6x1015cm-3的n型掺杂外延层，衬底背部是漏极电极，背部漏极电极形成欧姆接触结构，顶部进行双边刻蚀，中间未被刻蚀部分形成垂直鳍型结构，鳍型结构顶部生长金属形成源极电极，鳍型结构双边凹槽沉积金属形成双栅极电极。
衬底区域：采用2x1018cm-3掺杂浓度的Sn掺杂形成的n型高掺杂衬底区域。
外延区域：采用6x1015cm-3掺杂浓度的Si掺杂形成的n型低掺杂区域，低掺杂浓度有利于提高器件击穿电压，结合氧化镓本身宽禁带材料的优势，充分发挥器件耐高压性能，使其可以运用于高压高功率的复杂环境。
鳍型(fin)结构区域：对外延层顶部进行一系列的刻蚀工艺步骤，可以刻蚀掉鳍型结构两边外延层形成凹槽，保留垂直鳍型结构区域，用于形成沟道，便于使用栅极控制器件开启与关闭。
底部漏极：生长金属形成漏极电极，形成低电阻欧姆接触以获得良好的导通性能，降低器件导通功耗。
顶部源极：生长金属形成顶部源极，获得具有低电阻的欧姆接触，以获得良好的导通性能，降低导通功耗。
双栅极：鳍型结构左右两边的半凹槽区域生长金属形成肖特基接触，形成栅极控制，控制器件的关断与开启。
器件建模与仿真：
使用半导体工艺模拟及器件模拟工具TCAD软件建立垂直鳍型Ga2O3 MESFET器件结构，设置相应的材料参数模型及物理模型，进行相应的电学性能表征。使用TCAD软件模型建立工具建立器件结构，建立底部衬底区域，外延层区域，顶部鳍型结构区域为氧化镓材料区域，并设置形成相应的漏极电极、源极电极、栅极电极，分别对衬底区域、外延层区域、鳍型结构区域进行n型掺杂形成有效的n型掺杂区域，建立整个器件结构的网格方便下一步的求解。器件模型建立后使用仿真求解工具添加氧化镓材料参数模型，进行电学特性仿真，在仿真求解工具中设置栅极金属特性，器件仿真所需物理模型，数学求解模型及方法，并设置相应的求解方法、步骤以获得相应的输出曲线及特性转移曲线及物理参数。仿真过程中结合相应的结构参数对应的电学性能及其提取的参数修改器件对应的结构参数，形成反馈优化器件结构，提升器件的电学性能，已实现较高耐压的增强型氧化镓MESFET。其次使用数据提取工具对器件进行电学特性曲线进行数据提取，对所提取数据进行分析研究，参数提取，进一步研究鳍型氧化镓MESFET器件的性能。
(1)鳍型结构宽度的设置，设置外延层掺杂浓度为6x1015cm-3，沟道长度为1.6μm，选取0.6、0.8、1.0、1.2、1.4、1.6μm的鳍型结构宽度，可以得到0.6μm的鳍型结构宽度阈值电压为+0.52V，实现的器件长关状态，随着鳍型结构沟槽宽度的增加，阈值电压从+0.52V逐渐下降，鳍型结构沟槽宽度为1.6μm时阈值电压可以达到-3.3V，实现了从长关到长开型器件的转变。
(2)外延层掺杂浓度的设置，设置鳍型结构沟槽宽度为0.6μm，沟道长度为1.6μm，选取外延层掺杂浓度从6×1015-2×1016cm-3变化，实现阈值电压从+0.6V逐渐下降到-0.32V，但饱和导通电流增加了20倍以上，说明了外延层掺杂浓度的改变对于器件电学性能的影响较大，掺杂浓度的降低可以增大器件的正向阈值电压，掺杂浓度的提高可以增大器件的饱和导通电流。
(3)鳍型侧壁沟道长度的设置，沟道长度的变化会影响沟道电阻，影响器件的导通性能及栅控能力，通过设置鳍型结构沟槽宽度为0.6μm，外延层掺杂浓度从6×1015cm-3，沟道长度从0.6-1.6μm，步长0.2μm变化，器件的电学性能随着改变。
(4)栅极金属的设置，栅极设置铂(Pt)、钯(Pd)、金(Au)、镍(Ni)、铜(Cu)五种金属材料，由于不同的金属本身材料性质不同，可以得到不同的器件电学性能，栅极金属的功函数会影响肖特基势垒高度，进而影响MESFET的栅控能力，在鳍型结构沟槽宽度为0.6μm，外延层掺杂浓度从6×1015cm-3，沟道长度1.6μm情况下，使用Pt金属作为栅极时可以使器件的阈值电压为+0.5V，实现器件常闭状态，使得器件成为增强型MESFET。
(5)外延层厚度的设置，对于垂直型器件，可以通过设置调节外延层厚度改变器件的击穿电压及导通性能。
上述仅为本发明的一个具体导向实施方式，但本发明的设计构思并不局限于此，凡利用此构思对本发明进行非实质性的改动，均应属于侵犯本发明的保护范围的行为。
Claims (9)
1.一种双栅极增强型氧化镓MESFET器件，其特征在于，包括衬底(1)，衬底(1)底部固定有漏极电极(2)，衬底(1)顶部两侧凹陷形成凹槽(3)，凹槽(3)底部和/或侧壁固定有双栅极电极(4)；两个凹槽(3)之间为鳍型结构(5)，鳍型结构(5)顶部固定有源极电极(6)。
2.如权利要求1所述的双栅极增强型氧化镓MESFET器件，其特征在于，所述衬底(1)包括处于下层的衬底区域(7)和处于上层的外延区域(8)，衬底区域(7)为采用2x1018cm-3掺杂浓度的Sn掺杂形成的n型高掺杂衬底区域；外延区域(8)为采用6x1015cm-3-2x1016cm掺杂浓度的Si掺杂形成的n型低掺杂区域。
3.如权利要求1所述的双栅极增强型氧化镓MESFET器件，其特征在于，所述鳍型结构(5)为垂直鳍型结构。
4.如权利要求1所述的双栅极增强型氧化镓MESFET器件，其特征在于，所述衬底(1)为Ga2O3外延片制作形成。
5.如权利要求1所述的双栅极增强型氧化镓MESFET器件，其特征在于，所述鳍型结构(5)的宽度为0.6-1.6μm。
6.如权利要求1所述的双栅极增强型氧化镓MESFET器件，其特征在于，所述鳍型结构(5)的长度为0.6-1.6μm。
7.如权利要求1所述的双栅极增强型氧化镓MESFET器件，其特征在于，所述双栅极电极(4)由Pt金属制成。
8.一种双栅极增强型氧化镓MESFET器件的制作方法，其特征在于，包括如下步骤：
步骤一、使用Ga2O3外延片作为衬底(1)，衬底(1)包括外延区域(8)和衬底区域(7)；外延区域(8)处于衬底区域(7)正上方；
步骤二、在外延区域(8)顶部做双边刻蚀形成两个凹槽(3)，两个凹槽(3)之间形成鳍型结构(5)；
步骤三、在两个凹槽(3)底部沉积金属形成双栅极电极(4)，在鳍型结构(5)顶部沉积金属形成源极电极(6)，衬底区域(7)底部沉积金属形成漏极电极(2)。
9.如权利要求8所述的双栅极增强型氧化镓MESFET器件的制作方法，其特征在于，所述衬底区域(7)为采用2x1018cm-3掺杂浓度的Sn掺杂形成的n型高掺杂衬底区域；外延区域(8)为采用6x1015cm-3-2x1016cm掺杂浓度的Si掺杂形成的n型低掺杂区域。
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008021689A (ja) * | 2006-07-11 | 2008-01-31 | Fuji Electric Device Technology Co Ltd | 半導体装置 |
| US20100163935A1 (en) * | 2008-12-22 | 2010-07-01 | Renesas Technology Corp. | Semiconductor device and method of manufacturing the same |
| US20140217469A1 (en) * | 2011-09-08 | 2014-08-07 | National Institute of Information and Communicatio Technology | Ga2O3 SEMICONDUCTOR ELEMENT |
| CN105097896A (zh) * | 2014-05-08 | 2015-11-25 | Flosfia株式会社 | 结晶性层叠结构体以及半导体装置 |
| US20170288061A1 (en) * | 2014-08-29 | 2017-10-05 | Tamura Corporation | Semiconductor element and production method for same |
| US20180240873A1 (en) * | 2017-02-21 | 2018-08-23 | International Business Machines Corporation | Techniques for VFET Top Source/Drain Epitaxy |
| US10103147B1 (en) * | 2017-05-01 | 2018-10-16 | International Business Machines Corporation | Vertical transport transistors with equal gate stack thicknesses |
| CN110571275A (zh) * | 2019-09-17 | 2019-12-13 | 中国科学技术大学 | 氧化镓mosfet的制备方法 |
| US20210013314A1 (en) * | 2018-03-28 | 2021-01-14 | Cornell University | Vertical gallium oxide (ga2o3) power fets |
-
2021
- 2021-06-24 CN CN202110706987.9A patent/CN113629148A/zh active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008021689A (ja) * | 2006-07-11 | 2008-01-31 | Fuji Electric Device Technology Co Ltd | 半導体装置 |
| US20100163935A1 (en) * | 2008-12-22 | 2010-07-01 | Renesas Technology Corp. | Semiconductor device and method of manufacturing the same |
| US20140217469A1 (en) * | 2011-09-08 | 2014-08-07 | National Institute of Information and Communicatio Technology | Ga2O3 SEMICONDUCTOR ELEMENT |
| CN105097896A (zh) * | 2014-05-08 | 2015-11-25 | Flosfia株式会社 | 结晶性层叠结构体以及半导体装置 |
| US20170288061A1 (en) * | 2014-08-29 | 2017-10-05 | Tamura Corporation | Semiconductor element and production method for same |
| US20180240873A1 (en) * | 2017-02-21 | 2018-08-23 | International Business Machines Corporation | Techniques for VFET Top Source/Drain Epitaxy |
| US10103147B1 (en) * | 2017-05-01 | 2018-10-16 | International Business Machines Corporation | Vertical transport transistors with equal gate stack thicknesses |
| US20210013314A1 (en) * | 2018-03-28 | 2021-01-14 | Cornell University | Vertical gallium oxide (ga2o3) power fets |
| CN110571275A (zh) * | 2019-09-17 | 2019-12-13 | 中国科学技术大学 | 氧化镓mosfet的制备方法 |
Non-Patent Citations (2)
| Title |
|---|
| 施敏: "半导体器件物理与工艺", 苏州大学出版社, pages: 234 * |
| 翟东媛 等: "High performance trench MOS barrier Schottky diode with high-k gate oxide", CHINESE PHYSICS B, vol. 24, no. 7, pages 077201 - 1 * |
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