CN113555354B - 一种集成sbd的沟槽终端结构及其制备方法 - Google Patents
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Abstract
本发明公开了一种集成SBD的沟槽终端结构及其制备方法，涉及半导体的技术领域，旨在解决现有技术中SBD结构占用大量硅表面面积，导致芯片面积大、成本高且工艺控制难度较大的问题。其技术方案要点是在元胞区设置第一类沟槽，在终端区环绕元胞区设置有截止环结构，在终端区设置有位于第一类沟槽和截止环结构之间的若干个第二类沟槽，位于N型外延层顶部设置有位于相邻的至少两个第二类沟槽之间的肖特基结构，肖特基结构包括有同时跨越至少两个第二类沟槽的金属条，金属条底壁向下延伸出嵌入对应第二类沟槽的突出部，金属条与N型外延层形成肖特基接触，金属条与源极金属电气连接。本发明达到了节约芯片面积、工艺简单、降低成本的效果。
Description
技术领域
本发明涉及半导体的技术领域，尤其是涉及一种集成SBD的沟槽终端结构及其制备方法。
背景技术
常规沟槽功率器件MOSFET在应用中存在开关损耗过大的问题，尤其在高频同步整流应用中劣势更加明显，主要是寄生二极管的Trr(Internal diode reverse recoverytime，反向恢复时间)和Irr(Internal diode peak reverse recovery current，反向恢复电流)偏大导致。
现有技术通过在芯片有源区内集成SBD(Schottky Barrier Diode，肖特基二极管)来降低Trr和Irr，参考美国专利US7564097、US6921957、US7816732等。现有技术在集成沟槽MOSFET和SBD的方式上，均是通过在有源区内单独划分一个区域或者两者交替排列的方式，实现沟槽MOSFET和SBD结构的集成。
但是，上述技术存在以下问题：1、SBD结构占用大量硅表面面积，导致芯片面积大，成本高，会占用有源区面积，工艺控制难度较大。2、工艺流程复杂，制造成本高。
发明内容
本发明的目的是提供一种集成SBD的沟槽终端结构及其制备方法，其具有节约芯片面积、工艺简单、降低成本的效果。
本发明的上述发明目的是通过以下技术方案得以实现的：
一种集成SBD的沟槽终端结构，包括半导体基板，所述半导体基板被划分为元胞区和终端区，所述元胞区位于半导体基板的中心区并设置有源极金属，所述终端区位于元胞区的外圈且环绕元胞区，所述半导体基板包括有N型衬底和位于N型衬底上的N型外延层，在所述元胞区设置有第一类沟槽，在所述终端区环绕元胞区的外围设置有截止环结构，在所述终端区设置有位于第一类沟槽和截止环结构之间的若干个第二类沟槽，所述第二类沟槽的底壁和侧壁上均形成有有栅介质层，所述第二类沟槽内设置有导电多晶硅；
位于所述N型外延层顶部设置有位于相邻的至少两个第二类沟槽之间的肖特基结构，所述肖特基结构包括有同时跨越至少两个第二类沟槽的金属条，所述金属条底壁向下延伸出嵌入对应第二类沟槽的突出部，所述金属条与N型外延层形成肖特基接触，所述金属条与源极金属电气连接；金属条覆盖范围外的相邻第二类沟槽间空间形成P阱。
本发明进一步设置为：所述第二类沟槽设有四个，距所述元胞区最近的两个第二类沟槽构成的空间设有肖特基结构，远离所述元胞区的三个第二类沟槽之间构成的两个空间形成P阱。
本发明进一步设置为：所述第二类沟槽设有四个，距所述元胞区最近和最远的两个第二类沟槽分别与各自相邻第二类沟槽构成两个空间形成P阱，位于中间的两个所述第二类沟槽之间构成的空间设有肖特基结构。
本发明进一步设置为：所述第二类沟槽设有四个，距所述元胞区最近的三个第二类沟槽构成的两个空间均设有肖特基结构，远离所述元胞区的两个第二类沟槽之间构成的空间形成P阱。
本发明进一步设置为：相邻所述第二类沟槽间距离相同。
本发明进一步设置为：所述金属条的材质下层为钛，上层为铝。
本发明进一步设置为：所述半导体基板顶部表面除肖特基接触面外均设有绝缘介质层。
本发明进一步设置为：所述第一类沟槽和第二类沟槽之间设有P阱，所述源极金属下方、P阱上方设有N+区。
本发明的上述发明目的二是通过以下技术方案得以实现的：
一种集成SBD的沟槽终端结构制备方法，包括以下步骤：
S1、衬底材料准备：衬底采用N型(100)晶向，掺杂砷元素或磷元素，电阻率在0.001-0.05Ω·cm范围内，在衬底做外延生长，所生长的外延电阻率和厚度根据器件的耐压要求确定；
S2、沟槽刻蚀：圆片表面淀积一层SiO2，沟槽光刻、刻蚀形成沟槽结构，沟槽结构深度0.6-2um，宽度0.2-1.2um，倾斜角度89度；
S3、牺牲氧化生长：在沟槽侧壁通过干法氧化形成一层厚度500-2000埃氧化层，氧化温度1000-1100℃，再利用湿法漂洗去除所有氧化层，修复沟槽刻蚀损伤，并使沟槽底部圆滑；
S4、栅介质层形成：在沟槽侧壁生长一层厚度500-1000埃的氧化层，生长温度950℃-1050℃，温度随氧化层厚度增大而升高；
S5、多晶栅形成：多晶经过淀积、光刻、刻蚀处理，多晶厚度0.8-1.2um，多晶掺杂浓度1E19-6E19，掺杂元素为磷；
S6、P阱和N+区形成：在肖特基结构区域用光刻胶遮挡，在芯片表面注入硼元素，能量60KEV～120Kev，高温退火形成P阱，退火条件1100℃/60min，采用双注入提高P阱掺杂浓度的均匀性；通过光刻、注入、退火形成N+区，注入元素为砷元素，能量60KeV，退火条件950℃/60min；
S7、绝缘介质层淀积、孔刻蚀：淀积一层厚度8000-12000埃的氧化层，在氧化层中掺入一定比例的硼元素和磷元素，吸收可动Na、K离子；在氧化层通过光刻、刻蚀形成孔，孔深度为0.3-0.45um；
S8、孔注入、填充：孔注入、退火，降低接触电阻，注入元素为BF2或B，剂量为2E14-5E14，能量30-40KeV，快速退火，退火条件950℃/30s；在接触孔中淀积Ti或TiN层并填充钨金属，形成欧姆接触孔；
S9、SBD接触区形成：通过光刻、ILD刻蚀，形成SBD接触区，继续淀积金属钛，快速退火，退火条件800℃/30s,形成肖特基势垒；在ILD刻蚀时，需刻蚀至Si层；
S10、金属淀积、刻蚀：沉积厚度为4um金属铝，铝中掺杂一定比例的SiCu，防止铝硅互溶，然后光刻腐蚀铝；
S11、钝化层沉积，钝化层光刻，腐蚀：沉积钝化层氮化硅7000-12000埃，然后光刻腐蚀，形成源极和栅极的开口区；
S12、背面Ti-Ni-Ag：减薄圆片背面到150um左右，在背面蒸镀Ti-Ni-Ag合金。
综上所述，本发明的有益技术效果为：
通过引入肖特基势，可优化沟槽终端的电势分布，显著增加耗尽面积，提高终端耐压能力，同时将肖特基结构设置在两个第二类沟槽之间，不影响有源区的过流面积，节约芯片面积，降低成本。在芯片面积不变的情况下，SBD的线宽可以做得更大，工艺简单，降低了制造成本。
附图说明
图1是现有技术中的沟槽终端结构的整体结构示意图；
图2是现有技术中沟槽终端结构耐压时的终端区域电势分布图；
图3是本发明的俯视图；
图4是本发明沿图3的虚线AA’截得实施例一的结构示意图；
图5是本发明沿图3的虚线AA’截得实施例二的结构示意图；
图6是本发明沿图3的虚线AA’截得实施例三的结构示意图；
图7是本发明实施例一耐压时的终端区域电势分布图。
图中，01、元胞区；02、终端区；1、源极金属；11、第一类沟槽；2、栅极；3、肖特基结构；31、金属条；32、突出部；33、第二类沟槽；34、栅介质层；35、导电多晶硅；36、绝缘介质层；4、截止环结构；5、P阱；6、N+区；7、N型衬底；71、N型外延层。
具体实施方式
实施例一
参照图3和图4，本发明公开了一种集成SBD的沟槽终端结构，包括半导体基板，半导体基板被划分为元胞区01和终端区02，元胞区01位于半导体基板的中心区并设置有源极金属1，终端区02位于元胞区01的外圈且环绕元胞区01，半导体基板包括有N型衬底7和位于N型衬底7上的N型外延层71，在元胞区01设置有第一类沟槽11，在终端区02环绕元胞区01的外围设置有截止环结构4，在终端区02设置有位于第一类沟槽11和截止环结构4之间的若干个第二类沟槽33，第二类沟槽33的底壁和侧壁上均形成有有栅介质层34，第二类沟槽33内设置有导电多晶硅35；
位于N型外延层71顶部设置有位于相邻的至少两个第二类沟槽33之间的肖特基结构3，肖特基结构3包括有同时跨越至少两个第二类沟槽33的金属条31，金属条31的下层为钛，上层为铝。金属条31底壁向下延伸出嵌入对应第二类沟槽33的突出部32，金属条31与N型外延层71形成肖特基接触，金属条31与源极金属1电气连接；金属条31覆盖范围外的相邻第二类沟槽33间空间形成P阱5。
在本实施例中，第二类沟槽33设有四个，距元胞区01最近的两个第二类沟槽33构成的空间设有肖特基结构3，远离元胞区01的三个第二类沟槽33之间构成的两个空间形成P阱5。相邻第二类沟槽33间距离相同。
半导体基板顶部表面除肖特基接触面外均设有绝缘介质层36。
第一类沟槽11和第二类沟槽33之间设有P阱5，源极金属1下方、P阱5上方设有N+区。
实施例1从仿真结果来看(如图7)，MOSFET反向截止除了主结承担耐压以外，两第二沟槽间由于肖特基势垒的存在，也会分担部分电压，相比普通沟槽终端结构(如图1和图2)，击穿电压更高；从正向导通到关断时，集成在终端位置的SBD结构，可大幅度降低寄生二极管的反向恢复时间，提高开关频率，降低开关损耗。
实施例二
参照图5，本发明公开了一种集成SBD的沟槽终端结构，本实施例与实施例一的区别在于，第二类沟槽33设有四个，距元胞区01最近和最远的两个第二类沟槽33分别与各自相邻第二类沟槽33构成两个空间形成P阱5，位于中间的两个第二类沟槽33之间构成的空间设有肖特基结构3。本实施例与实施例一的原理相同，并达到与实施例一相同的技术效果。
实施例三
参照图6，本发明公开了一种集成SBD的沟槽终端结构，本实施例与实施例一的区别在于，第二类沟槽33设有四个，距元胞区01最近的三个第二类沟槽33构成的两个空间均设有肖特基结构3，远离元胞区01的两个第二类沟槽33之间构成的空间形成P阱5。本实施例与实施例一的原理相同，并达到与实施例一相同的技术效果。
实施例四
本发明公开了一种适用于实施例一至三所公开集成SBD的沟槽终端结构的制备方法，包括以下步骤：
S1、衬底材料准备：衬底采用N型(100)晶向，掺杂砷元素或磷元素，电阻率在0.001-0.05Ω·cm范围内，在衬底做外延生长，所生长的外延电阻率和厚度根据器件的耐压要求确定；
S2、沟槽刻蚀：圆片表面淀积一层SiO2，沟槽光刻、刻蚀形成沟槽结构，沟槽结构深度0.6-2um，宽度0.2-1.2um，倾斜角度89度；
S3、牺牲氧化生长：在沟槽侧壁通过干法氧化形成一层厚度500-2000埃氧化层，氧化温度1000-1100℃，再利用湿法漂洗去除所有氧化层，修复沟槽刻蚀损伤，并使沟槽底部圆滑；
S4、栅介质层34形成：在沟槽侧壁生长一层厚度500-1000埃的氧化层，生长温度950℃-1050℃，温度随氧化层厚度增大而升高；
S5、多晶栅形成：多晶经过淀积、光刻、刻蚀处理，多晶厚度0.8-1.2um，多晶掺杂浓度1E19-6E19，掺杂元素为磷；
S6、P阱5和N+区形成：在肖特基结构3区域用光刻胶遮挡，在芯片表面注入硼元素，能量60KEV～120Kev，高温退火形成P阱5，退火条件1100℃/60min，采用双注入提高P阱5掺杂浓度的均匀性；通过光刻、注入、退火形成N+区，注入元素为砷元素，能量60KeV，退火条件950℃/60min；
S7、绝缘介质层36淀积、孔刻蚀：淀积一层厚度8000-12000埃的氧化层，在氧化层中掺入一定比例的硼元素和磷元素，吸收可动Na、K离子，提高器件可靠性；在氧化层通过光刻、刻蚀形成孔，孔深度为0.3-0.45um；
S8、孔注入、填充：孔注入、退火，降低接触电阻，注入元素为BF2或B，剂量为2E14-5E14，能量30-40KeV，快速退火，退火条件950℃/30s；在接触孔中淀积Ti或TiN层并填充钨金属，形成欧姆接触孔；
S9、SBD接触区形成：通过光刻、ILD刻蚀，形成SBD接触区，继续淀积金属钛，快速退火，退火条件800℃/30s,形成肖特基势垒；在ILD刻蚀时，需刻蚀一定厚度至Si层，提高肖特基势垒的稳定性。
S10、金属淀积、刻蚀：沉积厚度为4um金属铝，铝中掺杂一定比例的SiCu，防止铝硅互溶，然后光刻腐蚀铝；
S11、钝化层沉积，钝化层光刻，腐蚀：沉积钝化层氮化硅7000-12000埃，然后光刻腐蚀，形成源极和栅极2的开口区，可降低芯片表面可动离子引起的器件漏电。
S12、背面Ti-Ni-Ag：减薄圆片背面到150um左右，在背面蒸镀Ti-Ni-Ag合金。
本具体实施方式的实施例均为本发明的较佳实施例，并非依此限制本发明的保护范围，故：凡依本发明的结构、形状、原理所做的等效变化，例如，调整第二类沟槽33的数量等，均应涵盖于本发明的保护范围之内。
Claims (9)
1.一种集成SBD的沟槽终端结构，包括半导体基板，所述半导体基板被划分为元胞区(01)和终端区(02)，所述元胞区(01)位于半导体基板的中心区并设置有源极金属(1)，所述终端区(02)位于元胞区(01)的外圈且环绕元胞区(01)，所述半导体基板包括有N型衬底(7)和位于N型衬底(7)上的N型外延层(71)，其特征在于，在所述元胞区(01)设置有第一类沟槽(11)，在所述终端区(02)环绕元胞区(01)的外围设置有截止环结构(4)，在所述终端区(02)设置有位于第一类沟槽(11)和截止环结构(4)之间的若干个第二类沟槽(33)，所述第二类沟槽(33)的底壁和侧壁上均形成有栅介质层(34)，所述第二类沟槽(33)内设置有导电多晶硅(35)；
位于所述N型外延层(71)顶部设置有位于相邻的至少两个第二类沟槽(33)之间的肖特基结构(3)，所述肖特基结构(3)包括有同时跨越至少两个第二类沟槽(33)的金属条(31)，所述金属条(31)底壁向下延伸出嵌入对应第二类沟槽(33)的突出部(32)，所述金属条(31)与N型外延层(71)形成肖特基接触，所述金属条(31)与源极金属(1)电气连接；金属条(31)覆盖范围外的相邻第二类沟槽(33)间空间形成P阱(5)。
2.根据权利要求1所述的一种集成SBD的沟槽终端结构，其特征在于：所述第二类沟槽(33)设有四个，距所述元胞区(01)最近的两个第二类沟槽(33)构成的空间设有肖特基结构(3)，远离所述元胞区(01)的三个第二类沟槽(33)之间构成的两个空间形成P阱(5)。
3.根据权利要求1所述的一种集成SBD的沟槽终端结构，其特征在于：所述第二类沟槽(33)设有四个，距所述元胞区(01)最近和最远的两个第二类沟槽(33)分别与各自相邻第二类沟槽(33)构成两个空间形成P阱(5)，位于中间的两个所述第二类沟槽(33)之间构成的空间设有肖特基结构(3)。
4.根据权利要求3所述的一种集成SBD的沟槽终端结构，其特征在于：所述第二类沟槽(33)设有四个，距所述元胞区(01)最近的三个第二类沟槽(33)构成的两个空间均设有肖特基结构(3)，远离所述元胞区(01)的两个第二类沟槽(33)之间构成的空间形成P阱(5)。
5.根据权利要求1-4任一项权利要求所述的一种集成SBD的沟槽终端结构，其特征在于：相邻所述第二类沟槽(33)间距离相同。
6.根据权利要求5所述的一种集成SBD的沟槽终端结构，其特征在于：所述金属条(31)的材质下层为钛，上层为铝。
7.根据权利要求6所述的一种集成SBD的沟槽终端结构，其特征在于：所述半导体基板顶部表面除肖特基接触面外均设有绝缘介质层(36)。
8.根据权利要求7所述的一种集成SBD的沟槽终端结构，其特征在于：所述第一类沟槽(11)和第二类沟槽(33)之间设有P阱(5)，所述源极金属(1)下方、P阱(5)上方设有N+区。
9.根据权利要求1所述的一种集成SBD的沟槽终端结构制备方法，其特征在于，包括以下步骤：
S1、衬底材料准备：衬底采用N型（100）晶向，掺杂砷元素或磷元素，电阻率在0.001-0.05Ω•cm范围内，在衬底做外延生长，所生长的外延电阻率和厚度根据器件的耐压要求确定；
S2、沟槽刻蚀：圆片表面淀积一层SiO2，沟槽光刻、刻蚀形成沟槽结构，沟槽结构深度0.6-2um，宽度0.2-1.2um，倾斜角度89度；
S3、牺牲氧化生长：在沟槽侧壁通过干法氧化形成一层厚度500-2000埃氧化层，氧化温度1000-1100℃，再利用湿法漂洗去除所有氧化层，修复沟槽刻蚀损伤，并使沟槽底部圆滑；
S4、栅介质层(34)形成：在沟槽侧壁生长一层厚度500-1000埃的氧化层，生长温度950℃-1050℃，温度随氧化层厚度增大而升高；
S5、多晶栅形成：多晶经过淀积、光刻、刻蚀处理，多晶厚度0.8-1.2um，多晶掺杂浓度1E19-6E19，掺杂元素为磷；
S6、P阱(5)和N+区形成：在肖特基结构(3)区域用光刻胶遮挡，在芯片表面注入硼元素，能量60KEV~120Kev，高温退火形成P阱(5)，退火条件1100℃/60min，采用双注入提高P阱(5)掺杂浓度的均匀性；通过光刻、注入、退火形成N+区，注入元素为砷元素，能量60KeV，退火条件950℃/60min；
S7、绝缘介质层(36)淀积、孔刻蚀：淀积一层厚度8000-12000埃的氧化层，在氧化层中掺入一定比例的硼元素和磷元素，吸收可动Na、K离子；在氧化层通过光刻、刻蚀形成孔，孔深度为0.3-0.45um；
S8、孔注入、填充：孔注入、退火，降低接触电阻，注入元素为BF2或B，剂量为2E14-5E14，能量30-40KeV，快速退火，退火条件950℃/30s；在接触孔中淀积Ti或TiN层并填充钨金属，形成欧姆接触孔；
S9、SBD接触区形成：通过光刻、ILD刻蚀，形成SBD接触区，继续淀积金属钛，快速退火，退火条件800℃/30s,形成肖特基势垒； 在ILD刻蚀时，需刻蚀至Si层；
S10、金属淀积、刻蚀：沉积厚度为4um金属铝，铝中掺杂一定比例的SiCu，防止铝硅互溶，然后光刻腐蚀铝；
S11、钝化层沉积，钝化层光刻，腐蚀：沉积钝化层氮化硅 7000-12000埃，然后光刻腐蚀，形成源极和栅极(2)的开口区；
S12、背面Ti-Ni-Ag：减薄圆片背面到150um左右，在背面蒸镀Ti-Ni-Ag合金。
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