CN113497074A - 微型发光二极管显示面板及其制备方法 - Google Patents

微型发光二极管显示面板及其制备方法 Download PDF

Info

Publication number
CN113497074A
CN113497074A CN202010202937.2A CN202010202937A CN113497074A CN 113497074 A CN113497074 A CN 113497074A CN 202010202937 A CN202010202937 A CN 202010202937A CN 113497074 A CN113497074 A CN 113497074A
Authority
CN
China
Prior art keywords
layer
emitting diode
semiconductor layer
light emitting
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010202937.2A
Other languages
English (en)
Inventor
陈右儒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN202010202937.2A priority Critical patent/CN113497074A/zh
Priority to PCT/CN2021/081368 priority patent/WO2021185289A1/zh
Priority to US17/763,645 priority patent/US20220344315A1/en
Publication of CN113497074A publication Critical patent/CN113497074A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09FDISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0093Wafer bonding; Removal of the growth substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68354Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68363Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026Bonding areas specifically adapted for layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05575Plural external layers
    • H01L2224/0558Plural external layers being stacked
    • H01L2224/05583Three-layer coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081Disposition
    • H01L2224/0812Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/085Material
    • H01L2224/08501Material at the bonding interface
    • H01L2224/08502Material at the bonding interface comprising an eutectic alloy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808Bonding techniques
    • H01L2224/80801Soldering or alloying
    • H01L2224/80805Soldering or alloying involving forming a eutectic alloy at the bonding interface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • H01L2224/83805Soldering or alloying involving forming a eutectic alloy at the bonding interface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/95001Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/9512Aligning the plurality of semiconductor or solid-state bodies
    • H01L2224/95136Aligning the plurality of semiconductor or solid-state bodies involving guiding structures, e.g. shape matching, spacers or supporting members
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008Processes
    • H01L2933/0033Processes relating to semiconductor body packages
    • H01L2933/0058Processes relating to semiconductor body packages relating to optical field-shaping elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008Processes
    • H01L2933/0033Processes relating to semiconductor body packages
    • H01L2933/0066Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26Materials of the light emitting region
    • H01L33/30Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58Optical field-shaping elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Led Devices (AREA)
  • Led Device Packages (AREA)

Abstract

本申请实施例提供了一种微型发光二极管显示面板及其制备方法。该制备方法,包括:在衬底基材的一侧制备磊晶层,磊晶层包括第一半导体层、发光材料层、第二半导体层和第一导电层,第一半导体层与衬底基材直接接触,第一导电层为磊晶层中最远离衬底基材的膜层;将磊晶层划分为阵列排布的多个发光二极管晶粒;提供背板,在背板上制作绑定结构;将多个发光二极管晶粒中的至少部分发光二极管晶粒的第一导电层与绑定结构相绑定;将与绑定结构相绑定的发光二极管晶粒从衬底基材剥离。本申请实施例提高了巨量转移的转移效率、转移精度,以及能够实现对垂直电极结构的微型发光二极管晶粒的转移。

Description

微型发光二极管显示面板及其制备方法
技术领域
本申请涉及显示技术领域,具体而言,本申请涉及一种微型发光二极管显示面板及其制备方法。
背景技术
微型发光二极管(Micro LED)显示面板的制备过程中,在磊晶工序结束后,通常需要进行巨量转移。
巨量转移是指,把数百万甚至数千万颗微米级的Micro LED晶粒正确且有效率的移动到电路基板上。以一个4K三色显示器(显示屏分辨率为3840×2160及以上的超高清电视,其分辨率是高清的8倍、全高清的4倍)为例,需要转移的晶粒就高达2400万颗(4000×2000×3),即使一次转移1万颗,也需要重复2400次。
在现有的巨量转移技术中,激光转移以其高可靠性、高产量、高可量测性、高可选择性及高成功率等优势,受到业内欢迎。但目前常用的激光转移存在以下缺陷:需要使用至少一片carrier(粘贴基板或转移基板)做为中转层,转移环节多、配合转移的器件多,转移效率低、转移精度受限;目前只能实现水平电极结构的Micro LED的转移,难以实现垂直电极结构的Micro LED的转移,兼容性不足。
发明内容
本申请针对现有方式的缺点,提出一种微型发光二极管显示面板及其制备方法,用以解决现有技术存在转移效率低、转移精度受限或难以实现水平电极结构的微型发光二极管晶粒转移的技术问题。
第一个方面,本申请实施例提供了一种微型发光二极管显示面板的制备方法,包括:
在衬底基材的一侧制备磊晶层,磊晶层包括第一半导体层、发光材料层、第二半导体层和第一导电层,第一半导体层与衬底基材直接接触,第一导电层为磊晶层中最远离衬底基材的膜层;
将磊晶层划分为阵列排布的多个发光二极管晶粒;
提供背板,在背板上制作绑定结构;
将多个发光二极管晶粒中的至少部分发光二极管晶粒的第一导电层与绑定结构相绑定;
将与绑定结构相绑定的发光二极管晶粒从衬底基材剥离。
第二个方面,本申请实施例提供了一种微型发光二极管显示面板,包括:背板和多个发光二极管晶粒;
多个发光二极管晶粒中的每个发光二极管晶粒包括叠层设置的第一半导体层、发光材料层、第二半导体层和第一导电层;
第一导电层与背板上的绑定结构相绑定;
第二半导体层位于第一导电层远离背板的一侧;
发光材料层位于第二半导体层远离第一导电层的一侧;
第一半导体层位于发光材料层远离第二半导体层的一侧。
本申请实施例提供的微型发光二极管显示面板的制备方法带来的有益技术效果包括:在衬底基材上制备阵列排布的多个垂直电极结构的发光二极管晶粒,采用可选择性剥离,将指定的发光二极管晶粒直接转移到目标背板,即采用一次转移,不需使用作为中转的粘贴基板或转移基板,简化了转移环节,减少了配合转移的器件数量,大大提高了转移效率以及转移精度;制备得到的发光二极管晶粒为垂直电极结构,改善了现有技术只能实现水平电极结构的发光二极管晶粒转移的局限,实现了对垂直电极结构的发光二极管晶粒的转移,提高了巨量转移的兼容性。
本申请实施例提供的微型发光二极管显示面板及显示装置带来的有益技术效果包括:采用垂直电极结构的微型发光二极管,使得电流几乎全部垂直流过微型发光二极管的外延层,极少横向流动的电流,利于电流的扩散以及热量的散发,可满足大功率发展趋势。
本申请附加的方面和优点将在下面的描述中部分给出,这些将从下面的描述中变得明显,或通过本申请的实践了解到。
附图说明
本申请上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解,其中:
图1为本申请实施例提供的一种微型发光二极管显示面板的制备方法的流程示意图;
图2为本申请实施例提供的另一种微型发光二极管显示面板的制备方法的流程示意图;
图3为本申请实施例提供的再一种微型发光二极管显示面板的制备方法的流程示意图;
图4为经过步骤S201在衬底基材的一侧制备磊晶层、步骤S202将磊晶层划分为阵列排布的多个发光二极管晶粒和S203提供背板,在背板上制作绑定结构后,得到的衬底基材以及背板的结构示意图;
图5为经过步骤S204将多个发光二极管晶粒中的至少部分发光二极管晶粒的第一导电层与绑定结构相绑定后,得到的衬底基材与背板的位置关系示意图;
图6为步骤S205将与绑定结构相绑定的发光二极管晶粒从衬底基材剥离中的剥离状态示意图;
图7为本申请实施例提供的经过弧面化的激光烧蚀得到的发光二极管晶粒的结构示意图;
图8为本申请实施例提供的一种微型发光二极管显示面板的俯视结构示意图;
图9为图8中Z-Z面的一种截面结构示意图。
其中:
100-背板;110-绑定结构;120-驱动器件;
200-衬底基材;
300-发光二极管晶粒;310-第一导电层;320-第二半导体层;330-发光材料层;340-第一半导体层;340a-弧面;350-顶电极层;350a-弧形区域;360-第二电极图案;
400-掩膜板。
具体实施方式
下面详细描述本申请,本申请的实施例的示例在附图中示出,其中自始至终相同或类似的标号表示相同或类似的部件或具有相同或类似功能的部件。此外,如果已知技术的详细描述对于示出的本申请的特征是不必要的,则将其省略。下面通过参考附图描述的实施例是示例性的,仅用于解释本申请,而不能解释为对本申请的限制。
本技术领域技术人员可以理解,除非另外定义,这里使用的所有术语(包括技术术语和科学术语),具有与本申请所属领域中的普通技术人员的一般理解相同的意义。还应该理解的是,诸如通用字典中定义的那些术语,应该被理解为具有与现有技术的上下文中的意义一致的意义,并且除非像这里一样被特定定义,否则不会用理想化或过于正式的含义来解释。
本技术领域技术人员可以理解,除非特意声明,这里使用的单数形式“一”、“一个”、“所述”和“该”也可包括复数形式。应该进一步理解的是,本申请的说明书中使用的措辞“包括”是指存在所述特征、整数、步骤、操作、元件和/或组件,但是并不排除存在或添加一个或多个其他特征、整数、步骤、操作、元件、组件和/或它们的组。应该理解,当我们称元件被“连接”或“耦接”到另一元件时,它可以直接连接或耦接到其他元件,或者也可以存在中间元件。此外,这里使用的“连接”或“耦接”可包括无线连接或无线耦接。这里使用的措辞“和/或”包括一个或更多个相关联的列出项的全部或任一单元和全部组合。
本申请的发明人进行研究发现,在现有的巨量转移技术中,目前常用的激光转移存在以下缺陷:需要使用至少一片carrier(粘贴基板或转移基板)做为中转层,转移环节多、配合转移的器件多,转移效率低、转移精度受限;目前只能实现水平电极结构的MicroLED的转移,兼容性不足。
本申请提供的微型发光二极管显示面板及其制备方法,旨在解决现有技术的如上技术问题。
下面以具体地实施例对本申请的技术方案以及本申请的技术方案如何解决上述技术问题进行详细说明。
本申请实施例提供了一种微型发光二极管显示面板的制备方法,该制备方法的流程示意图如图1所示,包括步骤S101-S105:
S101、在衬底基材200的一侧制备磊晶层,磊晶层包括第一半导体层340、发光材料层330、第二半导体层320和第一导电层310,第一半导体层340与衬底基材200直接接触,第一导电层310为磊晶层中最远离衬底基材200的膜层。
S102:将磊晶层划分为阵列排布的多个发光二极管晶粒300,之后执行步骤S104。
S103:提供背板100,在背板100上制作绑定结构110。
S104:将多个发光二极管晶粒300中的至少部分发光二极管晶粒300的第一导电层310与绑定结构110相绑定。
S105:将与绑定结构110相绑定的发光二极管晶粒300从衬底基材200剥离。
在本实施例中,在衬底基材200上制备阵列排布的多个垂直电极结构的发光二极管晶粒300,采用可选择性剥离,将指定的发光二极管晶粒300直接转移到目标背板100,即采用一次转移,不需使用作为中转的粘贴基板或转移基板,简化了转移环节,减少了配合转移的器件数量,大大提高了转移效率以及转移精度。
在衬底基材200上制备的磊晶层中,第一半导体层340与衬底基材200直接接触,第一导电层310位于磊晶层中最远离衬底基材200的膜层,用于与背板100的绑定结构110相绑定。制备得到的磊晶层为垂直电极结构,由磊晶层阵列划分后得到的多个发光二极管晶粒300也为垂直电极结构,改善了现有技术只能实现水平电极结构的发光二极管晶粒300转移的局限,实现了对垂直电极结构的发光二极管晶粒300的转移,提高了巨量转移的兼容性。
在一些可能的实施方式中,图1提供的制备方法可以先执行步骤S101-S102,完成在衬底基材200的一侧制备阵列排布的多个发光二极管晶粒300,然后执行步骤S103,在背板100上制作绑定结构110,再执行步骤S104-S105,完成至少部分(即指定)发光二极管晶粒300与背板100上绑定结构110的绑定,以及将此部分发光二极管晶粒300从衬底基材200的一侧剥离。
在一些可能的实施方式中,图1提供的制备方法可以先执行步骤S103,在背板100上制作绑定结构110,然后执行步骤S101-S102,完成在衬底基材200的一侧制备阵列排布的多个发光二极管晶粒300,再执行步骤S104-S105,完成至少部分(即指定)发光二极管晶粒300与背板100上绑定结构110的绑定,以及将此部分发光二极管晶粒300从衬底基材200的一侧剥离。
在一些可能的实施方式中,图1提供的制备方法在执行步骤S101-S102的过程中,执行步骤S103,然后执行步骤S104-S105。
本申请实施例提供了另一种微型发光二极管显示面板的制备方法,该方法的流程示意图如图2所示,该方法包括步骤S201-S207:
S201:在衬底基材200的一侧制备磊晶层,磊晶层包括第一半导体层340、发光材料层330、第二半导体层320和第一导电层310,第一半导体层340与衬底基材200直接接触,第一导电层310为磊晶层中最远离衬底基材200的膜层。
经过上述步骤S201,可在衬底基材200的一侧得到垂直电极结构的磊晶层,为下一步获得垂直电极结构的发光二极管晶粒300阵列做好了准备。其中,磊晶层中的第一半导体层340与衬底基材200直接接触,可便于后续发光二极管晶粒300从衬底基材200的一侧剥离。第一导电层310为磊晶层中最远离衬底基材200的膜层,可利于后续将发光二极管晶粒300与背板100上的绑定结构110相绑定。
可选地,衬底基材200可选用透明材质,以配合后续采用激光剥离的方式时,便于激光穿过衬底基材200后作用在发光二极管晶粒300的第一半导体层340与衬底基材200接触的表面,实现发光二极管晶粒300从衬底基材200的一侧剥离。可选地,衬底基材200可以为蓝宝石。
可选地,第一半导体层340是N型半导体,可采用氮化镓材质。氮化镓材质能够在激光的烧蚀作用下分解为氮气和金属镓,有利于实现后续激光剥离。
可选地,第二半导体层320是P型半导体,也可采用氮化镓材质。
可选地,发光材料层330包括多量子阱结构。
S202:将磊晶层划分为阵列排布的多个发光二极管晶粒300,之后执行步骤S204。
在一些可能的实施方式中,上述步骤S202中将磊晶层划分为阵列排布的多个发光二极管晶粒300,包括:对第一半导体层340、发光材料层330、第二半导体层320和第一导电层310进行阵列化刻蚀。阵列化刻蚀可借助掩膜板实现,该掩膜板上的图案与目标发光二极管晶粒300阵列相适应,即掩膜板上的镂空区域与发光二极管晶粒300阵列中,各发光二极管晶粒300之间的间隙相对应。经过前述操作,可以在衬底基材200的一侧得到阵列排布的多个垂直电极结构的发光二极管晶粒300。
在另一些可能的实施方式中,上述步骤S202中将磊晶层划分为阵列排布的多个发光二极管晶粒300,包括:对第一半导体层340、发光材料层330、第二半导体层320和第一导电层310,进行阵列化刻蚀,得到阵列排布的多个发光二极管晶粒300;多个发光二极管晶粒300中的任意一个发光二极管晶粒300的截面形状为梯形或圆形,截面平行于衬底基材200所在平面。
经过前述操作,不仅可以在衬底基材200的一侧得到阵列排布的多个垂直电极结构的发光二极管晶粒300,还可以使得到的发光二极管晶粒300的平行于衬底基材200的截面形状为梯形或圆形。具体地,可以调整阵列化刻蚀时使用的掩膜板,使掩膜板上的图案与发光二极管晶粒300阵列中每个发光二极管晶粒300的截面形状相适应。
得到的发光二极管晶粒300具有梯形或圆形的截面形状,即可形成沿激光扫描的方向上截面逐步增大的结构,可在后续采用激光剥离的方式将发光二极管晶粒300从衬底基材200的一侧剥离时,激光沿激光扫描方向烧蚀的第一半导体层340的面积逐步增大,可利于第一半导体层340因激光剥离而产生的大量气体迅速脱离发光二极管晶粒300,可避免快速产生的气体堆积在发光二极管晶粒300内部而导致的发光二极管晶粒300破裂。
可选地,发光二极管晶粒300的平行于衬底基材200的截面为梯形截面时,梯形截面的上底位于激光剥离的激光扫描方向的上游,梯形截面的下底位于激光剥离的激光扫描方向的下游。如图8所示,图8中的实线箭头,表示激光剥离时的激光扫描方向;图8中的虚线箭头,表示排气方向。
可以理解地,前述针对发光二极管晶粒300的平行于衬底基材200的截面的阵列化刻蚀,还可以包括其他形状化的阵列化刻蚀,满足位于激光扫描方向上游端的尺寸小于位于中游部的尺寸即可。例如,对第一半导体层340、发光材料层330、第二半导体层320和第一导电层310,进行三角形图案化或椭圆形图案化的阵列化刻蚀。
S203:提供背板100,在背板100上制作绑定结构110。
在一些可能的实施方式中,上述步骤S203中在背板100上制作绑定结构110,可包括步骤:在背板100上的沉积用于绑定的导电层,根据衬底基材200上至少部分的发光二极管晶粒300的第一导电层310的分布,即针对衬底基材200400上指定的发光二极管晶粒300的第一导电层310的分布,将背板100上用于绑定的导电层适应性地图案化,得到绑定结构110。
可选地,背板100上还可以包括用于驱动发光二极管晶粒300发光的驱动器件120,例如:TFT(Thin Film Transistor,薄膜晶体管)或者μIC(微型控制电路)。
经过步骤S201-S203后,得到的衬底基材200结构以及背板100的结构如图4所示。衬底基材200上制得了阵列排布的多个垂直电极结构的发光二极管晶粒300,背板100上制得了用于绑定选定发光二极管晶粒300的绑定结构110。
S204:将多个发光二极管晶粒300中的至少部分发光二极管晶粒300的第一导电层310与绑定结构110相绑定。
上述步骤S204中将多个发光二极管晶粒300中的至少部分发光二极管晶粒300的第一导电层310与绑定结构110相绑定,可包括:将至少部分的发光二极管晶粒300的第一导电层310通过共晶反应与绑定结构110相绑定。
经过步骤S204后,得到的衬底基材200与背板100的位置关系如图5所示。此时发光二极管晶粒300的第一导电层310与背板100上的绑定结构110完成了绑定。
S205:将与绑定结构110相绑定的发光二极管晶粒300从衬底基材200剥离。
在一些可能的实施方式中,上述步骤S205中将与绑定结构110相绑定的发光二极管晶粒300从衬底基材200剥离,包括:对与绑定结构110相绑定的发光二极管晶粒300的第一半导体层340进行激光烧蚀,使发光二极管晶粒300的第一半导体层340与衬底基材200分离。
步骤S205的剥离以激光剥离为例,剥离状态如图6所示,图6中的箭头表示激光照射方向。可以利用掩膜板400,该掩膜板400上的镂空区域与发光二极管晶粒300阵列中,与绑定结构110相绑定的各发光二极管晶粒300相对应,以使激光穿过掩膜板400上的图案镂空的部分,通过衬底基材200,作用在指定的微型发光二极管晶粒300的第一半导体层340直接接触衬底基材200的表面,将氮化镓材质的第一半导体层340连接衬底基材200的表面分解为氮气和金属镓,实现激光剥离。
可选地,激光剥离可使用型号为Excimer 248nm laser或266nm DPSS laser的激光设备,搭配DOE(Diffractive Optical Elements,光学衍射元器件)或是震镜与掩膜板400,实现激光剥离。
可选地,在前述方法中,对与绑定结构110相绑定的发光二极管晶粒300的第一半导体层340进行激光烧蚀,包括:对发光二极管晶粒300的第一半导体层340远离背板100的一侧表面,进行弧面化的激光烧蚀。
在本实施例中,由于点光源的出光波前为弧面340a,并且在激光烧蚀的过程中,掩膜板400上镂空区域的边缘可对激光烧蚀产生一定的屏蔽作用,即掩膜板上镂空区域的边缘对应的第一半导体层340被激光烧蚀的速率,会低于掩膜板上镂空区域的中心对应的第一半导体层340被激光烧蚀的速率,利用该烧蚀速率差即可对第一半导体层340远离背板100的一侧表面烧蚀得到弧面,再通过控制激光的强度和照射时间即可获得需要的弧面340a深度。经过前述弧面化的激光烧蚀可以使发光二极管晶粒300的第一半导体层340远离发光材料层330的一侧表面形成向发光材料层330凹陷的弧面340a结构,发光二极管晶粒300结构如图7所示。发光二极管晶粒300的第一半导体层340上的弧面340a结构可减少垂直电极结构的发光二极管晶粒300存在的电流拥挤,可增加光取出电流效率。由于发光二极管晶粒300的第一导电层310与绑定结构110可通过共晶反应相绑定,因此图7和图9中将完成绑定后的第一导电层310与绑定结构110视为同一膜层结构。
S206:在发光二极管晶粒300的第一半导体层340远离背板100的一侧制作顶电极(TCL,Top conductor layer)层。
S207:在顶电极层350远离背板100的一侧制作第二电极图案360。
经过步骤S206和步骤S207后,可以得到如图9所示的显示面板结构。图9中的实线箭头表示的是显示面板的出光方向,图9中的虚线箭头示意的是发光二极管晶粒300结构中,由第一导电层310通往第二电极图案360的两条导电路径,R1是其中一条导电路径(即在垂直于第一导电层310的方向上存在正对的第二电极图案360的路径)的等效电阻,R2是另一条导电路径(即在垂直于第一导电层310的方向上不存在正对的第二电极图案360的路径)中由第一导电层310到第一半导体层340(具体地到第一半导体层340靠近TCL层的边界)的等效电阻,RTCL是另一条路径经过TCL层中的等效电阻,可见,发光二极管晶粒300的第一半导体层340远离发光材料层330的一侧表面经过弧面化处理后,R2+RTCL的值可以更接近R1,甚至R2+RTCL的值可以等于R1,即可以减少垂直电极结构的发光二极管晶粒300存在的电流拥挤,可增加光取出电流效率。
可以理解的是,与前述实施例提供的一种实施例提供的一种微型发光二极管显示面板的制备方法相同,本实施例提供的另一种微型发光二极管显示面板的制备方法中,步骤S201-S202与步骤S203的先后顺序无需严格规定,可以是步骤S201-S202在步骤S203之前执行,也可以是步骤S201-S202在步骤S203之后执行,还可以是步骤S201-S202与步骤S203同时执行。
本申请实施例提供了再一种微型发光二极管显示面板的制备方法,该方法的流程示意图如图3所示,该方法包括步骤S301-S307:
S301:在衬底基材200的一侧制备磊晶层,磊晶层包括第一半导体层340、发光材料层330、第二半导体层320和第一导电层310,第一半导体层340与衬底基材200直接接触,第一导电层310为磊晶层中最远离衬底基材200的膜层。
S302:将磊晶层划分为阵列排布的多个发光二极管晶粒300,之后执行步骤S304。
S303:提供背板100,在背板100上制作绑定结构110。
S304:将多个发光二极管晶粒300中的至少部分发光二极管晶粒300的第一导电层310与绑定结构110相绑定。
S305:将与绑定结构110相绑定的发光二极管晶粒300从衬底基材200剥离。
S306:在发光二极管晶粒300远离背板100的一侧制作第二电极图案360。
S307:以第二电极图案360为掩膜,对发光二极管晶粒300的第一半导体层340远离发光材料层330的一侧表面,进行弧面化的激光烧蚀。
本实施例提供的再一种微型发光二极管显示面板的制备方法,与前述另一种微型发光二极管显示面板的制备方法的原理基本相同,区别在于:在发光二极管晶粒300的第一半导体层340与衬底基材200的激光剥离完成之后,先在发光二极管晶粒300远离背板100的一侧制作第二电极图案360,然后以第二电极图案360为掩膜,对第一半导体层340远离发光材料层330的一侧表面进行弧面化的激光烧蚀。本实施例的有益效果在于,第二电极图案360在对第一半导体层340进行的弧面化的激光烧蚀之前制作,用于制作第二电极图案360的掩膜板无需根据完成弧面化的第一半导体层340表面结构进行设计,可降低制作第二电极图案360的难度。
可选地,第二电极图案360可为环形电极图案,以配合发光二极管晶粒300的第一半导体层340远离发光材料层330的一侧表面形成向发光材料层330凹陷的弧面340a结构,提升垂直结构的发光二极管晶粒300内电流分布均匀性与导电性。
可选地,在上述任一种制备方法中,激光烧蚀至少满足以下条件A-D中任一种条件:
条件A:激光烧蚀的激光照射频率为0.1Hz-1kHz(赫兹),并且可以搭配相适应的工作循环或脉冲周期。
条件B:激光烧蚀的环境气氛包括湿度低于5%的空气,例如CDA(即Cold Dry Air,冷干空气)。
条件C:激光烧蚀的环境气氛中包括大于0.1摩尔浓度的雾化氯化氢,以利于移除氮化镓受激光作用而分解得到的金属镓。具体地,以CDA为载体,氯化氢为腐蚀性溶剂形成气溶胶悬浮于CDA中,将氮化镓分解得到的金属镓溶解并移除,这并可加速工艺,避免因为镓金属积累让工艺均匀度下降、或是剥离速率下降。
条件D:激光烧蚀采用温度低于25℃的氮气进行冷却。
基于同一发明构思,本申请实施例提供的一种微型发光二极管显示面板,该显示面板的结构示意图如图8所示,包括:背板100和多个发光二极管晶粒300;
多个发光二极管晶粒300中的每个发光二极管晶粒300包括叠层设置的第一半导体层340、发光材料层330、第二半导体层320和第一导电层310;
第一导电层310与背板100上的绑定结构110相绑定;
第二半导体层320位于第一导电层310远离背板100的一侧;
发光材料层330位于第二半导体层320远离第一导电层310的一侧;
第一半导体层340位于发光材料层330远离第二半导体层320的一侧。
在本实施例中,微型发光二极管晶粒300采用垂直电极结构,使得电流几乎全部垂直流过微型发光二极管晶粒300的外延层,极少横向流动的电流,利于电流的扩散以及热量的散发,可满足大功率发展趋势。
采用垂直电极结构的发光二极管晶粒300,其所有的制造工艺都是在晶片水平进行的,因此具备如下特点:
与水平结构相比,抗静电能力高。
无需打金线,一方面封装厚度薄,可用于制造超薄型的器件,如背光源,大屏幕显示等;另一方面,良品率和可靠性均得以提高。
可在封装前进行老化,降低生产成本。
可以采用较大直径的通孔和金属填充塞,或采用多个的通孔和金属填充塞,进一步提高衬底的散热效率,特别适合对大功率发光二极管的需要。
在一些可能的实施方式中,如图9所示,发光二极管晶粒300不仅包括前述第一半导体层340、发光材料层330、第二半导体层320和第一导电层310,发光二极管晶粒300还包括第二电极图案360和顶电极(TCL,Top conductor layer)层350。
顶电极层350位于第一半导体层340远离发光材料层330的一侧。
第二电极图案360位于顶电极层350远离第一半导体层340的一侧。
第一半导体层340包括凹陷区和非凹陷区,所述凹陷区远离发光材料层330的一侧表面具有弧面340a,弧面340a在背板100所在平面的正投影与第二电极图案360在背板100所在平面的正投影不重合;顶电极层350具有与第一半导体层340的弧面340a相适应的弧形区域350a。
本实施例提供了一种具体的垂直电极结构的发光二极管晶粒300。发光二极管晶粒300的第一半导体层340上的弧面340a结构可减少垂直电极结构的发光二极管晶粒300存在的电流拥挤,可增加光取出电流效率。
可选地,如图9所示,第一半导体层340的非凹陷区的厚度h1为5-10μm(微米),第一半导体层340的凹陷区的最小厚度h2为2-5μm,即第一半导体层340的任一弧面340a顶点处的厚度为2-5μm。弧面340a的曲率不大于0.3。
可选地,第一导电层310可以是阳极,第二电极图案360可以是阴极。
可选地,第一导电层310和第二电极图案360均可采用ITO(Indium Tin Oxides,氧化铟锡)材质。
本申请的发明人考虑到,微型发光二极管晶粒300在制备过程中需要经过巨量转移,巨量转移工序中的激光剥离会排放大量气体,若气体排放不畅,容易造成发光二极管晶粒300的破坏。为此,本申请为微型发光二极管显示面板提供如下一种可能的实现方式:
如图8所示,本申请实施例的发光二极管晶粒300的平行于背板100的截面形状为梯形或圆形。
图8中的实线箭头,表示激光剥离时的激光扫描方向;图8中的虚线箭头,表示排气方向。
制备发光二极管晶粒300过程中,将发光二极管晶粒300与衬底基材200激光剥离时,激光扫描的行走方向通常与衬底基材200所在平面相平行,背板100通常也与衬底基材200平行。发光二极管晶粒300的梯形或圆形的截面平行于背板100,就意味着与激光扫描的行走方向相平行。发光二极管晶粒300具有梯形或圆形的截面结构,即可形成沿激光扫描的方向上截面逐步增大的结构,利于在巨量转移工序中,单位时间内激光烧蚀的第一半导体层340的面积逐步增大,可利于发光二极管晶粒300的第一半导体层340因激光剥离而产生的大量气体迅速脱离发光二极管晶粒300,可避免快速产生的气体堆积在发光二极管晶粒300内部而导致的发光二极管晶粒300破裂,提高良品率。
可选地,发光二极管晶粒300的平行于背板100的截面为梯形截面时,梯形截面的上底位于激光剥离的激光扫描方向的上游,梯形截面的下底位于激光剥离的激光扫描方向的下游。
可以理解地,前述发光二极管晶粒300的平行于背板100的截面,还可以包括其他形状,满足位于激光扫描方向上游端的尺寸小于位于中游部的尺寸即可。例如,发光二极管晶粒300的平行于背板100的截面为三角形或椭圆形。
在一些可能的实施方式中,如图8所示,若发光二极管晶粒300的平行于背板100的截面为梯形,则截面的尺寸满足b>2a,c<b;
其中,a是梯形的上底尺寸,b是梯形的下底尺寸,c是梯形的高。
本实施例中,发光二极管晶粒300的平行于所述背板100的截面满足上述尺寸要求后,可以在激光剥离过程中有利于氮化镓分解后产生的氮气迅速脱离发光二极管晶粒300,可避免快速产生的氮气堆积在发光二极管晶粒300内部而导致的发光二极管晶粒300破裂。
可选地,梯形截面的尺寸可以采用:a<100μm,b<200μm,c<200μm。
下面提供一种具体的微型发光二极管显示面板的制备方法实施例。
第一步,采用标准方法清洗背板,在背板上制作驱动器件120。以驱动器件120为TFT为例,可以在背板上依次沉积厚度为0.2μm左右的金属Mo(钼)层,并图形化形成TFT的栅电极以及与之同层的第一信号线;形成厚度0.15μm的栅极介质SiO2(二氧化硅);形成厚度40nm的IGZO(铟镓锌氧化物)层,并图形化形成有源图案;沉积厚度为0.2μm左右的金属Mo(钼)层,图案化形成源漏极电极以及与之同层的第二信号线;形成厚度约0.3μm的钝化层SiO2;形成Ti(钛)/Al(铝)/Ti层叠膜层,图形化构成像素电极和连接电极,其中像素电极与源漏极电极中的一者电连接,而连接电极与第一信号线或第二信号线中传输固定电平信号的信号线连接。像素电极和连接电极可以直接作为绑定结构,也可以在像素电极和连接电极表面制作其他导电图案作为绑定结构,以与发光二极管晶粒300的电极电连接。
第二步,采用标准方法清洗衬底基材,如蓝宝石,在蓝宝石衬底上依次形成P-GaN(P型氮化镓半导体)层;Ni(镍)/Au(金)层,作为欧姆接触层,Ni与Au的厚度分别大约为0.005μm和0.005μm;形成发光材料层,包括多量子阱结构;形成N-GaN(N型氮化镓半导体)层;沉积Ti/Au层或沉积Ti/Al层,Ti与Au的厚度分别大约为0.01μm和0.1μm,或电极中Ti与Al的厚度分别为0.01μm和0.1μm,经过构图工艺形成电极结构。在衬底基材上得到磊晶层(包括P型氮化镓半导体,欧姆接触层,N型氮化镓半导体,发光材料层和电极层的叠层结构),将磊晶层阵列划分后得到阵列排布的多个发光二极管晶粒300。
第三步,将通过选择阵列排布的多个发光二极管晶粒300中与背板上的绑定结构位置对应处的发光二极管晶粒300的电极与背板上的绑定结构通过共晶反应绑定在一起,对绑定在背板上的发光二极管晶粒300的P-GaN层进行激光烧蚀,从而将对应的发光二极管晶粒300从衬底基材上剥离;此外,通过控制激光烧蚀工艺的参数(如可参考本发明上述实施例中描述的内容),以使发光二极管晶粒300的P-GaN层远离背板100的一侧表面包括弧面部分,再将带有未与背板绑定的发光二极管晶粒的衬底基材从背板一侧完全移开。
第四步,利用混有雾化HCl(氯化氢)的空气去除发光二极管晶粒300的P-GaN层上残留的Ga(镓)金属。
第五步,形成平坦层,平坦层覆盖位于背板100上的发光二极管晶粒300并填充相邻发光二极管晶粒300之间的间隙,之后进行构图工艺,以露出发光二极管晶粒300远离背板100一侧的部分表面。
第六步,在发光二极管晶粒300远离背板100一侧的裸露表面制作电极,该电极可以是发光二极管晶粒300的阴极,也可以是与阴极电连接的其他导电层,最后得到微型发光二极管显示面板。
应用本申请实施例,至少能够实现如下有益效果:
1、在衬底基材200上制备阵列排布的多个垂直电极结构的发光二极管晶粒300,采用可选择性剥离,将指定的发光二极管晶粒300直接转移到目标背板100,即采用一次转移,不需使用作为中转的粘贴基板或转移基板,简化了转移环节,减少了配合转移的器件数量,大大提高了转移效率以及转移精度。
2、制备得到的磊晶层为垂直电极结构,由磊晶层阵列划分后得到的多个发光二极管晶粒300也为垂直电极结构,改善了现有技术只能实现水平电极结构的发光二极管晶粒300转移的局限,实现了对垂直电极结构的发光二极管晶粒300的转移,提高了巨量转移的兼容性。
3、对发光二极管磊晶层进行梯形图案化或圆形图案化的阵列化刻蚀,使刻蚀得到的发光二极管晶粒300的平行于衬底基材200的截面形状为梯形或圆形,即可形成沿激光扫描的方向上截面逐步增大的结构,可在后续采用激光剥离的方式将发光二极管晶粒300从衬底基材200的一侧剥离时,激光沿激光扫描方向烧蚀的第一半导体层340的面积逐步增大,可利于第一半导体层340因激光剥离而产生的大量气体迅速脱离发光二极管晶粒300,可避免快速产生的气体堆积在发光二极管晶粒300内部而导致的发光二极管晶粒300破裂。
4、弧面化的激光烧蚀可以使发光二极管晶粒300的第一半导体层340远离发光材料层330的一侧表面形成向发光材料层330凹陷的弧面340a结构,通过控制激光的强度和照射时间即可获得需要的弧面340a深度。发光二极管晶粒300的第一半导体层340上的弧面340a结构可减少垂直电极结构的发光二极管晶粒300存在的电流拥挤,可增加光取出电流效率。
5、在发光二极管晶粒300的第一半导体层340与衬底基材200的激光剥离完成之后,先在发光二极管晶粒300远离背板100的一侧制作第二电极图案360,然后以第二电极图案360为掩膜,对第一半导体层340远离发光材料层330的一侧表面进行弧面化的激光烧蚀。这样,用于制作第二电极图案360的掩膜板无需根据完成弧面化的第一半导体层340表面结构进行设计,可降低制作第二电极图案360的难度。
6、提供了采用垂直电极结构的微型发光二极管晶粒300,使得电流几乎全部垂直流过微型发光二极管的外延层,极少横向流动的电流,利于电流的扩散以及热量的散发,可满足大功率发展趋势。
7、发光二极管晶粒300的第一半导体层340上的弧面340a结构可减少垂直电极结构的发光二极管晶粒300存在的电流拥挤,可增加光取出电流效率。
8、发光二极管晶粒300的平行于背板100的截面呈梯形或圆形,利于在巨量转移工序中,单位时间内激光烧蚀的第一半导体层340的面积逐步增大,可利于发光二极管晶粒300的第一半导体层340因激光剥离而产生的大量气体迅速脱离发光二极管晶粒300,可避免快速产生的气体堆积在发光二极管晶粒300内部而导致的发光二极管晶粒300破裂,提高良品率。
本技术领域技术人员可以理解,本申请中已经讨论过的各种操作、方法、流程中的步骤、措施、方案可以被交替、更改、组合或删除。进一步地,具有本申请中已经讨论过的各种操作、方法、流程中的其他步骤、措施、方案也可以被交替、更改、重排、分解、组合或删除。进一步地,现有技术中的具有与本申请中公开的各种操作、方法、流程中的步骤、措施、方案也可以被交替、更改、重排、分解、组合或删除。
在本申请的描述中,需要理解的是,术语“中心”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本申请和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本申请的限制。
术语“第一”、“第二”仅用于描述目的,而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此,限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中,除非另有说明,“多个”的含义是两个或两个以上。
在本申请的描述中,需要说明的是,除非另有明确的规定和限定,术语“安装”、“相连”、“连接”应做广义理解,例如,可以是固定连接,也可以是可拆卸连接,或一体地连接;可以是直接相连,也可以通过中间媒介间接相连,可以是两个元件内部的连通。对于本领域的普通技术人员而言,可以具体情况理解上述术语在本申请中的具体含义。
在本说明书的描述中,具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
应该理解的是,虽然附图的流程图中的各个步骤按照箭头的指示依次显示,但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明,这些步骤的执行并没有严格的顺序限制,其可以以其他的顺序执行。而且,附图的流程图中的至少一部分步骤可包括多个子步骤或者多个阶段,这些子步骤或者阶段并不必然是在同一时刻执行完成,而是可以在不同的时刻执行,其执行顺序也不必然是依次进行,而是可以与其他步骤或者其他步骤的子步骤或者阶段的至少一部分轮流或者交替地执行。
以上所述仅是本申请的部分实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本申请原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本申请的保护范围。

Claims (12)

1.一种微型发光二极管显示面板的制备方法,其特征在于,包括:
在衬底基材的一侧制备磊晶层,所述磊晶层包括第一半导体层、发光材料层、第二半导体层和第一导电层,所述第一半导体层与所述衬底基材直接接触,所述第一导电层为磊晶层中最远离所述衬底基材的膜层;
将所述磊晶层划分为阵列排布的多个发光二极管晶粒;
提供背板,在所述背板上制作绑定结构;
将所述多个发光二极管晶粒中的至少部分发光二极管晶粒的第一导电层与所述绑定结构相绑定;
将与所述绑定结构相绑定的所述发光二极管晶粒从所述衬底基材剥离。
2.根据权利要求1所述的制备方法,其特征在于,所述将所述磊晶层划分为阵列排布的多个发光二极管晶粒,包括:
对所述第一半导体层、所述发光材料层、所述第二半导体层和所述第一导电层进行阵列化刻蚀,得到阵列排布的所述多个发光二极管晶粒;所述多个发光二极管晶粒中的任意一个发光二极管晶粒的截面形状为梯形或圆形,所述截面平行于所述衬底基材。
3.根据权利要求1所述的制备方法,其特征在于,所述将与所述绑定结构相绑定的所述发光二极管晶粒从所述衬底基材剥离,包括:
对与所述绑定结构相绑定的所述发光二极管晶粒的所述第一半导体层进行激光烧蚀,使所述发光二极管晶粒的所述第一半导体层与所述衬底基材分离。
4.根据权利要求3所述的制备方法,其特征在于,所述对与所述绑定结构相绑定的所述发光二极管晶粒的所述第一半导体层进行激光烧蚀,包括:对所述发光二极管晶粒的所述第一半导体层远离所述背板的一侧表面,进行弧面化的激光烧蚀。
5.根据权利要求4所述的制备方法,其特征在于,所述将与所述绑定结构相绑定的所述发光二极管晶粒从所述衬底基材剥离之后,还包括:
在所述发光二极管晶粒的所述第一半导体层远离所述背板的一侧制作顶电极层;
在所述顶电极层远离所述背板的一侧制作第二电极图案。
6.根据权利要求1所述的制备方法,其特征在于,所述将与所述绑定结构相绑定的所述发光二极管晶粒从所述衬底基材的所述一侧剥离之后,还包括:
在所述发光二极管晶粒远离所述背板的一侧制作第二电极图案;
以所述第二电极图案为掩膜,对所述发光二极管晶粒的所述第一半导体层远离所述发光材料层的一侧表面,进行弧面化的激光烧蚀。
7.根据权利要求3-6中任一项所述的制备方法,其特征在于,所述激光烧蚀至少满足以下一种条件:
所述激光烧蚀的激光照射频率为0.1Hz-1kHz;
所述激光烧蚀的环境气氛包括湿度低于5%的空气;
所述激光烧蚀的环境气氛中包括大于0.1摩尔浓度的雾化氯化氢;
所述激光烧蚀采用温度低于25℃的氮气进行冷却。
8.一种微型发光二极管显示面板,其特征在于,包括:背板(100)和多个发光二极管晶粒(300);
所述多个所述发光二极管晶粒(300)中的每个发光二极管晶粒(300)包括叠层设置的第一半导体层(340)、发光材料层(330)、第二半导体层(320)和第一导电层(310);
所述第一导电层(310)与所述背板(100)上的绑定结构(110)相绑定;
所述第二半导体层(320)位于所述第一导电层(310)远离所述背板(100)的一侧;
所述发光材料层(330)位于所述第二半导体层(320)远离所述第一导电层(310)的一侧;
所述第一半导体层(340)位于所述发光材料层(330)远离所述第二半导体层(320)的一侧。
9.根据权利要求8所述的显示面板,其特征在于,所述发光二极管晶粒(300)还包括第二电极图案(360)和顶电极层(350);
所述顶电极层(350)位于所述第一半导体层(340)远离所述发光材料层(330)的一侧;
所述第二电极图案(360)位于所述顶电极层(350)远离所述第一半导体层(340)的一侧;
所述第一半导体层(340)包括凹陷区和非凹陷区,所述凹陷区远离所述发光材料层(330)的一侧表面具有弧面,所述弧面(340a)在所述背板所在平面的正投影与所述第二电极图案(360)在所述背板所在平面的正投影不重合;所述顶电极层(350)具有与所述第一半导体层(340)的所述弧面(340a)相适应的弧形区域(350a)。
10.根据权利要求9所述的显示面板,其特征在于,所述第一半导体层(340)的所述非凹陷区的厚度为5-10μm,所述第一半导体层(340)的所述凹陷区的最小厚度为2-5μm,所述弧面(340a)的曲率不大于0.3。
11.根据权利要求8-10中任一项所述的显示面板,其特征在于,所述发光二极管晶粒的平行于所述背板(100)的截面形状为梯形或圆形。
12.根据权利要求11所述的显示面板,其特征在于,若所述发光二极管晶粒(300)的平行于所述背板(100)的截面为梯形,则所述截面的尺寸满足b>2a,c<b;
其中,a是所述截面的上底尺寸,b是所述截面的下底尺寸,c是所述截面的高。
CN202010202937.2A 2020-03-20 2020-03-20 微型发光二极管显示面板及其制备方法 Pending CN113497074A (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202010202937.2A CN113497074A (zh) 2020-03-20 2020-03-20 微型发光二极管显示面板及其制备方法
PCT/CN2021/081368 WO2021185289A1 (zh) 2020-03-20 2021-03-17 微型发光二极管显示面板及其制备方法
US17/763,645 US20220344315A1 (en) 2020-03-20 2021-03-17 Micro light-emitting diode display panel and manufacturing method therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010202937.2A CN113497074A (zh) 2020-03-20 2020-03-20 微型发光二极管显示面板及其制备方法

Publications (1)

Publication Number Publication Date
CN113497074A true CN113497074A (zh) 2021-10-12

Family

ID=77770075

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010202937.2A Pending CN113497074A (zh) 2020-03-20 2020-03-20 微型发光二极管显示面板及其制备方法

Country Status (3)

Country Link
US (1) US20220344315A1 (zh)
CN (1) CN113497074A (zh)
WO (1) WO2021185289A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116314491A (zh) * 2023-05-25 2023-06-23 江西兆驰半导体有限公司 一种Micro LED灯珠及其制备方法
CN116314492A (zh) * 2023-05-25 2023-06-23 江西兆驰半导体有限公司 一种全彩化Micro LED器件及其制备方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116682912B (zh) * 2023-06-21 2024-05-28 惠科股份有限公司 发光芯片、显示面板、发光组件及其制作方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103887387A (zh) * 2012-12-24 2014-06-25 鸿富锦精密工业(深圳)有限公司 Led晶粒、led车灯及led晶粒的制造方法
CN105493297A (zh) * 2015-05-21 2016-04-13 歌尔声学股份有限公司 微发光二极管的转移方法、制造方法、装置和电子设备
CN109661122A (zh) * 2018-11-09 2019-04-19 华中科技大学 一种适用于微型发光二极管的选择性巨量转移方法
CN109935664A (zh) * 2017-12-19 2019-06-25 优显科技股份有限公司 光电半导体戳记及其制造方法与光电半导体装置
US20190302917A1 (en) * 2018-03-27 2019-10-03 Shaoher Pan Integrated light-emitting pixel arrays based devices by bonding
CN110828364A (zh) * 2019-11-20 2020-02-21 广东省半导体产业技术研究院 巨量转移方法、显示装置的制作方法和显示装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9548332B2 (en) * 2012-04-27 2017-01-17 Apple Inc. Method of forming a micro LED device with self-aligned metallization stack
KR102039685B1 (ko) * 2013-04-17 2019-11-04 삼성디스플레이 주식회사 유기 발광 표시 장치
TWI520376B (zh) * 2013-12-06 2016-02-01 隆達電子股份有限公司 發光二極體元件的製造方法
CN105870265A (zh) * 2016-04-19 2016-08-17 京东方科技集团股份有限公司 发光二极管基板及其制备方法、显示装置
WO2018035668A1 (en) * 2016-08-22 2018-03-01 Goertek.Inc Micro-led transfer method, manufacturing method and device
WO2018102961A1 (en) * 2016-12-05 2018-06-14 Goertek.Inc Micro laser diode transfer method and manufacturing method
CN110998879B (zh) * 2017-08-10 2023-06-27 夏普株式会社 半导体模块、显示装置以及半导体模块的制造方法
JP2019047058A (ja) * 2017-09-06 2019-03-22 株式会社ブイ・テクノロジー 結晶化モニタ方法、レーザアニール装置、およびレーザアニール方法
CN109148652B (zh) * 2018-08-23 2020-08-25 上海天马微电子有限公司 无机发光二极管显示面板及其制作方法和显示装置
JP6915029B2 (ja) * 2018-11-30 2021-08-04 シャープ株式会社 マイクロ発光素子及び画像表示素子
US11387384B2 (en) * 2019-04-16 2022-07-12 Samsung Electronics Co., Ltd. LED transferring method and display module manufactured by the same
TWI790405B (zh) * 2019-06-21 2023-01-21 錼創顯示科技股份有限公司 半導體材料基板、微型發光二極體面板及其製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103887387A (zh) * 2012-12-24 2014-06-25 鸿富锦精密工业(深圳)有限公司 Led晶粒、led车灯及led晶粒的制造方法
CN105493297A (zh) * 2015-05-21 2016-04-13 歌尔声学股份有限公司 微发光二极管的转移方法、制造方法、装置和电子设备
CN109935664A (zh) * 2017-12-19 2019-06-25 优显科技股份有限公司 光电半导体戳记及其制造方法与光电半导体装置
US20190302917A1 (en) * 2018-03-27 2019-10-03 Shaoher Pan Integrated light-emitting pixel arrays based devices by bonding
CN109661122A (zh) * 2018-11-09 2019-04-19 华中科技大学 一种适用于微型发光二极管的选择性巨量转移方法
CN110828364A (zh) * 2019-11-20 2020-02-21 广东省半导体产业技术研究院 巨量转移方法、显示装置的制作方法和显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116314491A (zh) * 2023-05-25 2023-06-23 江西兆驰半导体有限公司 一种Micro LED灯珠及其制备方法
CN116314492A (zh) * 2023-05-25 2023-06-23 江西兆驰半导体有限公司 一种全彩化Micro LED器件及其制备方法

Also Published As

Publication number Publication date
US20220344315A1 (en) 2022-10-27
WO2021185289A1 (zh) 2021-09-23

Similar Documents

Publication Publication Date Title
US11728457B2 (en) Nano-scale LED element for horizontally-aligned assembly, method for manufacturing same, and horizontally-aligned assembly comprising same
CN113497074A (zh) 微型发光二极管显示面板及其制备方法
US10326045B2 (en) Micro light emitting diode device and manufacturing method thereof
TWI411124B (zh) 發光二極體裝置及其製造方法
US7364926B2 (en) Method for manufacturing gallium nitride light emitting diode devices
JP2008141026A (ja) 電子機器及びその製造方法、並びに、発光ダイオード表示装置及びその製造方法
CN111048497B (zh) 一种有源矩阵彩色显示器件的制造方法
EP3410480B1 (en) Display device
US20130069102A1 (en) Semiconductor light-emitting device, light-emitting module and method for manufacturing the same
CN111883553A (zh) 无需巨量转移操作的Micro LED显示面板制备方法
US9530930B2 (en) Method of fabricating semiconductor devices
US10937929B2 (en) Semiconductor unit, semiconductor device, light-emitting apparatus, display apparatus, and method of manufacturing semiconductor device
CN109148676B (zh) 一种高密度微显示led器件及其制作方法
CN114824047A (zh) 微型发光二极管显示芯片及制备方法
CN110246945B (zh) Led芯片及其制造方法、显示面板以及电子设备
US20210384176A1 (en) Micro light-emitting diode display device and method for fabricating same
CN116565103A (zh) MicroLED微显示芯片及其制造方法
TW202004851A (zh) 發光元件的製造方法
JP4078830B2 (ja) 表示装置及び表示装置の製造方法
CN102623589A (zh) 一种垂直结构的半导体发光器件制造方法
CN112909136A (zh) 发光二极管、显示面板、显示装置及制备方法
CN114975711B (zh) 一种Micro LED芯片及其制作方法
CN115692449A (zh) 一种芯片组件及其制作方法、芯片转移方法和电子装置
TW201205873A (en) Fabrication method of semiconductor light emitting element
TWI811729B (zh) 半導體結構及其製作方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination