CN113471286A - 半导体装置及半导体装置的制造方法 - Google Patents

半导体装置及半导体装置的制造方法 Download PDF

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CN113471286A
CN113471286A CN202110302505.3A CN202110302505A CN113471286A CN 113471286 A CN113471286 A CN 113471286A CN 202110302505 A CN202110302505 A CN 202110302505A CN 113471286 A CN113471286 A CN 113471286A
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diffusion layer
drain
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gate electrode
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畠中雅宏
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Abstract

本发明提供一种抑制ESD保护元件的劣化，容易实现所期望的耐压同时具有充分的ESD耐性的半导体装置及其制造方法。在半导体装置中，在ESD保护元件的漏极扩散层(106B)的周围配置高浓度扩散层(103)及低浓度扩散层(102)。高浓度扩散层(103)与栅极电极(105)隔开，在隔开的间隙配置中浓度的LDD扩散层(107B)。通过减少对高浓度扩散层(103)及中浓度扩散层(107)的热处理来抑制特性的偏差。

Description

半导体装置及半导体装置的制造方法
技术领域
本发明涉及一种半导体装置，特别是涉及一种强化了耐压的半导体装置的结构及其制造方法。
背景技术
在半导体集成电路中，为了保护内部元件不受以静电放电(electrostaticdischarge，ESD)为代表的各种电涌(surge)或电源电压的变动引起的噪声的影响，设置有ESD保护元件。特别是，以栅极常闭(normally off)的方式配置的截止晶体管(offtransistor)之类的ESD保护元件的运行范围需要设定得比半导体集成电路的最大运行电压高，比在半导体集成电路内部使用的内部元件的耐压低。但是，由于微细化，对ESD保护元件所要求的运行范围变窄，难以实现所期望的特性。
另一方面，作为保护元件的功能，还需要具备高的ESD耐性，即，即使电阻低而流过大量的电流，也不破坏。
作为改善对策，为了降低决定晶体管耐压的漏极侧的P/N结(P/N junction)附近的杂质浓度、提高杂质浓度高(也称高浓度)的漏极扩散层附近的杂质浓度，通过在包含漏极扩散层的漏极区域的周围配置双重扩散层来提高耐压，且设法成为低导通电阻(例如，参照专利文献1)。
[现有技术文献]
[专利文献]
[专利文献1]日本专利特开2007-266473号公报
发明内容
[发明所要解决的问题]
一般而言，若将高浓度的扩散层配置在栅极电极附近，则电场会变大，耐压会下降，因此为了强化耐压，需要远离栅极电极地配置高浓度的扩散层。另外，保护元件通过施加过电压而进入双极运行，容易发生漏极扩散层边界的电场集中引起的热破坏。为了抑制这种现象，需要将自栅极电极至漏极扩散层的中途区域以使其成为具有高浓度的方式来形成。
即，为了确保漏极耐压，抑制保护元件的劣化，需要使高浓度的漏极扩散层远离栅极电极，同时尽量提高其中途区域整体的浓度。
另一方面，为了确保耐压，形成了多重扩散结构的晶体管需要以处于所期望的耐压范围的方式调整扩散层的结构，以使在漏极区域内到达漏极扩散层的区域的浓度梯度变缓。但是，耐压会相对于结构或制程(process)的变化而变动，因此难以制造出具有裕度(margin)、可保护内部元件的元件。
因此，本发明的课题在于提供一种抑制ESD保护元件的劣化，容易实现所期望的耐压同时具有充分的ESD耐性的半导体装置。
[解决问题的技术手段]
为了解决所述问题，本发明以如下方式构成半导体装置。
即，一种半导体装置，包括：半导体基板；第二导电型的低浓度扩散层，设置在所述半导体基板；栅极电极，隔着栅极氧化膜设置在所述第二导电型的低浓度扩散层的表面；第一导电型的源极扩散层及第一导电型的漏极扩散层，所述第一导电型的源极扩散层设置在位于所述栅极电极的一侧的所述半导体基板的表面，所述第一导电型的漏极扩散层在位于所述栅极电极的另一侧的所述半导体基板的表面，与所述栅极电极隔开地设置；第一导电型的漏极LDD扩散层，设置在所述半导体基板的表面且位于所述漏极扩散层与所述栅极电极的所述漏极扩散层侧的端部的正下方之间；第一导电型的高浓度扩散层，设置成自较所述漏极LDD扩散层的所述源极扩散层侧的端部更靠近所述漏极扩散层的位置起包含所述漏极扩散层，相较于所述漏极LDD扩散层而言杂质浓度高，且相较于所述漏极扩散层而言杂质浓度低；以及第一导电型的低浓度扩散层，设置成自成为所述栅极电极的下方的所述半导体基板的表面起，在内部包含所述漏极LDD扩散层、所述高浓度扩散层及所述漏极扩散层，相较于所述漏极LDD扩散层而言杂质浓度低。
另外，本发明的一实施方式以如下方式构成半导体装置。
即，一种半导体装置，包括：半导体基板；第二导电型的低浓度扩散层，自所述半导体基板的表面至内部设置；第一导电型的源极扩散层及第一导电型的漏极扩散层，在成为所述第二导电型的低浓度扩散层的内侧的所述半导体基板的表面空开间隔地设置；场氧化膜，自所述源极扩散层及所述漏极扩散层之间的地点至所述漏极扩散层的端部设置；栅极氧化膜，在所述第二导电型的低浓度扩散层的表面，自所述场氧化膜的所述源极侧的端部至所述源极扩散层的端部设置；栅极电极，设置成覆盖所述栅极氧化膜与所述场氧化膜的一部分；第一导电型的漏极LDD扩散层，设置在所述场氧化膜下的所述半导体基板的表面；第一导电型的高浓度扩散层，设置成自较所述漏极LDD扩散层的所述源极扩散层侧的端部更靠近所述漏极扩散层的位置起包含所述漏极扩散层，相较于所述漏极LDD扩散层而言杂质浓度高，且相较于所述漏极扩散层而言杂质浓度低；以及第一导电型的低浓度扩散层，设置成自成为所述栅极电极的下方的所述半导体基板的表面，在内部包含所述漏极LDD扩散层、所述高浓度扩散层及所述漏极扩散层，相较于所述漏极LDD扩散层而言杂质浓度低。
另外，本发明的一实施方式以如下方式构成半导体装置的制造方法。
一种半导体装置的制造方法，包括：在半导体基板上离子注入第二导电型的杂质的工序；离子注入第一导电型的杂质，通过热扩散来形成低浓度扩散层的工序；离子注入第一导电型的杂质，形成高浓度扩散层的工序；形成栅极氧化膜的工序；形成栅极电极的工序；离子注入第一导电型的杂质，形成源极扩散层及漏极扩散层的工序；以及离子注入第一导电型的杂质，形成作为中浓度扩散层的LDD扩散层的工序。
[发明的效果]
通过使用所述手段，可缓和栅极电极附近的电场，实现耐压的强化，同时通过漏极扩散层附近的高浓度化，可降低电阻，实现高的ESD耐性。
另外，通过使高浓度扩散层远离栅极电极来设置漏极LDD扩散层，能够在抑制高浓度扩散层的偏差的同时，利用漏极LDD扩散层容易地调整耐压。
附图说明
图1是表示本发明的半导体装置的第一实施方式的N型MOS晶体管的示意性剖面图。
图2是表示第一实施方式的半导体装置的制造工序的示意性剖面图。
图3是表示第一实施方式的半导体装置的制造工序的示意性剖面图。
图4是表示第一实施方式的半导体装置的制造工序的示意性剖面图。
图5是表示第一实施方式的半导体装置的制造工序的示意性剖面图。
图6是表示第一实施方式的半导体装置的制造工序的示意性剖面图。
图7是表示第一实施方式的半导体装置的制造工序的示意性剖面图。
图8是表示本发明的半导体装置的第一实施方式的N型MOS晶体管的第一变形例的示意性剖面图。
图9是表示本发明的半导体装置的第一实施方式的N型MOS晶体管的第二变形例的示意性剖面图。
图10是表示本发明的半导体装置的第一实施方式的N型MOS晶体管的第三变形例的示意性剖面图。
图11是表示本发明的半导体装置的第二实施方式的N型MOS晶体管的示意性剖面图。
图12是表示本发明的半导体装置的第三实施方式的P型MOS晶体管的示意性剖面图。
图13是表示本发明的半导体装置的第三实施方式的P型MOS晶体管的变形例的示意性剖面图。
图14是表示本发明的第四实施方式的N型MOS晶体管的示意性剖面图。
[符号的说明]
10、20、30、40、50、80：N型MOS晶体管
60、70：P型MOS晶体管
100：半导体基板
101：P型低浓度扩散层
102、102A、102B：N型低浓度扩散层
103、103A、103B：N型高浓度扩散层
104：栅极氧化膜
105：栅极电极
106A：N型源极扩散层
106B：N型漏极扩散层
107A：N型源极LDD扩散层
107B：N型漏极LDD扩散层
108：P型中浓度区域
109A、109B、109C：抗蚀剂膜
110：场氧化膜
201：N型低浓度扩散层
202：P型低浓度扩散层
203：P型高浓度扩散层
206A：P型源极扩散层
206B：P型漏极扩散层
207A：P型源极LDD扩散层
207B：P型漏极LDD扩散层
208：N型中浓度区域
具体实施方式
以下，使用图示来说明发明的实施方式。另外，以下，在仅记为漏极的情况下，是指包括漏极扩散层、包含与漏极扩散层相同的导电型的杂质层的结构，在仅记为源极的情况下，是指包括源极扩散层、包含与源极扩散层相同的导电型的杂质层的结构。
＜第一实施方式＞
图1是表示本发明的半导体装置的第一实施方式的N型MOS晶体管10的示意性剖面图。
N型MOS晶体管10包括：半导体基板100；自半导体基板100的表面至内部配置的第二导电型(本实施方式中为P型)的低浓度扩散层101；在半导体基板100的表面隔着栅极氧化膜104配置的栅极电极105；配置在位于栅极电极105的一侧的半导体基板100的表面的第一导电型(本实施方式中为N型)的源极扩散层106A及在位于栅极电极105的另一侧的半导体基板100的表面与栅极电极105隔开配置的第一导电型的漏极扩散层106B；自栅极电极105的一端、即漏极扩散层106B侧的端部的正下方起，在与漏极扩散层106B之间配置的第一导电型的漏极LDD扩散层107B；设置成自相对于栅极电极105较漏极LDD扩散层107B的源极侧的端部更靠近漏极侧的位置起，在内部包含漏极扩散层106B，在垂直方向上自半导体基板100的表面至较漏极扩散层106B的底部更深的位置设置的第一导电型的高浓度扩散层103；以及设置成自处于栅极电极105的下方的半导体基板100的表面起，在内部包含漏极LDD扩散层107B、高浓度扩散层103、漏极扩散层106B的第一导电型的低浓度扩散层102。漏极LDD扩散层107B的杂质浓度高于第一导电型的低浓度扩散层102的杂质浓度，低于第一导电型的高浓度扩散层103的杂质浓度，因此还能够称为中浓度。
进而，在N型MOS晶体管10中，自作为栅极电极105的另一端的源极扩散层侧的端部的正下方起，在与源极扩散层106A之间配置有源极LDD扩散层107A。因此，源极扩散层106A与栅极电极105的另一端隔开配置。在源极LDD扩散层107A与漏极LDD扩散层107B之间，且在成为栅极电极105的下方的第二导电型的低浓度扩散层101的半导体基板的表面附近的区域引起通道(channel)。此外，还能够不配置与所述源极扩散层106A接触的源极LDD扩散层107A，关于不配置的情况，作为变形例在后面叙述。
在半导体基板100与低浓度扩散层101具有相同的导电型的情况下，可将两者同等看待。即为将半导体基板100本身看作低浓度扩散层101的情况。
图中使用的N--、N-、N+、N++及P--、P-、P+、P++的记号表示扩散至某个区域的杂质的相对浓度的大小。即，N型杂质的浓度以N--、N-、N+、N++的顺序变高，P型杂质的浓度以P--、P-、P+、P++的顺序变高。
通过采用所述结构，能够自通道朝向漏极扩散层阶段性地形成浓度梯度，因此与现有技术相比，可使通道附近的杂质浓度变淡，使漏极扩散层附近的杂质浓度变浓。因此，可缓和通道附近的电场，强化耐压，且抑制热载流子引起的劣化，进而降低漏极扩散层附近的电阻，实现高的ESD耐性。
接下来，对图1所示的N型MOS晶体管10的制造方法进行说明。图2至图7是表示N型MOS晶体管10的制作工序的示意性剖面图。
首先，如图2所示，在半导体基板100上离子注入P型杂质，形成P型区域101。P型区域101还能够通过外延生长来形成。
接着，如图3所示附上抗蚀剂膜109A，以其为掩模离子注入N型杂质，并在抗蚀剂膜109A的剥离后进行热扩散，由此形成N型低浓度扩散层102。
接着，如图4所示，以成为N型低浓度扩散层102的内侧的区域开口的方式附上抗蚀剂膜109B，以其为掩模离子注入N型杂质，形成N型高浓度扩散层103。
P型低浓度扩散层101、N型低浓度扩散层102大多主要用作阱(well)，因此使所含的杂质在大范围内扩散，浓度也变淡。与此相对，N型高浓度扩散层103不施加用于阱的扩散的高温、长时间的热处理，因此能够均匀且减少热处理引起的偏差地形成扩散层。由此，如图1所示，通过所述N型高浓度扩散层103与通道的距离以及自N型高浓度扩散层103的端部至位于漏极扩散层106B的触点(contact)的距离，可使MOS晶体管的耐压大幅变化，因此使用结构偏差少的N型高浓度扩散层103在制作与内部元件的耐压的裕度少的情况下可使用的截止晶体管时特别有效。
接着，如图5所示形成栅极氧化膜104后，如图6所示形成栅极电极105。栅极电极105一般以多晶硅为主成分。
接着，如图7所示，使用将必要部分开口的抗蚀剂膜109C，离子注入N型杂质，由此形成N型的源极扩散层106A及漏极扩散层106B。
然后，返回到图1，如图1所示，以栅极电极105为掩模，离子注入N型杂质而形成N型的源极LDD扩散层107A及漏极LDD扩散层107B。源极LDD扩散层107A及漏极LDD扩散层107B也可自栅极电极105两侧的端部连续地形成至到达源极扩散层106A及漏极扩散层106B的表面为止。其原因在于，源极LDD扩散层107A及漏极LDD扩散层107B的杂质浓度高于N型低浓度扩散层102的杂质浓度，但低于N型高浓度扩散层103与N型的源极扩散层106A及漏极扩散层106B各自的杂质浓度。N型的源极LDD扩散层107A及漏极LDD扩散层107B的形成是临近晶片制造工序的结束的阶段，因此所施加的热处理少，伴随热扩散产生的特性的偏差少。因此，通过这两者具有的杂质的浓度，能够容易地调整元件耐压。
以下，虽省略图示，但通过贯通栅极电极105、源极扩散层106A及漏极扩散层106B上所设置的层间绝缘膜而形成触点，并形成金属配线、钝化膜，从而完成半导体装置。
图8是表示本发明的半导体装置的第一实施方式的N型MOS晶体管10的第一变形例即N型MOS晶体管20的示意性剖面图。与N型MOS晶体管10不同之处在于：在N型MOS晶体管20中，设置有覆盖源极扩散层106A及源极LDD扩散层107A并到达栅极电极105下的通道的P型中浓度区域108。
通过设置P型中浓度区域108，而使与源极扩散层106A及源极LDD扩散层107A接触的P型区域的杂质浓度较P型低浓度扩散层101更高，由此能够削减流入至源极扩散层106A及源极LDD扩散层107A的漏电流。进而，由于P型中浓度区域108仅设置在源极侧，因此漏极侧的杂质分布不变化。因此，N型MOS晶体管20可保持与第一实施方式的N型MOS晶体管10同等的ESD耐压。
图9是表示本发明的半导体装置的第一实施方式的N型MOS晶体管10的第二变形例即N型MOS晶体管30的示意性剖面图。在N型MOS晶体管30中未设置N型MOS晶体管10中，在自源极扩散层106A到达栅极电极105的正下方的区域设置的源极LDD扩散层107A。进而，源极扩散层106A与栅极电极105的端部的正下方接触设置。在源极扩散层106A的附近，在电场强度不会显著增大的情况下，可如上所述省略源极LDD扩散层107A，将源极扩散层106A配置在栅极电极105的端部的正下方。通过所述方式，能够缩小N型MOS晶体管30的沿着通道的方向的尺寸。
图10是表示本发明的半导体装置的第一实施方式的N型MOS晶体管10的第三变形例即N型MOS晶体管40的示意性剖面图。与N型MOS晶体管10的不同之处在于：在N型MOS晶体管40中，并无在自源极扩散层106A到达栅极电极105的正下方的区域设置的源极LDD扩散层107A；以及设置有覆盖源极扩散层106A并到达栅极电极105下的通道的P型中浓度区域108。
在N型MOS晶体管40中，通过设置P型中浓度区域108，与作为第一变形例的N型MOS晶体管20同样，能够削减流入至源极扩散层106A的漏电流。进而，由于并无源极LDD扩散层107A，因此可将源极扩散层106A配置在栅极电极105的端部的正下方，能够缩小N型MOS晶体管40的沿着通道的方向的尺寸。
＜第二实施方式＞
图11是表示本发明的半导体装置的第二实施方式的N型MOS晶体管50的示意性剖面图。
N型MOS晶体管50的漏极与源极的结构相同，且对称。即，在第一实施方式的N型MOS晶体管10中，源极与漏极的结构不同，不对称，但通过使包围源极扩散层106A的源极的结构与漏极的结构相等，来构成N型MOS晶体管50。
具体而言，N型MOS晶体管50包括：半导体基板100；自半导体基板100的表面至内部配置的第二导电型(本实施方式中为P型)的低浓度扩散层101；隔着栅极氧化膜104配置在半导体基板100的表面的栅极电极105；在位于栅极电极105的一侧的半导体基板100的表面与栅极电极105隔开配置的第一导电型(本实施方式中为N型)的源极扩散层106A及在位于栅极电极105的另一侧的半导体基板100的表面与栅极电极105隔开配置的第一导电型的漏极扩散层106B；自栅极电极105的一端即漏极扩散层106B侧的端部的正下方起，在与漏极扩散层106B之间配置的第一导电型的漏极LDD扩散层107B以及自栅极电极105的另一端即源极扩散层106A侧的端部的正下方起，在与源极扩散层106A之间配置的第一导电型的源极LDD扩散层107A；自相对于栅极电极105较漏极LDD扩散层107B更靠近漏极侧的位置至漏极扩散层106B设置，在垂直方向上自半导体基板100的表面至较漏极扩散层106B的底部更深的位置设置的第一导电型的高浓度扩散层103B以及自相对于栅极电极105较源极LDD扩散层107A更靠近源极侧的位置至源极扩散层106A设置，在垂直方向上自半导体基板100的表面至较源极扩散层106A的底部更深的位置设置的第一导电型的高浓度扩散层103A；以及设置成自处于栅极电极105的下方的半导体基板100的表面起，在内部包含漏极LDD扩散层107B、高浓度扩散层103B、漏极扩散层106B的第一导电型的低浓度扩散层102B及设置成自处于栅极电极105的下方的半导体基板100的表面起，在内部包含源极LDD扩散层107A、高浓度扩散层103A、源极扩散层106A的第一导电型的低浓度扩散层102A。
N型MOS晶体管50的漏极与源极的结构相同，且对称，因此能够调换源极与漏极来使用。
＜第三实施方式＞
图12是表示本发明的半导体装置的第三实施方式的P型MOS晶体管60的示意性剖面图。P型MOS晶体管60是在第一实施方式的N型MOS晶体管10中将全部区域的导电型替换为相反的导电型的晶体管。即，在N型MOS晶体管10中，将P型区域设为N型区域，将N型区域设为P型区域。
P型MOS晶体管60包括：半导体基板100；自半导体基板100的表面至内部配置的第二导电型(本实施方式中为N型)的低浓度扩散层201；在半导体基板100的表面隔着栅极氧化膜104配置的栅极电极105；配置在位于栅极电极105的一侧的半导体基板100的表面的第一导电型(本实施方式中为P型)的源极扩散层206A及在位于栅极电极105的另一侧的半导体基板100的表面与栅极电极105隔开配置的第一导电型的漏极扩散层206B；自栅极电极105的一端、即漏极扩散层206B侧的端部的正下方起，在与漏极扩散层206B之间配置的第一导电型的漏极LDD扩散层207B；自相对于栅极电极105较漏极LDD扩散层207B更靠近漏极侧的位置至漏极扩散层206B设置，在垂直方向上自半导体基板100的表面至较漏极扩散层206B的底部更深的位置设置的第一导电型的高浓度扩散层203；以及设置成自处于栅极电极105的下方的半导体基板100的表面起，在内部包含漏极LDD扩散层207B、高浓度扩散层203、漏极扩散层206B的第一导电型的低浓度扩散层202。进而，自作为栅极电极105的另一端的源极扩散层侧的端部的正下方起，在与源极扩散层206A之间配置有源极LDD扩散层207A。
P型MOS晶体管60容易像漏极间电压(Voltage Drain-to-Drain，VDD)等那样，作为将电源电压高的一侧施加到源极的电压，与N型MOS晶体管10等一起组合使用。
图13是表示本发明的半导体装置的第三实施方式的P型MOS晶体管60的变形例即P型MOS晶体管70的示意性剖面图。与P型MOS晶体管60不同之处在于：在P型MOS晶体管70中，还设置有覆盖源极扩散层206A及源极LDD扩散层207A并到达栅极电极105下的通道的N型中浓度区域208。
P型MOS晶体管70相对于图12所示的P型MOS晶体管60而言的特征与N型MOS晶体管20相对于图1所示的N型MOS晶体管10而言的特征相同，能够在保持ESD耐压的状态下削减漏电流。
＜第四实施方式＞
图14是表示本发明的半导体装置的第四实施方式的N型MOS晶体管80的示意性剖面图。
N型MOS晶体管80与作为第一实施方式的第一变形例而说明的N型MOS晶体管20的不同之处在于，在自通道中途到达漏极扩散层106B的半导体基板100的表面具有较栅极氧化膜104更厚的场氧化膜110。另一方面，关于设置在第一导电型(此处为N型)的源极扩散层106A周围的第一导电型的源极LDD扩散层107A及第二导电型(此处为P型)的中浓度区域108、设置在漏极扩散层106B周围的第一导电型的低浓度扩散层102、第一导电型的高浓度扩散层103、及第一导电型的漏极LDD扩散层107B，本质上相同。
栅极电极105设置为不仅延伸至栅极氧化膜104上，而且延伸至场氧化膜110上。由此，栅极电极105的漏极扩散层侧的端部与漏极LDD扩散层107B的源极扩散层侧的端部不需要在自垂直于半导体基板表面的方向俯视观察时接触。另外，关于第一导电型的低浓度扩散层102，若半导体基板的表面中的源极扩散层侧的边界面还会位于场氧化膜110之下，则还会位于栅极氧化膜104之下。
在N型MOS晶体管80的结构中，在栅极电极105与设置在漏极扩散层106B周围的多个第一导电型的扩散层之间存在场氧化膜110，因此可提高栅极与漏极之间的耐压，特别是使N型MOS晶体管80关断时的耐压提高。
N型MOS晶体管80具有源极LDD扩散层107A及第二导电型的中浓度区域108，但不具有它们中的任一者或这两者的结构也与所述第一实施方式中说明的同样，能够容易地实施。
另外，还容易构成相对于N型MOS晶体管80，将含有杂质的扩散层的导电型全部调换的P型MOS晶体管。

Claims (9)

1.一种半导体装置，包括：
半导体基板；
第二导电型的低浓度扩散层，设置在所述半导体基板；
栅极电极，隔着栅极氧化膜设置在所述第二导电型的低浓度扩散层的表面；
第一导电型的源极扩散层及第一导电型的漏极扩散层，所述第一导电型的源极扩散层设置在位于所述栅极电极的一侧的所述半导体基板的表面，所述第一导电型的漏极扩散层在位于所述栅极电极的另一侧的所述半导体基板的表面，与所述栅极电极隔开地设置；
第一导电型的漏极LDD扩散层，设置在所述半导体基板的表面且位于所述漏极扩散层与所述栅极电极的所述漏极扩散层侧的端部的正下方之间；
第一导电型的高浓度扩散层，设置成自较所述漏极LDD扩散层的所述源极扩散层侧的端部更靠近所述漏极扩散层的位置起包含所述漏极扩散层，相较于所述漏极LDD扩散层而言杂质浓度高，且相较于所述漏极扩散层而言杂质浓度低；以及
第一导电型的低浓度扩散层，设置成自成为所述栅极电极的下方的所述半导体基板的表面起，在内部包含所述漏极LDD扩散层、所述高浓度扩散层及所述漏极扩散层，相较于所述漏极LDD扩散层而言杂质浓度低。
2.根据权利要求1所述的半导体装置，还包括：第二导电型的中浓度区域，覆盖所述源极扩散层，到达所述栅极电极下的通道。
3.根据权利要求1所述的半导体装置，还包括：第一导电型的源极LDD扩散层，设置在所述源极扩散层与通道之间的所述半导体基板的表面。
4.根据权利要求3所述的半导体装置，还包括：第二导电型的中浓度区域，覆盖所述源极扩散层及所述源极LDD扩散层，到达所述栅极电极下的通道。
5.一种半导体装置，包括：
半导体基板；
第二导电型的低浓度扩散层，自所述半导体基板的表面至内部设置；
第一导电型的源极扩散层及第一导电型的漏极扩散层，在成为所述第二导电型的低浓度扩散层的内侧的所述半导体基板的表面空开间隔地设置；
场氧化膜，自所述源极扩散层及所述漏极扩散层之间的地点至所述漏极扩散层的端部设置；
栅极氧化膜，在所述第二导电型的低浓度扩散层的表面，自所述场氧化膜的所述源极侧的端部至所述源极扩散层的端部设置；
栅极电极，设置成覆盖所述栅极氧化膜与所述场氧化膜的一部分；
第一导电型的漏极LDD扩散层，设置在所述场氧化膜下的所述半导体基板的表面；
第一导电型的高浓度扩散层，设置成自较所述漏极LDD扩散层的所述源极扩散层侧的端部更靠近所述漏极扩散层的位置起包含所述漏极扩散层，相较于所述漏极LDD扩散层而言杂质浓度高，且相较于所述漏极扩散层而言杂质浓度低；以及
第一导电型的低浓度扩散层，设置成自成为所述栅极电极的下方的所述半导体基板的表面起，在内部包含所述漏极LDD扩散层、所述高浓度扩散层及所述漏极扩散层，相较于所述漏极LDD扩散层而言杂质浓度低。
6.根据权利要求5所述的半导体装置，还包括：第二导电型的中浓度区域，覆盖所述源极扩散层，到达所述栅极电极下的通道。
7.根据权利要求5所述的半导体装置，还包括：第一导电型的源极LDD扩散层，设置在所述源极扩散层与通道之间的所述半导体基板的表面。
8.根据权利要求7所述的半导体装置，还包括：第二导电型的中浓度区域，覆盖所述源极扩散层及所述源极LDD扩散层，到达所述栅极电极下的通道。
9.一种半导体装置的制造方法，其特征在于，包括：
在半导体基板上离子注入第二导电型的杂质的工序；
离子注入第一导电型的杂质，通过热扩散来形成低浓度扩散层的工序；
离子注入第一导电型的杂质，形成高浓度扩散层的工序；
形成栅极氧化膜的工序；
形成栅极电极的工序；
离子注入第一导电型的杂质，形成源极扩散层及漏极扩散层的工序；以及
离子注入第一导电型的杂质，形成作为中浓度扩散层的LDD扩散层的工序。
CN202110302505.3A 2020-03-31 2021-03-22 半导体装置及半导体装置的制造方法 Pending CN113471286A (zh)

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