CN113463055B - 基板托盘 - Google Patents

基板托盘 Download PDF

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CN113463055B
CN113463055B CN202110325079.5A CN202110325079A CN113463055B CN 113463055 B CN113463055 B CN 113463055B CN 202110325079 A CN202110325079 A CN 202110325079A CN 113463055 B CN113463055 B CN 113463055B
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吉河训太
入江畅
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Abstract

本发明提供一种减少因半导体基板的翘曲而引起的成膜时的成膜气体的背绕的基板托盘。基板托盘(1)对方形形状或半方形形状的基板(W)进行保持，上述基板托盘具有收容基板(W)的由方形形状的凹陷构成的凹兜(10)。凹兜(10)的底从凹兜(10)的四个侧壁(20)侧朝向凹兜(10)的内侧依次具有周底部(31)与中央底部(33)。周底部(31)比中央底部(33)浅，并对基板(W)的四个边部的背面进行支承，上述周底部在沿着凹兜(10)的侧壁(20)的方向上，以从凹兜(10)的拐角之间的中央朝向拐角逐渐变浅的方式弯曲。

Description

基板托盘
技术领域
本发明涉及基板托盘。
背景技术
例如，在太阳能电池单元的制造工序，特别是使用了CVD(Chemical VaporDeposition：化学气相沉积)法或PVD(Physical Vapor Deposition：物理气相沉积)法等的半导体层或TCO(Transparent Conductive Oxide：透明导电氧化物)层等的成膜工序中，使用对方形(Square：四边)形状或半方形(Semi-square：切割四边形状的四角而成的八边)形状的半导体基板(半导体晶片)进行保持的基板托盘。作为这样的基板托盘，在专利文献1中公开了凹兜类型的基板托盘，在专利文献2中公开了销类型的基板托盘。
专利文献1：日本特开2016-192453号公报
专利文献2：日本特开2014-118631号公报
在销类型的基板托盘中，在半导体基板的角以外设置销，由此对半导体基板进行保持，因此所谓的成膜时的成膜气体的背绕(成膜气体绕入半导体基板的与成膜面相反一侧的背面侧，使半导体基板的背面侧也被成膜)的抑制效果较低。
另一方面，在凹兜类型的基板托盘中，在由方形形状的凹陷构成的凹兜收容半导体基板，因此成膜时的成膜气体的背绕的抑制效果较高。但是，即便在凹兜类型的基板托盘中，也因自重而导致半导体基板翘曲，由此存在导致成膜时的成膜气体的背绕增加的情况。
发明内容
本发明的目的在于，提供一种在凹兜类型的基板托盘中，减少因半导体基板的翘曲而引起的成膜时的成膜气体的背绕的基板托盘。
本发明所涉及的基板托盘对方形形状或半方形形状的基板进行保持，该基板托盘具有收容上述基板的由方形形状的凹陷构成的凹兜。上述凹兜的底从上述凹兜的四个侧壁侧朝向上述凹兜的内侧依次具有周底部与中央底部。上述周底部比上述中央底部浅，并对上述基板的四个边部的背面进行支承，上述周底部在沿着上述凹兜的上述侧壁的方向上，以从上述凹兜的拐角之间的中央朝向上述拐角逐渐变浅的方式弯曲。
根据本发明，在凹兜类型的基板托盘中，能够减少因半导体基板的翘曲而引起的成膜时的成膜气体的背绕。
附图说明
图1是表示本实施方式所涉及的基板托盘的俯视图。
图2是放大表示图1所示的基板托盘中的II部分(凹兜)的俯视图。
图3是图2所示的基板托盘的凹兜的一个例子的立体图。
图4是将图2所示的基板托盘的凹兜的一个例子中的IVA-IVA线端面(一半)、IVB-IVB线端面(一半)、IVC-IVC线端面(一半)、IVD-IVD线端面(一半)、IVE-IVE线端面(一半)以及IVF-IVF线端面(一半)重叠而表示的图。
图5是半导体基板的一个例子的翘曲(挠曲)特性的模拟结果。
图6是半导体基板的边部的支承位置处的、半导体基板的一个例子的边部的翘曲(挠曲)特性的模拟结果。
图7是表示图6中的半导体基板的边部的支承位置的图。
附图标记说明
1…基板托盘；10…凹兜；20…侧壁；31…周底部；33…中央底部。
具体实施方式
以下，参照附图对本发明的实施方式的一个例子进行说明。此外，对各附图中相同或相当的部分标注相同的附图标记。另外，为了方便起见，也存在省略阴影线、部件附图标记等的情况，在这种情况下，参照其他附图。
图1是表示本实施方式所涉及的基板托盘的俯视图。图1所示的基板托盘1是例如在太阳能电池单元的制造工序，特别是使用了CVD法或PVD法等的半导体层或TCO层等的成膜工序中，对方形形状或半方形形状的半导体基板(半导体晶片)进行保持的基板托盘。作为基板托盘1的材料，没有特别限定，例如能够列举铝。基板托盘1具有收容半导体基板的由方形形状的凹陷构成的多个凹兜10。多个凹兜10例如排列成二维状。
图2是放大表示图1所示的基板托盘中的凹兜(II部分)的俯视图。图3是图2所示的基板托盘的凹兜的一个例子的立体图，图4是将图2所示的基板托盘的凹兜的一个例子中的IVA-IVA线端面(一半)、IVB-IVB线端面(一半)、IVC-IVC线端面(一半)、IVD-IVD线端面(一半)、IVE-IVE线端面(一半)以及IVF-IVF线端面(一半)重叠而表示的图。
如图2～图4所示，凹兜10具有四个侧壁20。凹兜10的底从四个侧壁20朝向凹兜10的内侧依次具有周底部31与中央底部33。在凹兜10的与底相反的一侧具有用于收容或取出半导体基板W的开口。
周底部31比中央底部33浅，对半导体基板W的周缘部，即四个边部的背面进行支承。周底部31以从四个侧壁20朝向凹兜10的内侧逐渐变深的方式倾斜。
这里，图5表示半导体基板W的一个例子(6英寸×170μm(厚度))的翘曲(挠曲)特性的模拟结果。如图5所示，半导体基板W存在因自重而三维地翘曲(挠曲)的情况。在图5中，半导体基板W的边部的中央部位于150μm～175μm的范围，与此相对，半导体基板W的角部位于200μm～225μm的范围。根据本申请发明人(们)的见解，例如在6英寸×170μm(厚度)的半导体基板W中，相对于半导体基板W的边部的中央部，半导体基板W的角部存在翘曲(挠曲)40μm～70μm左右的情况。
与此相对，若基板托盘的凹兜的周底部的沿着侧壁的方向的高度均匀，则半导体基板W的边部的中央部被支承，从而导致半导体基板W的角部浮起。于是，导致产生成膜时的成膜气体的背绕。
关于该点，在本实施方式中，将周底部31形成追随半导体基板W的翘曲(挠曲)的形状。具体而言，如图3及图4所示，周底部31在沿着侧壁20的方向上以从凹兜10的拐角之间的中央朝向拐角逐渐变浅的方式弯曲。
换言之，从凹兜10的拐角之间的中央朝向拐角，周底部31的从四个侧壁20朝向凹兜10的内侧的倾斜逐渐变陡。
这里，图6表示半导体基板W的边部的支承位置处的、半导体基板W的一个例子(6英寸×170μm(厚度))的边部的翘曲(挠曲)特性的模拟结果(四边的平均值)。如图6所示，在仅对半导体基板W的角部(图7的G)的背面进行支承时，半导体基板W的四个边部的翘曲(挠曲)成为最大(曲线G)，仅对半导体基板W的四个边部的中央部(图7的H)的背面进行支承时的半导体基板W的四个边部的翘曲(挠曲)成为最小(曲线H)。
关于该点，在本实施方式中，周底部31的沿着侧壁20的方向的弯曲比仅对半导体基板W的角部的背面进行支承时的半导体基板W的四个边部的翘曲(挠曲)的弯曲平缓，且比仅对半导体基板W的四个边部的中央部的背面进行支承时的半导体基板W的四个边部的翘曲(挠曲)的弯曲陡。
如以上说明的那样，根据本实施方式的基板托盘1，凹兜10中的、对半导体基板W的四个边部的背面进行支承的周底部31在沿着凹兜10的侧壁20的方向上，以从凹兜10的拐角之间的中央朝向拐角逐渐变浅的方式弯曲。即，凹兜10的周底部31是追随凹兜10的边部的翘曲(挠曲)的形状。由此，能够减少因半导体基板的翘曲而引起的半导体基板W的角部的浮起，从而能够减少成膜时的成膜气体的背绕。
另外，根据本实施方式的基板托盘1，凹兜10的周底部31的沿着侧壁20的方向的弯曲比仅对半导体基板W的角部的背面进行支承时的半导体基板W的四个边部的翘曲的弯曲平缓，且比仅对半导体基板W的四个边部的中央部的背面进行支承时的半导体基板W的四个边部的翘曲的弯曲陡。即，周底部31的沿着侧壁20的方向的弯曲被设定为图5所示的半导体基板W的四个边部的翘曲(挠曲)的最大与最小之间。由此，能够进一步减少因半导体基板的翘曲而引起的半导体基板W的角部的浮起，从而能够进一步减少成膜时的成膜气体的背绕。
另外，根据本实施方式的基板托盘1，凹兜10的周底部31以从四个侧壁20朝向凹兜10的内侧变深的方式倾斜。由此，能够仅对半导体基板W的周缘部的背面进行支承，从而能够抑制半导体基板W的周缘部以外的背面与凹兜10的底接触，进而能够抑制太阳能电池的性能降低。
另外，使中央底部33变深，由此即使半导体基板W产生翘曲，也能够抑制半导体基板W的背面与凹兜10的底接触。
另外，使周底部31逐渐变深，由此能够减小半导体基板W的周缘部的背面侧的空间。这样，若半导体基板W的周缘部的背面侧的空间较小，则能够减少成膜时的成膜气体的背绕。
以上，对本发明的实施方式进行了说明，但本发明并不限定于上述实施方式，能够进行各种变更及变形。例如，在上述实施方式中，例示了在太阳能电池的制造工序，特别是使用了CVD法或PVD法等的半导体层或TCO层等的成膜工序中使用的基板托盘。但是，本发明并不限定于此，能够应用于对方形形状或半方形形状的各种基板进行保持的基板托盘。

Claims (2)

1.一种基板托盘，其对方形形状或半方形形状的基板进行保持，
所述基板托盘的特征在于，
具有收容所述基板的由方形形状的凹陷构成的凹兜，
所述凹兜的底从所述凹兜的四个侧壁侧朝向所述凹兜的内侧依次具有周底部与中央底部，
所述周底部比所述中央底部浅，并对所述基板的四个边部的背面进行支承，
所述周底部在沿着所述凹兜的所述侧壁的方向以从所述凹兜的拐角之间的中央朝向所述拐角逐渐变浅的方式弯曲，
所述周底部以从四个所述侧壁侧朝向所述凹兜的内侧逐渐变深的方式倾斜，
从所述凹兜的拐角之间的中央朝向所述拐角，所述周底部的从四个所述侧壁侧朝向所述凹兜的内侧的倾斜逐渐变陡。
2.根据权利要求1所述的基板托盘，其特征在于，
所述周底部的沿着所述侧壁的方向的弯曲比仅对所述基板的角部的背面进行支承时的所述基板的四个边部的翘曲的弯曲平缓，且比仅对所述基板的四个边部的中央部的背面进行支承时的所述基板的四个边部的翘曲的弯曲陡。
CN202110325079.5A 2020-03-31 2021-03-26 基板托盘 Active CN113463055B (zh)

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CN1774794A (zh) * 2003-04-14 2006-05-17 信越半导体株式会社 衬托器和气相生长装置
JP2008081269A (ja) * 2006-09-28 2008-04-10 Dainippon Printing Co Ltd 板状物の受け取り方法および板状物の受け取り装置
CN109423626A (zh) * 2017-08-30 2019-03-05 胜高股份有限公司 成膜装置、成膜用托盘、成膜方法、成膜用托盘的制造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4030926B2 (ja) 2003-06-12 2008-01-09 株式会社日本製鋼所 基板の位置決め方法及びその装置
JP2006041028A (ja) 2004-07-23 2006-02-09 Komatsu Electronic Metals Co Ltd サセプタ、およびエピタキシャルウェーハの製造方法
JP5429257B2 (ja) 2006-10-16 2014-02-26 大日本印刷株式会社 板状物用トレイと板状物の積層方法
JP2013071742A (ja) 2011-09-27 2013-04-22 Toppan Printing Co Ltd 板状物用トレイ
JP2016192453A (ja) 2015-03-30 2016-11-10 株式会社カネカ 基板ホルダおよびそれを用いた太陽電池の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1774794A (zh) * 2003-04-14 2006-05-17 信越半导体株式会社 衬托器和气相生长装置
JP2008081269A (ja) * 2006-09-28 2008-04-10 Dainippon Printing Co Ltd 板状物の受け取り方法および板状物の受け取り装置
CN109423626A (zh) * 2017-08-30 2019-03-05 胜高股份有限公司 成膜装置、成膜用托盘、成膜方法、成膜用托盘的制造方法

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