CN113380744B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN113380744B
CN113380744B CN202010934734.2A CN202010934734A CN113380744B CN 113380744 B CN113380744 B CN 113380744B CN 202010934734 A CN202010934734 A CN 202010934734A CN 113380744 B CN113380744 B CN 113380744B
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resin
semiconductor
semiconductor device
wiring substrate
chip
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CN113380744A (zh
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菅生悠树
天野彩那
服部圭一郎
渡部武志
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Kioxia Corp
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Kioxia Corp
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Abstract

实施方式的半导体装置具备：配线衬底；半导体芯片，搭载在配线衬底上；含树脂层，粘接于配线衬底以将半导体芯片固定在配线衬底上。含树脂层包含125℃下的破坏强度为15MPa以上的含树脂材。

Description

半导体装置
[相关申请案]
本申请案享有以日本专利申请案2020-39951号(申请日：2020年3月9日)为基础申请案的优先权。本申请案通过参考该基础申请案而包含基础申请案的全部内容。
技术领域
此处公开的实施方式涉及一种半导体装置。
背景技术
为了实现半导体装置的小型化、高速化、高功能化等，使具有在1个封装体内积层密封着多个半导体芯片的构造的半导体存储装置等半导体封装体实用化。半导体存储装置具备如下构造：例如在配线衬底上嵌埋控制器芯片，并且粘接FOD(Film On Device，装置上薄膜)材，且在FOD材上多级地积层存储器芯片。在构成这种半导体存储装置的半导体装置中，存储器芯片的积层数增加，以诸如16级、24级、32级的个数积层存储器芯片。在具有多级积层的半导体芯片的半导体装置中，担心粘接在配线衬底上的FOD材产生龟裂，使衬底配线断裂而产生不良，因此，要求抑制诸如FOD材这样的粘接层的龟裂。
发明内容
实施方式提供一种半导体装置，该半导体装置能够抑制将半导体芯片粘接在配线衬底上的粘接层的龟裂及由此引起的衬底配线的断裂等。
实施方式的半导体装置具备：配线衬底；半导体芯片，搭载在所述配线衬底上；以及含树脂层，粘接于所述配线衬底以将所述半导体芯片固定在所述配线衬底上；且所述含树脂层包含125℃下的破坏强度为15MPa以上的含树脂材。
附图说明
图1是表示第1实施方式的半导体装置的剖视图。
图2是放大表示图1所示的半导体装置的一部分的剖视图。
图3是表示作为实施方式的含树脂层的含树脂材(试样1、2)及作为比较例的含树脂材(试样3、4)的拉伸试验结果的图。
图4是表示具有包含试样1的含树脂层的半导体装置循环1000次TCT(ThermalCycling Test，热循环试验)试验后的配线衬底的状态的图。
图5是表示具有包含试样2的含树脂层的半导体装置循环1000次TCT试验后的配线衬底的状态的图。
图6是表示具有包含试样3的含树脂层的半导体装置循环1000次TCT试验后的配线衬底的状态的图。
图7是表示具有包含试样4的含树脂层的半导体装置循环1000次TCT试验后的配线衬底的状态的图。
图8是表示第1实施方式的半导体装置的变化例的剖视图。
图9是表示第2实施方式的半导体装置的剖视图。
具体实施方式
以下，参照附图对实施方式的半导体装置进行说明。此外，各实施方式中，对实质上相同的构成部位标附相同符号，有时省略一部分说明。附图是示意性的图，存在厚度与平面尺寸的关系、各部分的厚度比率等与实物不同的情况。在没有特别明确记载的情况下，说明中的上下等表示方向的术语表示将以下所述的衬底的半导体芯片搭载面设为上时的相对方向，有时与以重力加速度方向为基准的实际方向不同。
(第1实施方式)
图1是表示第1实施方式的半导体装置的剖视图。图1所示的半导体装置1具备：配线衬底2；第1半导体芯片3，搭载在配线衬底2上；含树脂层(FOD)4，嵌埋第1半导体芯片3并固定在配线衬底2上；硅制或树脂制间隔芯片5，搭载在含树脂层4上；多个第2半导体芯片6的积层体7，搭载在间隔芯片5上；以及密封树脂层8，以密封第1半导体芯片3及第2半导体芯片6的积层体7等的方式设置在配线衬底2上。
配线衬底2具有配线网，该配线网由设置在例如绝缘性树脂衬底或绝缘性陶瓷衬底等的表面的配线层9及设置在内部的配线层10等构成，具体可列举使用诸如玻璃-环氧树脂这类绝缘树脂的印刷配线板等。配线层9、10例如包含铜或铜合金、金或金合金等金属材料。配线衬底2具有成为外部端子的形成面等的第1面2a、及成为半导体芯片3、6的搭载面的第2面2b。
在配线衬底2的第2面2b上搭载着第1半导体芯片3，第1半导体芯片3嵌埋在含树脂层4内，并且搭载在配线衬底2的芯片搭载区域。含树脂层4的一部分粘接在配线衬底2上。第1半导体芯片3具有40μm左右的厚度，含树脂层4具有80～150μm左右的厚度，另外，视情况具有40～150μm左右的厚度。如下文所述，嵌埋第1半导体芯片3的含树脂层4包含125℃下的破坏强度为15MPa以上的含树脂材。构成含树脂层4的含树脂材(已硬化的含树脂材)是指用于形成含树脂层4的树脂组合物的硬化物。作为第1半导体芯片3，例如可列举在用作第2半导体芯片6的半导体存储器芯片与外部设备之间收发数字信号的控制器芯片或接口芯片、逻辑芯片、RF(radio frequency，射频)芯片等系统LSI(Large Scale Integration，大规模集成电路)芯片，但并不限定于这些。
图2是放大表示图1所示的半导体装置的一部分的剖视图。如图2所示，第1半导体芯片3具有电极3A，这些电极3A经由键合线11与配线衬底2的配线层9电连接。通过将控制器芯片等第1半导体芯片3直接搭载在配线衬底2上，能够缩短第1半导体芯片3与配线衬底2之间的配线长度。由此，能够谋求第1半导体芯片3与配线衬底2之间的信号传输速度的提高等，从而能够应对半导体装置1的高速化。进而，由于第1半导体芯片3嵌埋在含树脂层4内，所以不会降低第2半导体芯片6相对于配线衬底2的搭载性，或者妨碍封装体尺寸的小型化等。因此，能够提供小型且与高速装置对应的半导体装置1。
控制器芯片等第1半导体芯片3的外形形状通常比半导体存储器芯片等第2半导体芯片6的外形形状小。因此，将搭载在配线衬底2上的第1半导体芯片3嵌埋在含树脂层4内后，在含树脂层4上积层搭载多个第2半导体芯片6。作为第2半导体芯片6的具体例，可列举诸如NAND(Not AND，与非)型闪存这类半导体存储器芯片，但并不限于此。在第1实施方式中，积层搭载了16个半导体存储器芯片作为第2半导体芯片6。此外，第2半导体芯片6的积层数并不限于16级，也可为24级、32级等。
如图2所示，多个(例如16块以上)第2半导体芯片6分别具有沿着1个端部排列的电极6A。搭载在含树脂层4上的多个第2半导体芯片6中第1级到第4级的第2半导体芯片6以露出各自的电极6A的方式，沿第1方向(图中为纸面右方向)错开排列着电极6A的端部而呈阶梯状积层，构成第1积层部。第5级到第8级的第2半导体芯片6以露出各自的电极6A的方式，沿与第1方向为相反方向的第2方向(图中为纸面左方向)错开排列着电极6A的端部而呈阶梯状积层，构成第2积层部。第9级到第12级的第2半导体芯片6以露出各自的电极6A的方式，沿第1方向错开排列着电极6A的端部而呈阶梯状积层，构成第3积层部。第13级到第16级的第2半导体芯片6以露出各自的电极6A的方式，沿第2方向错开排列着电极6A的端部而呈阶梯状积层，构成第4积层部。
如图2所示，间隔芯片5固定粘着在含树脂层4上。多个第2半导体芯片6中第1级的第2半导体芯片6经由粘接层13固定粘着在间隔芯片5上。粘接层13使用普通的DAF(DieAttach Film，晶片粘结薄膜)等粘接剂。除第1级以外的第2半导体芯片6如图2所示通过由DAF等构成的粘接层13而固定粘着在位于下侧的第2半导体芯片6上。此外，配线衬底2与第1半导体芯片3之间也可以通过由DAF等构成的未图示的粘接层而固定粘着。第2半导体芯片6的电极6A经由键合线12与配线衬底2的配线层9电连接。关于电特性或信号特性相同的电极6A，能够以键合线12依次连接配线衬底2的配线层9与多个第2半导体芯片6的电极6A。第1级到第4级的第2半导体芯片6的电极6A由键合线12依次连接，且以键合线12连接第1级的第2半导体芯片6的电极6A与配线衬底2的配线层9。第5～8级的第2半导体芯片6、第9～12级的第2半导体芯片6、及第13～16级的第2半导体芯片6也同样如此。
多个第2半导体芯片6中第5级、第9级、及第13级的第2半导体芯片6中，分别排列着被线键合的电极6A的端部比位于各自的下侧的第2半导体芯片6突出。因此，第5级、第9级、及第13级的第2半导体芯片6的厚度设定得比除它们以外的第2半导体芯片6厚，以便不因线键合时施加的力而产生裂痕或破裂等。例如，第5级、第9级、及第13级的第2半导体芯片6具有55μm左右的厚度。除它们以外的第2半导体芯片6为了降低积层体7的厚度及基于其的半导体装置1的厚度，实现半导体装置1的薄型化，例如具有36μm左右的厚度。
在配线衬底2的第2面2b上，以将第1半导体芯片3及第2半导体芯片6的积层体7与键合线11、12等一并密封的方式，例如模铸成形有使用环氧树脂等绝缘树脂的密封树脂层8。由这些构成要素构成第1实施方式的半导体装置1。这种半导体装置1中，第1及第2半导体芯片3、6例如具有3ppm左右的线膨胀系数。配线衬底2例如具有20ppm左右的线膨胀系数。密封树脂层8例如具有10ppm左右的线膨胀系数。构成含树脂层4的含树脂材例如具有70ppm以下的线膨胀系数。半导体装置1例如具有1.3mm左右的厚度。
除如上所述的半导体装置1的构成材料间的线膨胀系数的差异以外，随着第2半导体芯片6的积层数增加，担心半导体装置1对热循环试验(TCT：Thermal Cycle Test)的耐受性降低。也就是说，由于配线衬底2与第2半导体芯片6的积层体7之间的线膨胀系数差等，因TCT的温度差而产生的应力会导致嵌埋有第1半导体芯片3的含树脂层4容易产生裂痕。这种情况随着第2半导体芯片6的积层数增加，第2半导体芯片6的合计厚度变厚，含树脂层4会越容易产生裂痕。应力集中在含树脂层4产生的裂痕的前端，使与裂痕相接的配线层9产生断裂(配线断开)而引起不良。
为了抑制含树脂层4的裂痕及由裂痕引起的配线层9的断裂(配线断开)，在第1实施方式的半导体装置1中，含树脂层4由125℃下的破坏强度为15MPa以上的含树脂材构成。半导体装置1的TCT是将例如-55℃×15分钟+125℃×15分钟这样的热循环设为1个循环，通过施加例如700个循环、进而1000个循环的这种热循环，来评估半导体装置1的可靠性。在这种半导体装置1的TCT中，通过由125℃下的破坏强度为15MPa以上的含树脂材构成含树脂层4，能够抑制基于因温度差而产生的应力在含树脂层4产生裂痕，进而因应力集中在裂痕的前端而导致配线层9产生断裂(配线断开)。也就是说，能够提高半导体装置1的可靠性。
具体地对含树脂层4在125℃下的破坏强度与半导体装置1的TCT中的裂痕产生的关系进行说明。此处，将包含作为热硬化树脂的环氧树脂组合物、作为用来片材化的高分子成分的丙烯酸系橡胶、及作为无机填充材的二氧化硅(氧化硅)粒子的混合组合物(环氧树脂-丙烯酸系橡胶混合组合物(硬化前组合物))的硬化物应用到含树脂层4中。此外，环氧树脂组合物包含酚系树脂作为硬化剂。于制备环氧树脂-丙烯酸系橡胶混合组合物时，通过改变环氧树脂的环氧基当量、作为硬化剂的酚系树脂的羟基当量、环氧树脂与酚系树脂的当量比、丙烯酸系橡胶的重量平均分子量、丙烯酸系橡胶的调配比率等，制作出125℃下的破坏强度不同的4个试样。对试样1、试样2、试样3、及试样4的硬化物实施拉伸试验，测定在125℃下拉伸时的破断强度。将测定结果示于图3中。此处所说的破坏强度表示125℃下的拉伸试验中的破断强度。
如图3所示，试样1的硬化物在125℃下的破断强度(破坏强度)为40MPa，试样2的硬化物在125℃下的破断强度(破坏强度)为23MPa。这些试样1、2的硬化物满足125℃下的破坏强度为15MPa以上这一条件，相当于实施例的含树脂层4(环氧树脂-丙烯酸系橡胶混合组合物的硬化物)。另一方面，试样3的硬化物在125℃下的破断强度(破坏强度)为12MPa，试样4的硬化物在125℃下的破断强度(破坏强度)为6MPa。这些试样3、4的硬化物不满足125℃下的破坏强度为15MPa以上这一条件，相当于实施方式的比较例的含树脂层(环氧树脂-丙烯酸系橡胶混合组合物的硬化物)。
使用所述试样1、试样2、试样3、及试样4，制作出图1所示的半导体装置1(实施例1、实施例2、比较例1、及比较例2)。半导体装置1是如上所述在配线衬底2上将第1半导体芯片3嵌埋并固定在含树脂层4中，并在含树脂层4上搭载16级第2半导体芯片6而成。进而，使用125℃下的破断强度(破坏强度)为15MPa的试样5，以同样的方式制作半导体装置1(实施例3)。在-55℃×15分钟+125℃×15分钟的条件下，对这些实施例1～3及比较例1～2的半导体装置实施TCT。针对各例实施700个循环的TCT后，评估含树脂层4有无裂痕。将含树脂层4未产生裂痕的半导体装置归为良品，将产生了裂痕的半导体装置归为次品。针对各例分别实施100个样品的TCT，分析不良比率。将结果示于表1中。另外，关于实施例1～2及比较例1～2的半导体装置，将1000个循环的TCT后的配线层的代表例示于图4至图7中。
表1
如表1所示，可知：具有由125℃下的破坏强度为15MPa以上的含树脂材构成的含树脂层4的半导体装置1(实施例1～3)在700个循环的TCT后含树脂层4均未产生裂痕，不良比率为0％。这点从图4及图5的配线层的平面照片来看也较明显，并未产生裂痕。另一方面，可知：具有由125℃下的破坏强度小于15MPa的含树脂材构成的含树脂层4的半导体装置1(比较例1～2)在700个循环的TCT后，含树脂层4产生了裂痕的样品均有所增加，可靠性较差。这点从图6及图7的配线层的平面照片来看也较明显，在含树脂层4产生了裂痕(图中以箭头表示)。
TCT后的半导体装置1的不良随着搭载在含树脂层4上的第2半导体芯片6的数量增加而容易产生。因此，实施方式对基于搭载在含树脂层4上的第2半导体芯片6的数量的厚度较厚的半导体装置1有效。具体来说，当第2半导体芯片6的积层体7的厚度(将半导体芯片6的合计厚度与用于粘接半导体芯片6的粘接层13的合计厚度相加所得的值)相对于半导体装置1的整体厚度为67％以上时，实施方式的半导体装置1有效地发挥作用，能够抑制含树脂层4的裂痕及由裂痕引起的衬底配线的破断。在第1实施方式中，对在嵌埋第1半导体芯片3的含树脂层4上搭载第2半导体芯片6的积层体7的情况进行了说明，但并不限于此。对于在配线衬底2上搭载第2半导体芯片6的积层体7的情况，当第2半导体芯片6的积层体相对于半导体装置1的厚度的比率为67％以上时，作为由125℃下的破坏强度为15MPa以上的含树脂材构成的含树脂层4的粘接层也有效地发挥作用。
作为用于形成含树脂层4的树脂组合物，例如使用含有热硬化性环氧树脂的组合物、含有聚酰亚胺树脂的组合物、含有丙烯酸系树脂的组合物、含有酚系树脂的组合物等。这些组合物中，适宜使用含有热硬化性环氧树脂的组合物。具体来说，包含作为热硬化树脂的环氧树脂组合物、作为高分子成分的丙烯酸系橡胶、及作为无机填充材的二氧化硅粒子、氧化铝粒子、氧化锆粒子等的混合组合物较为合适。关于这种混合组合物，例如能够通过应用如下所示的条件，将该硬化物在125℃下的破坏强度设为15MPa以上。混合组合物(树脂组合物)也可以除所述成分以外还包含一般的热硬化性粘接剂等中使用的硬化促进剂、各种添加剂、溶剂等。
作为环氧树脂，能够单独或并用双酚型环氧树脂、酚系酚醛清漆型环氧树脂、甲酚酚醛清漆型环氧树脂等。另外，也可使用多官能环氧树脂、含有杂环的环氧树脂、脂环式环氧树脂等通常已知的环氧树脂。环氧树脂的环氧基当量优选为150～2000g/eq，进而更优选为150～1000g/eq。通过使用环氧基当量相对较低的环氧树脂，与硬化剂的交联变得致密，从而能够提高包含环氧树脂的组合物的硬化物的破坏强度。
作为环氧树脂的硬化剂，能够使用酚系树脂。作为酚系树脂，能够单独或并用酚醛清漆型酚系树脂、可溶酚醛型酚系树脂等。酚系树脂的羟基当量优选为90～220g/eq，进而更优选为90～180g/eq。通过使用羟基当量相对较低的酚系树脂，与环氧树脂的交联变得致密，从而能够提高包含环氧树脂的组合物的硬化物的破坏强度。进而，环氧树脂与酚系树脂的当量比(环氧树脂的当量/酚系树脂的当量)优选为0.8～1.2。通过使用这种当量比的混合物，在环氧树脂的环氧基与酚系树脂的羟基的反应中，能够减少多余的官能基，由此有望提高硬化物的破坏强度。
树脂组合物中例如可含有丙烯酸系橡胶作为高分子成分。丙烯酸系橡胶的重量平均分子量优选为50万～100万，进而优选为65万～100万。通过使用分子量较高的丙烯酸系橡胶，能够期待高分子彼此的交联，有望提高破坏强度。另外，丙烯酸系橡胶优选包含交联性官能基。作为具有交联性官能基的官能性单体，能够使用丙烯酸缩水甘油酯、丙烯酸等。通过使丙烯酸系橡胶包含交联性官能基，有望与环氧树脂或酚系树脂进行交联反应，在材料间形成复合性结合，由此，有望提高破坏强度。
进而，在树脂组合物中，作为高分子成分的丙烯酸系橡胶的调配比率优选为1～20质量％。通过使丙烯酸系橡胶的调配比率相对较低，热硬化性环氧树脂与酚系树脂的调配比率相对提高，有望提高这些组合物的硬化物的破坏强度。另外，在树脂组合物中，环氧树脂、酚系树脂、及丙烯酸系橡胶的各成分间的溶解度参数(SP值)的差优选小于5.0，进而更优选小于3.0。通过使各材料的溶解度参数接近，在材料间形成复合性结合，由此，有望提高破坏强度。
树脂组合物中例如可含有无机化合物作为无机填充材。作为无机化合物，使用二氧化硅粒子、氧化铝粒子、氧化锆粒子等，但也可为除它们以外的无机化合物。在树脂组合物中，无机化合物的含量优选为30～65质量％，进而更优选为35～60质量％。通过调配这种含量的无机化合物，能够提高树脂组合物的硬化物(含树脂物)的破坏强度。
构成含树脂层4的树脂组合物的硬化物优选125℃下的破坏强度为15MPa以上，且线膨胀系数为70ppm以下。由此，含树脂层4与第1及第2半导体芯片3、6等的线膨胀系数差得以降低，进而能够更有效地抑制含树脂层4的裂痕。进而，含树脂层4优选与配线衬底2的构成材料即金等金属材料(配线材料)或树脂材料(绝缘材料)等的粘接强度为10MPa以上。由此，能够更有效地抑制含树脂层4的裂痕及基于其的衬底配线的破断。
含树脂层4优选具有40μm以上150μm以下的厚度。如果含树脂层4的厚度小于40μm，就会有含树脂材更容易受到因TCT的温度差而产生的应力影响，对TCT的耐受性降低的疑虑。另外，如果含树脂层4的厚度超过150μm，对封装体尺寸的小型化就会不利。这是因为：在这种情况下，如果为了实现同等的封装体厚度而使密封树脂层8的厚度变薄，担心封装体的耐冲击性降低。
图1示出了具有配置在含树脂层4与第2半导体芯片6的积层体7之间的间隔芯片5的半导体装置1，但第1实施方式的半导体装置1并不限于此。图8示出第1实施方式的半导体装置1的变化例的剖视图。第1实施方式的变化例的半导体装置1如图8所示，也可不具有间隔芯片5。在图8所示的半导体装置1中，第2半导体芯片6的积层体7中的第1级的第2半导体芯片6固定粘着在含树脂层4上。第1实施方式的半导体装置1也可具有这种构成。
(第2实施方式)
图9是表示第2实施方式的半导体装置的剖视图。图8所示的半导体装置21具备：配线衬底2；第1半导体芯片23，经由第1粘接层22固定粘着在配线衬底2上；多个第2半导体芯片25的积层体26，经由第2粘接层24固定粘着在配线衬底2上；以及密封树脂层8，以密封第1半导体芯片23及第2半导体芯片25的积层体26等的方式设置在配线衬底2上。配线衬底2具有与第1实施方式相同的构成。在第2半导体芯片25的积层体26中，下侧的芯片为第1芯片，上侧的芯片为第2芯片。
作为第1半导体芯片23，与第1实施方式同样地可列举在用作第2半导体芯片25的半导体存储器芯片与外部设备之间收发数字信号的控制器芯片或接口芯片、逻辑芯片、RF芯片等系统LSI芯片，但并不限定于此。第1半导体芯片23例如具有80μm左右的厚度。这种第1半导体芯片23通过第1粘接层22而固定粘着在配线衬底2上。在第2实施方式的半导体装置21中，第1粘接层22使用普通的DAF材。第1半导体芯片23的电极(未图示)经由键合线11与配线衬底2的配线层9电连接。
作为第2半导体芯片25，与第1实施方式同样地可列举如NAND型闪存这类半导体存储器芯片，但并不限于此。在第2实施方式中，在配线衬底2上积层搭载着2个第2半导体芯片25。2个第2半导体芯片25分别具有250μm左右的厚度。在积层这种厚度的第2半导体芯片25并搭载在配线衬底2上时，下侧的第2半导体芯片25通过包含125℃下的破坏强度为15MPa以上的含树脂材的第2粘接层(第1粘接剂层)24粘接在配线衬底2上。第2粘接层(第1粘接剂层)24介置在配线衬底2与下侧的第2半导体芯片25之间。将上侧的第2半导体芯片25粘接在下侧的第2半导体芯片25上的第3粘接层(第2粘接剂层)27也可与第1粘接层22同样地使用普通的DAF材，在这种情况下，第2粘接层24相当于第1实施方式的含树脂层4，第3粘接层27相当于第1实施方式的粘接层13。另外，介置在上侧的第2半导体芯片25与下侧的第2半导体芯片25之间的第3粘接层27也可与第2粘接层24同样地使用125℃下的破坏强度为15MPa以上的含树脂材。
搭载在配线衬底2上的2个第2半导体芯片25以露出下侧的第2半导体芯片25的电极的方式，错开排列着电极的端部而呈阶梯状积层。第2半导体芯片25的电极(未图示)经由键合线12与配线衬底2的配线层9电连接。关于电特性及信号特性相同的电极垫，配线衬底2的配线层9与2个第2半导体芯片25的电极垫经由键合线12依次连接。
在配线衬底2的第2面2b上，以将第1半导体芯片23及第2半导体芯片25的积层体26与键合线11、12一并密封的方式，例如模铸成形着使用环氧树脂等绝缘树脂的密封树脂层8。由这些构成要素构成第2实施方式的半导体装置21。在这种半导体装置21中，第1及第2半导体芯片23、25例如具有3ppm左右的线膨胀系数。配线衬底2例如具有20ppm左右的线膨胀系数。密封树脂层8例如具有10ppm左右的线膨胀系数。构成第2粘接层24的含树脂材例如具有70ppm以下左右的线膨胀系数。另外，半导体装置21例如具有0.8mm左右的厚度。
除如上所述的半导体装置21的构成材料间的线膨胀系数的差异以外，以2个第2半导体芯片25的合计厚度增加，第2半导体芯片25的积层体26的厚度(将半导体芯片25的合计厚度与第3粘接层27的厚度相加所得的值)相对于半导体装置21的厚度为67％以上的方式使积层体26相对于封装体厚度的比率较高时，担心半导体装置21对TCT的耐受性降低。也就是说，担心由于配线衬底2与第2半导体芯片25的积层体26之间的线膨胀系数差等，因TCT的温度差而产生的应力会导致第2粘接层24容易产生裂痕。应力集中在第2粘接层24产生的裂痕的前端，使与裂痕相接的配线层9产生断裂(配线断开)而引起不良。
与所述第1实施方式同样地，为了抑制第2粘接层(第1粘接剂层)24的裂痕及由裂痕引起的配线层9的断裂(配线断开)，在第2实施方式的半导体装置21中，第2粘接层24由125℃下的破坏强度为15MPa以上的含树脂材构成。即便在施加了例如700个循环、进而1000个循环的具有如上所述的条件的热循环的情况下，通过由125℃下的破坏强度为15MPa以上的含树脂材构成第2粘接层24，也能够抑制基于因温度差而产生的应力在第2粘接层24产生裂痕，进而因应力集中在裂痕的前端而引起配线层9产生断裂(配线断开)。也就是说，能够提高半导体装置21的可靠性。
第2粘接层24中应用的含树脂材的具体构成与第1实施方式相同。也就是说，作为第2粘接层24的含树脂材通过如下方式形成：将包含作为热硬化树脂的环氧树脂组合物、作为高分子成分的丙烯酸系橡胶、及作为无机填充材的二氧化硅粒子、氧化铝粒子、氧化锆粒子等的混合组合物用作将下侧的第2半导体芯片25固定粘着在配线衬底2上的粘接剂，并使这种粘接剂硬化。作为含树脂材的混合组合物(树脂组合物)的各成分的构成、各成分的混合比率等也与第1实施方式相同。进而，第2粘接层24与第1实施方式相同，线膨胀系数优选为70ppm以下，与配线衬底2的构成材料即金等金属材料(配线材料)或树脂材料(绝缘材料)等的粘接强度优选为10MPa以上。第2粘接层24的厚度优选为40μm以上150μm以下。
此外，对本发明的若干实施方式进行了说明，但这些实施方式是作为例子提出的，并非意图限定发明的范围。这些实施方式能以其它各种方式实施，且能够在不脱离发明主旨的范围内进行各种省略、替换、变更。这些实施方式及其变化包含在发明的范围或主旨中，同时包含在权利要求书所记载的发明及其均等的范围内。

Claims (8)

1.一种半导体装置，具备：
配线衬底；
第1半导体芯片，搭载在所述配线衬底上；
含树脂层，设置于所述配线衬底以嵌埋第1所述半导体芯片；
多个第2半导体芯片，积层搭载在所述第1半导体芯片上；以及
密封树脂层，以密封所述第1半导体芯片及所述多个第2半导体芯片的方式设置在所述配线衬底上；
所述含树脂层包含125℃下的破坏强度为15MPa以上的含树脂材，且
所述多个第2半导体芯片形成的积层体的厚度是所述密封树脂层的上表面到所述配线衬底的下表面的厚度的67％以上。
2.根据权利要求1所述的半导体装置，其中所述含树脂材的线膨胀系数为70ppm/℃以下。
3.根据权利要求1所述的半导体装置，其中所述含树脂材与所述配线衬底的构成材料的粘接强度为10MPa以上。
4.根据权利要求1所述的半导体装置，其中所述含树脂层的厚度为40μm以上150μm以下。
5.根据权利要求1所述的半导体装置，其中所述含树脂材是含有环氧树脂、酚系树脂、丙烯酸系橡胶及无机填充材的树脂组合物的硬化物。
6.根据权利要求5所述的半导体装置，其中所述环氧树脂的环氧基当量为150g/eq以上2000g/eq以下，所述酚系树脂的羟基当量为90g/eq以上220g/eq以下，
所述环氧树脂的所述环氧基当量相对于所述酚系树脂的所述羟基当量的比率为0.8以上1.2以下。
7.根据权利要求5所述的半导体装置，其中所述丙烯酸系橡胶的重量平均分子量为500000以上1000000以下，所述树脂组合物中的所述丙烯酸系橡胶的调配比率为1质量％以上20质量％以下。
8.根据权利要求1所述的半导体装置，其还具备间隔芯片，所述间隔芯片介置在所述含树脂层与所述多个第2半导体芯片之间，且
所述间隔芯片的厚度加算到所述积层体的厚度上。
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