CN113363360A - LED chip with vertical structure and manufacturing method thereof - Google Patents

LED chip with vertical structure and manufacturing method thereof Download PDF

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Publication number
CN113363360A
CN113363360A CN202110557236.5A CN202110557236A CN113363360A CN 113363360 A CN113363360 A CN 113363360A CN 202110557236 A CN202110557236 A CN 202110557236A CN 113363360 A CN113363360 A CN 113363360A
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layer
concave
convex pattern
epitaxial layer
epitaxial
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CN113363360B (en
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范伟宏
毕京锋
郭茂峰
李士涛
赵进超
石时曼
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Xiamen Silan Advanced Compound Semiconductor Co Ltd
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Xiamen Silan Advanced Compound Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers

Abstract

Disclosed are a vertical structure LED chip and a method of manufacturing the same, the vertical structure LED chip including a bonding substrate; the first electrode layer is attached to the surface of the first side of the bonding substrate; the metal bonding layer is attached to the surface of the second side of the bonding substrate; the reflecting mirror layer is positioned on the surface of one side of the metal bonding layer, which is far away from the bonding substrate; the P-type ohmic contact layer is stacked on the surface of one side of the reflecting mirror layer, which is far away from the bonding substrate; the epitaxial layer comprises a second semiconductor layer, a carrier barrier layer, a multi-quantum well layer and a first semiconductor layer which are sequentially stacked on the surface of the P-type ohmic contact layer, wherein the surface of the P-type ohmic contact layer is away from one side of the reflector layer; the second electrode layer is located one side of the reflector layer, which deviates from the bonding substrate, and is arranged opposite to the first electrode layer, the epitaxial layer deviates from the surface of the reflector layer and is formed with a light extraction structure, the light extraction structure is a concave-convex structure arranged in an array with inclined side walls, and the light extraction structure comprises a second concave-convex graph formed on the basis of the first concave-convex graph.

Description

LED chip with vertical structure and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor chips, in particular to a vertical-structure LED chip and a manufacturing method thereof.
Background
Compared with the LED chip with the upright structure and the inverted structure, the LED chip with the vertical structure has the remarkable advantages that: on one hand, the epitaxial layer is transferred from the sapphire substrate with poor insulation and heat dissipation to the bonding substrate with excellent electric conduction and heat conduction capability, so that the epitaxial layer has good heat dissipation capability and can bear larger working current so as to obtain higher brightness; on the other hand, the LED chip with the vertical structure adopts the thicker n-type semiconductor layer as the light-emitting surface, so that micro-nano processing is easy to carry out, the light-emitting layer below the thicker n-type semiconductor layer is not easy to damage, a roughened surface is formed to reduce total reflection caused by larger difference of refractive indexes of semiconductor materials and air, the light extraction efficiency is increased, the brightness and the light efficiency of the LED chip with the vertical structure are obviously improved, and the LED chip with the vertical structure is widely applied to the field of high-power illumination.
At present, various schemes for micro-nano processing of the light-emitting surface of an LED chip with a vertical structure exist, the common scheme is that wet etching is carried out on an alkaline hot solution to process the n-GaN surface into a pyramid-shaped convex structure, but the chemical etching rates of different epitaxial wafers are obviously different due to the wet etching, and Ga with lower solubility is generated in the wet etching process of the alkaline solution2O3The coating can cover the n-GaN surface, so that the stability and the repeatability of the corrosion process are reduced; or preparing a photonic crystal structure on the surface of the n-GaN layer by adopting a photoetching technology, wherein a pattern obtained by theoretical calculation and a pattern obtained after etching have larger sizesCun difference, it cannot be used in large scale; an initial roughening surface is formed by an ICP (Inductively Coupled Plasma) etching process, and then wet etching is performed to increase the roughening effect, so that a wet etching process is also needed.
The method also comprises other surface roughening schemes, for example, a developing solution is adopted for roughening to reduce the difference of corrosion efficiency so as to relieve uneven roughening of the light emitting surface, but along with the reduction of the concentration of reactants in the corrosion solution, the stability of the roughening process is still difficult to control, and large-scale stable mass production effect cannot be realized. In addition, in the surface roughening process, the epitaxial bottom layer growth mode adopted by the epitaxial wafer, the specific patterning design of the sapphire substrate, and the substrate polishing and stripping processes all have different influences on the process stability and repeatability of the vertical structure LED chip roughening. Therefore, the surface roughening process such as wet etching adopted at present has poor process uniformity, repeatability and stability, the yield of the prepared LED chip is relatively low, and large-scale stable mass production cannot be realized.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a vertical structure LED chip and a manufacturing method thereof, which significantly improve uniformity, repeatability and yield of a micro-nano processing process on the surface of the vertical structure LED chip through a simple and efficient surface micro-nano processing scheme, and simultaneously obtain better light extraction efficiency and light extraction morphology.
According to a first aspect of the present invention, there is provided a vertical structure LED chip comprising:
bonding the substrate;
the first electrode layer is attached to the surface of the first side of the bonding substrate;
the metal bonding layer is attached to the surface of the second side of the bonding substrate;
the reflecting mirror layer is positioned on the surface of one side of the metal bonding layer, which faces away from the bonding substrate;
the P-type ohmic contact layer is stacked on the surface of one side, away from the bonding substrate, of the reflector layer;
the epitaxial layer comprises a second semiconductor layer, a carrier barrier layer, a multi-quantum well layer and a first semiconductor layer which are sequentially stacked on the surface of the P-type ohmic contact layer, wherein the surface of the P-type ohmic contact layer is away from one side of the reflector layer;
a second electrode layer located on a side of the mirror layer facing away from the bonding substrate and disposed opposite to the first electrode layer,
the surface of the epitaxial layer, which deviates from the reflector layer, is provided with a light extraction structure, the light extraction structure is a concave-convex structure with inclined side walls and arranged in an array, and the light extraction structure comprises a second concave-convex pattern formed on the basis of the first concave-convex pattern.
Optionally, the metal bonding layer comprises two groups of bonding structures, each group of bonding structures comprising a plurality of metal layers.
Optionally, the feature size of the unit structure of the second uneven pattern is smaller than the feature size of the unit structure of the first uneven pattern, and the second uneven pattern is distributed between the gaps of the unit structure of the first uneven pattern and on the unit structure of the first uneven pattern.
Optionally, the first concave-convex pattern and the second concave-convex pattern are both regular patterns.
Optionally, the first concave-convex pattern and the second concave-convex pattern are distributed in an array, and the array mode of the first concave-convex pattern is one of linear or curved strip, quadrilateral and triangular arrangement.
Optionally, the array manner of the second concave-convex pattern is one of triangular, square, rhombic, hexagonal or circular array arrangement manners, and the shape of the second concave-convex pattern is one of circular, rectangular, rhombic or other regular polygonal schemes of independent arrangement or combined arrangement.
Optionally, the characteristic dimension of the first concave-convex pattern is in a micrometer scale, and the characteristic dimension of the second concave-convex pattern is in a nanometer scale.
Optionally, the vertical structure LED chip is a reverse polarity vertical structure LED chip, the second electrode layer is located on the surface of the epitaxial layer having the light extraction structure, and the epitaxial layer is located between the second electrode layer and the P-type ohmic contact layer.
Optionally, the vertical structure LED chip is a positive polarity vertical structure LED chip, and the second electrode layer is located on a side of the epitaxial layer and on a surface of the mirror layer not covered by the epitaxial layer and the P-type ohmic contact layer.
Optionally, the vertical structure LED chip further includes:
the step structure is positioned at the periphery of the epitaxial layer, the surface of the epitaxial layer is used as an upper step surface of the step structure, and the P-type ohmic contact layer is used as a lower step surface of the step structure;
and the protective layer is positioned on the surface and the side wall of the epitaxial layer.
Optionally, the vertical structure LED chip further includes:
the contact through hole penetrates through the P-type ohmic contact layer, the reflector layer and part of the epitaxial layer to expose the first semiconductor layer;
the N-type ohmic contact layer is positioned on the first semiconductor layer at the bottom of the contact through hole, and the metal bonding layer is filled in the contact through hole and is connected with the N-type ohmic contact layer;
the dielectric layer is positioned between the reflector layer and the metal bonding layer, positioned on the side wall of the contact through hole and used for separating the metal bonding layer from the epitaxial layer;
and the protective layer is positioned on the surface and the side wall of the epitaxial layer.
According to a second aspect of the present invention, there is provided a method for manufacturing a vertical structure LED chip, comprising:
forming an epitaxial layer on the surface of the patterned growth substrate;
sequentially forming a P-type ohmic contact layer, a reflector layer and a metal bonding layer on the surface of the epitaxial layer to form an epitaxial wafer;
providing a bonding substrate, and forming a metal bonding layer on the surface of the bonding substrate;
bonding the bonding substrate and the epitaxial wafer through the metal bonding layer;
stripping the growth substrate, and forming a light extraction structure on the surface of the epitaxial layer, wherein the light extraction structure is a concave-convex structure with inclined side walls and arranged in an array manner, and the light extraction structure comprises a second concave-convex pattern formed on the basis of the first concave-convex pattern;
a first electrode layer and a second electrode layer are formed.
Optionally, the manufacturing method further includes: and cutting the LED chip with the vertical structure by using a wafer cutting technology.
Optionally, the growth substrate is stripped using a substrate transfer technique.
Optionally, the step of peeling off the growth substrate and forming the light extraction structure on the surface of the epitaxial layer includes:
stripping the growth substrate to expose the epitaxial layer with a first concave-convex pattern, wherein the first concave-convex pattern corresponds to the concave-convex pattern on the growth substrate;
forming a photoresist layer with a second concave-convex pattern on the epitaxial layer, wherein the second concave-convex pattern is provided with an inclined side wall;
and transferring the second concave-convex pattern to the epitaxial layer with the first concave-convex pattern by taking the photoresist layer as a mask.
Optionally, the forming a photoresist layer having a second concave-convex pattern on the epitaxial layer includes:
coating a photoresist layer on the surface of the epitaxial layer with the first concave-convex pattern;
preparing second concave-convex patterns distributed in an array on the photoresist layer by adopting a high-precision photoetching process;
and forming an inclined side wall on the second concave-convex pattern by adopting a photoresist thermal reflow deformation technology.
Optionally, the transferring the second concave-convex pattern onto the epitaxial layer with the first concave-convex pattern by using the photoresist layer as a mask includes:
etching the epitaxial layer by using the photoresist layer with the second concave-convex pattern as a mask and adopting a dry etching process;
and forming a second concave-convex pattern on the epitaxial layer with the first concave-convex pattern so as to form a light extraction structure on the surface of the epitaxial layer.
Optionally, the first concave-convex pattern and the second concave-convex pattern are both regular patterns.
Optionally, the first concave-convex pattern and the second concave-convex pattern are distributed in an array, and the array mode of the first concave-convex pattern is one of linear or curved strip, quadrilateral and triangular arrangement.
Optionally, the array manner of the second concave-convex pattern is one of triangular, square, rhombic, hexagonal or circular array arrangement manners, and the shape of the second concave-convex pattern is one of circular, rectangular, rhombic or other regular polygonal schemes of independent arrangement or combined arrangement.
Optionally, the high-precision lithography process includes a step-and-scan process, a nanosphere self-assembled array lithography process, and a nanoimprint process.
Optionally, the substrate transfer technology is one or more of laser lift-off, chemical wet etching and electrochemical etching.
Optionally, the wafer cutting technology is one of a water-guided laser, a laser surface cutting or a grinding wheel cutter cutting processing mode.
Optionally, forming an epitaxial layer on the patterned growth substrate surface comprises:
providing a patterned growth substrate with a concave-convex pattern;
and growing a buffer layer, an unintended doping layer, a first semiconductor layer, a multi-quantum well layer, a carrier barrier layer and a second semiconductor layer on the surface of the growth substrate in sequence.
Optionally, the surface of the epitaxial layer on which the light extraction structure is formed is the surface of the first semiconductor layer;
stripping the growth substrate comprises:
separating the growth substrate from the epitaxial layer by adopting a substrate transfer technology, and exposing the unintentional doping layer with a first concave-convex pattern, wherein the first concave-convex pattern corresponds to the concave-convex pattern on the growth substrate;
and etching and transferring the first concave-convex pattern on the unintentional doping layer to the surface of the first semiconductor layer by adopting a dry etching process.
Optionally, the surface of the epitaxial layer forming the light extraction structure is the surface of the unintentional doped layer;
stripping the growth substrate comprises:
and separating the growth substrate from the epitaxial layer by adopting a substrate transfer technology, and exposing the unintentional doping layer with a first concave-convex pattern, wherein the first concave-convex pattern corresponds to the concave-convex pattern on the growth substrate.
Optionally, the feature size of the unit structure of the second uneven pattern is smaller than the feature size of the unit structure of the first uneven pattern, and the second uneven pattern is distributed between the gaps of the unit structure of the first uneven pattern and on the unit structure of the first uneven pattern.
Optionally, the characteristic dimension of the first concave-convex pattern is in a micrometer scale, and the characteristic dimension of the second concave-convex pattern is in a nanometer scale.
Optionally, the manufacturing method further includes:
etching the epitaxial layer from the surface of the light extraction structure to form a step on the periphery of the epitaxial layer, wherein the surface of the epitaxial layer is used as the upper step surface of the step structure, and the P-type ohmic contact layer is used as the lower step surface of the step structure;
and forming a protective layer on the surface and the side wall of the epitaxial layer.
Optionally, the manufacturing method further includes:
etching the multi-quantum well layer, the carrier barrier layer and the second semiconductor layer to form a plurality of contact through holes, wherein the bottoms of the contact through holes are exposed out of the surface of the first semiconductor layer;
forming an N-type ohmic contact layer at the bottom of the contact through hole;
depositing a dielectric layer on the bottom and the side wall of the contact through hole and the surface of the reflector layer to separate the N-type ohmic contact layer from the epitaxial layer, and the metal bonding layer from the epitaxial layer;
and forming the metal bonding layer on the surface of the dielectric layer, wherein the metal bonding layer is in contact with the N-type ohmic contact layer and fills the contact through hole.
Optionally, the manufacturing method further includes:
etching the periphery of the epitaxial layer from the surface of one side where the light extraction structure is located until the reflector layer is exposed;
forming a protective layer on the surface and the side wall of the epitaxial layer;
a second electrode layer is formed on a surface of the mirror layer.
The invention provides a vertical structure LED chip and a manufacturing method thereof.A growth substrate with a concave-convex pattern is firstly formed with an epitaxial layer, then an epitaxial wafer and a bonding substrate are bonded together through a metal bonding layer, then the epitaxial layer and the growth substrate are separated by utilizing a substrate transfer technology, the first pattern transfer is completed, so that a first concave-convex pattern is formed on the epitaxial layer, and then a high-precision photoetching process is adopted to form a second concave-convex pattern on the surface of the epitaxial layer, so that light extraction structures arranged in an array mode are formed on the surface of the epitaxial layer, and the light extraction efficiency of the vertical structure LED chip is increased. Therefore, according to the vertical structure LED chip and the manufacturing method thereof, the light extraction structure is formed on the surface of the vertical structure LED through a simple and efficient micro-nano processing scheme, the uniformity, the repeatability and the yield of the micro-nano processing technology are remarkably improved, meanwhile, better light extraction efficiency and light-emitting appearance can be obtained, higher technology yield is finally obtained, and low-cost large-scale mass production can be realized.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1a and 1b show schematic structural views of vertical-structured LED chips according to first and second embodiments of the present invention, respectively;
FIG. 2 shows a flow chart of a method of manufacturing a vertical structure LED chip according to an embodiment of the invention;
FIGS. 3a to 3j respectively show schematic cross-sectional views of a vertical structure LED chip according to a first embodiment of the present invention at various stages in the manufacturing process;
FIGS. 4a to 4j are schematic cross-sectional views of a vertical structure LED chip according to a second embodiment of the present invention at various stages in the manufacturing process;
fig. 5a to 5c respectively show simplified plan views of several implementations of a light extraction structure of a vertical structure LED chip according to an embodiment of the present invention;
fig. 6a and 6b show simplified schematic plan views of several implementations of light extraction structures of vertical structure LED chips, respectively, according to another embodiment of the present invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
When a layer, a region, or a region is referred to as being "on" or "over" another layer, another region, or a region may be directly on or over the other layer, the other region, or another layer or a region may be included between the layer and the other layer or the other region. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.
Fig. 1a and 1b show schematic structural views of vertical-structured LED chips according to first and second embodiments of the present invention, respectively.
The vertical structure LED chip of the present embodiment includes a positive polarity structure and a negative polarity structure, and fig. 1a and 1b illustrate the structures of the vertical structure LED chips of the negative polarity and the positive polarity, respectively, and are described below with reference to the accompanying drawings.
As shown in fig. 1a, the reverse-polarity vertical-structure LED chip includes: the semiconductor device comprises a bonding substrate 200, a first electrode layer 108, a metal bonding layer 106, a reflector layer 104, a P-type ohmic contact layer 103, an epitaxial layer 101 and a second electrode layer 109.
The first electrode layer 108 is attached to the surface of the first side of the bonding substrate 200; the metal bonding layer 106 is attached to the surface of the second side of the bonding substrate 200, and the mirror layer 104 is located on the metal bonding layer 106; the metal bonding layer 106 includes two groups of bonding structures, i.e., a first metal bonding layer 1061 and a second metal bonding layer 1062 in fig. 1a, each group of bonding structures includes multiple metal layers, and the first metal bonding layer 1061 and the second metal bonding layer 1062 are sequentially distributed between the mirror layer 104 and the bonding substrate 200. The P-type ohmic contact layer 103 is positioned on the mirror layer 104; the epitaxial layer 101 is stacked on the P-type ohmic contact layer 103; the second electrode layer 109 is located on the epitaxial layer 101, in particular on the surface of the epitaxial layer 101 having the light extraction structures.
Wherein the epitaxial layer 101 includes a second semiconductor layer 16, a carrier blocking layer 15, a multiple quantum well layer 14, and a first semiconductor layer 13, which are sequentially stacked on the surface of the P-type ohmic contact layer 103. The epitaxial layer 101 deviates from being formed with light extraction structure on the surface of reflector layer 104, and this light extraction structure is formed at first semiconductor layer 13 surface, is the concave-convex structure that the array that has the slope lateral wall was arranged, and light extraction structure includes the second concave-convex figure that forms on the basis of first concave-convex figure, makes the surface of this vertical structure LED chip process and receives a little processing, and light extraction efficiency obtains promoting.
Further, the vertical structure LED chip further includes a step structure and a protection layer 105, the epitaxial layer 101 may be divided into a plurality of units by disposing a plurality of via layers inside the epitaxial layer 101, the via layers are etched and removed to form the step structure, only one unit structure is shown in the figure, the periphery of the epitaxial layer 101 of the unit structure is the step structure, the surface of the epitaxial layer 101 (the surface of the first semiconductor layer 13) serves as an upper step surface of the step structure, and the P-type ohmic contact layer 103 serves as a lower step surface of the step structure; the protective layer 105 is located on the surface and the side wall of the epitaxial layer 101, and protects the epitaxial layer 101 of the vertical LED chip.
As shown in fig. 1b, the positive polarity vertical structure LED chip includes a bonding substrate 400, a first electrode layer 309, a metal bonding layer 306, a mirror layer 304, a P-type ohmic contact layer 303, an epitaxial layer 301, and a second electrode layer 308, and further includes: a contact via, an N-type ohmic contact layer 302, a dielectric layer 305 and a protective layer 307.
A first electrode layer 309 is attached to a surface of the first side of the bond substrate 400; the metal bonding layer 306 is attached to the surface of the second side of the bonding substrate 400, and the reflector layer 304 is located on the side, away from the bonding substrate 400, of the metal bonding layer 306; the P-type ohmic contact layer 303 is positioned on the mirror layer 304; the epitaxial layer 301 is stacked on the P-type ohmic contact layer 303; the second electrode layer 308 is located on a surface of the mirror layer 304. Metal bonding layer 306 still includes two sets of bonding structures, first metal bonding layer 3061 and second metal bonding layer 3062, both sets of bonding structures including multiple metal layers (the multiple layers are not shown).
The epitaxial layer 301 includes a second semiconductor layer 36, a carrier blocking layer 35, a multi-quantum well layer 34, a first semiconductor layer 33, and an unintentional doping layer 32, which are sequentially stacked on the surface of the P-type ohmic contact layer 303, where the unintentional doping layer 32 may be regarded as a part of the first semiconductor layer 33. The epitaxial layer 301 deviates from being formed with light extraction structure on the surface of reflector layer 304, and this light extraction structure is formed at unintentional doping layer 32 surface, is the concave-convex structure that the array that has the slope lateral wall was arranged, and light extraction structure includes the second concave-convex figure that forms on the basis of first concave-convex figure, makes the surface of this vertical structure LED chip process a little and has received processing, and light extraction efficiency obtains promoting.
The contact through holes are uniformly distributed in an array, penetrate through the P-type ohmic contact layer 303, the reflector layer 304 and part of the epitaxial layer 301 (the second semiconductor layer 36, the carrier barrier layer 35 and the multiple quantum well layer 34) and expose the surface of the first semiconductor layer 33; the N-type ohmic contact layer 302 is positioned at the bottom of the contact through hole and is connected with the first semiconductor layer 33; the first metal bonding layer 3061 fills the contact via hole and is connected with the N-type ohmic contact layer 302. A dielectric layer 305 is positioned between the mirror layer 304 and the first metal bonding layer 3061 and on the sidewall of the contact via hole to separate the first metal bonding layer 3061 from the epitaxial layer 301; a protective layer 307 is located on the surface and sidewalls of epitaxial layer 301. The second electrode layer 308 is located on the mirror layer 304 and surrounds the epitaxial layer 301.
The light extraction structures of the above two embodiments each include a first concave-convex pattern having a characteristic dimension of between several micrometers and several tens of micrometers, and a second concave-convex pattern having a characteristic dimension of between several tens of nanometers and several hundreds of nanometers. The feature size of the unit structure of the second concave-convex pattern is smaller than the feature size of the unit structure of the first concave-convex pattern, and the second concave-convex pattern is distributed between the unit structures of the first concave-convex pattern and on the unit structures of the first concave-convex pattern. The first concave-convex pattern and the second concave-convex pattern are uniformly distributed in an array mode, the array mode of the first concave-convex pattern is one of linear or curved strip, quadrangle and triangle arrangement, the shape of the second concave-convex pattern is one of circular, rectangular, rhombic or other regular polygon arrangement schemes in a single or combined arrangement mode, the array mode is one of triangular, tetragonal, rhombic, hexagonal or circular array arrangement modes, and the specific shape and arrangement of the light extraction structure can refer to the attached figures 5 a-6 b, but not limited to the above.
According to the LED chip with the vertical structure, the surface layer of the epitaxial layer is subjected to micro-nano processing, so that the surface of the epitaxial layer is subjected to micro-nano structuring, a light extraction structure is formed, the light extraction efficiency is remarkably improved, the LED chip is suitable for large-scale mass production, and the yield is improved.
FIG. 2 shows a flow chart of a method of manufacturing a vertical structure LED chip according to an embodiment of the invention; fig. 3a to 3j respectively show schematic cross-sectional views of a vertical structure LED chip according to a first embodiment of the present invention at various stages in the manufacturing process. A method for manufacturing a vertical LED chip according to a first embodiment of the present application is described below with reference to fig. 2 to 3 j.
As shown in fig. 2, in step S101, an epitaxial layer is formed on the patterned growth substrate surface.
The vertical structure LED chip is a reversed polarity vertical structure LED chip. In this step, the growth of the epitaxial layer is first completed on a patterned foreign substrate, which is a growth substrate as a substrate for epitaxial layer growth. The method specifically comprises the following steps: providing a patterned growth substrate, namely, the surface of the substrate is provided with a concave-convex pattern; and growing a buffer layer, an unintended doping layer, a first semiconductor layer, a multi-quantum well layer, a carrier barrier layer and a second semiconductor layer on the surface of the growth substrate with the concave-convex pattern in sequence.
As shown in fig. 3a, firstly providing a micron-sized patterned sapphire substrate with a characteristic dimension of 3um, namely a growth substrate 100, and then preparing an epitaxial layer 101 thereon by using an epitaxial growth method, wherein the total thickness of the epitaxial layer 101 is controlled to be 5-10 microns; the epitaxial layer 101 includes a buffer layer 11, an unintentional doping layer 12, a first semiconductor layer 13 (heavily doped n-GaN), a multiple quantum well layer 14, a carrier blocking layer 15(p-AlGaN), and a second semiconductor layer 16(p-GaN) formed in this order on the surface of a growth substrate 100. Further, the MQW layer 14 is a GaN/InGaN/AlGaN material, and has a wavelength range from 200nm to 600 nm.
The method of epitaxial growth may be metal chemical vapor deposition, laser assisted molecular beam epitaxy, laser sputtering, or hydride vapor phase epitaxy. The epitaxial layer 101 comprises one of reciprocating continuous progressive epitaxial structures composed of GaN/InGaN material systems, which is preferably an InGaN structure with different In compositions.
The patterned growth substrate 100 has a concave-convex pattern, the concave-convex pattern on the growth substrate 100 can be prepared by photolithography of a bulk material and one or more dielectric materials, the characteristic dimension range is several micrometers to tens of micrometers, and the pattern array mode is one of linear or curved strip, quadrilateral and triangular arrangement. The material of the growth substrate 100 includes Ga2O3SiC, Si, sapphire, ZnO, LiGaO2A single crystal substrate or a high temperature resistant metal substrate, etc. Further, growThe surface of the substrate 100 may also be formed with a pre-deposited AlN film. The thickness of the growth substrate 100 is 300um to 2 mm.
Since the growth substrate 100 has the concave-convex pattern thereon, the epitaxial layer 101 grown thereon may conform to the growth substrate 100, for example, a first concave-convex pattern corresponding to the concave-convex pattern on the growth substrate 100 may be formed on the surface of the buffer layer 11 facing the growth substrate 100.
Further, a runner layer 17 is formed. With continued reference to fig. 3a, a plurality of via layers 17 are formed through the epitaxial layer 101, for example, the via layers 17 are formed in the epitaxial layer 101 by using a photolithography technique and a chemical vapor deposition technique, a MESA unit region is formed in a region surrounded by the via layers 17, the epitaxial layer 101 is divided into a plurality of units, and each unit subsequently forms a single vertical LED chip.
Next, in step S102, a P-type ohmic contact layer, a mirror layer, and a metal bonding layer are sequentially formed on a surface of the epitaxial layer to form an epitaxial wafer.
As shown in fig. 3b, a P-type ohmic contact layer 103 and a mirror layer 104 are formed on the second semiconductor layer 16 and the via layer 17 by photolithography and physical vapor deposition, the P-type ohmic contact layer 103 is made of, for example, NiAg and has a thickness of, for example, 10nm, and the mirror layer 104 is made of, for example, AgTiWTi and has a thickness of, for example, 200 nm. Then, a first metal bonding layer 1061 is formed on the surface of the mirror layer 104 by PVD (physical vapor deposition), and the first metal bonding layer 1061 is, for example, tiptaussn (multilayer metal layer). The resulting semiconductor structure is an epitaxial wafer 10 for subsequent bonding to a bonding substrate.
In step S103, a bonding substrate is provided, and a metal bonding layer is formed on a surface of the bonding substrate.
As shown in fig. 3c, a bonded substrate 200 is provided and a second metal bonding layer 1062 is formed thereon by PVD. The bonded substrate 200 is, for example, a silicon substrate having a thickness of 600 um.
In step S104, the bonding substrate is bonded to the epitaxial wafer through the metal bonding layer.
Next, as shown in fig. 3d, the epitaxial wafer 10 and the bonding substrate 200 are bonded together using a wafer bonding process under conditions of 300 ℃ and 1500kgf pressure. Specifically, the first metal bonding layer 1061 and the second metal bonding layer 1062 are bonded to each other, thereby bonding the bonded substrate 200 to the epitaxial wafer 10.
In this embodiment, the bonding substrate 200 is one of Si, Cu, Mo, W, CuW, CuMo, and AlSi substrates, and the thickness of the bonding substrate 200 is 100um to 1 um. The metal bonding layer 106 is one of a structure formed by directly bonding a binary eutectic bonding metal composed of Au, Ni, Cu, Ag high melting point metal and Sn, In low melting point metal, or Au — Au metal, and the first metal bonding layer 1061 and the second bonding layer 1062 may further include a titanium adhesion layer (not shown In the figure).
In step S105, the growth substrate is peeled to expose the epitaxial layer having the first concave-convex pattern.
In this step, the growth substrate 100 is removed mainly by using a substrate transfer technique, and the surface of the epitaxial layer 101 with the first concave-convex pattern is exposed. In this embodiment, after the growth substrate 100 is removed, the buffer layer 11 is also removed simultaneously, the surface of the unintentional doping layer 12 of the epitaxial layer 101 is exposed, and the surface of the unintentional doping layer 12 has the first concave-convex pattern.
The substrate transfer technology is one or more process combination of laser lift-off, chemical wet etching and electrochemical etching.
Specifically, as shown in fig. 3e, a DPSS laser is used to provide a small circular spot (spot size about 20um) with gaussian distribution of energy, and a spiral or linear scanning lift-off method is used to separate the patterned sapphire substrate (growth substrate 100) from the epitaxial layer 101, so as to obtain the unintentional doping layer 12 with the first concave-convex pattern. The shape of the unintentional doping layer 12 is conformal to the buffer layer 11 because the buffer layer 11 is thin, and a first concave-convex pattern is formed on the unintentional doping layer 12 after the buffer layer 11 is stripped; or may be understood as transferring a first relief pattern on the buffer layer 11 onto the unintentionally doped layer 12, the first relief pattern corresponding to the relief pattern on the patterned growth substrate 100.
Thereafter, as shown in fig. 3f, the unintentional doping layer 12 is etched to the first semiconductor layer 13 by using the dry etching process parameters with the physical etching characteristic, and the first concave-convex pattern is transferred to the surface of the first semiconductor layer 13 due to the physical etching characteristic. That is, the exposed surface of the epitaxial layer 101 is now the surface of the first semiconductor layer 13, and the first concave-convex pattern is transferred onto the first semiconductor layer 13, thereby completing the first patterning.
In this embodiment, the surface of the first semiconductor layer 13 of the epitaxial layer 101 has a first concave-convex pattern, and the surface of the epitaxial layer 101 on which the light extraction structure is formed subsequently is also the surface of the first semiconductor layer 13.
In step S106, a photoresist layer having a second concave-convex pattern having inclined sidewalls is formed on the epitaxial layer.
In this step, preparation is made for the second patterning of the epitaxial layer, which mainly includes: coating a photoresist layer 18 on the surface of the epitaxial layer 101 (first semiconductor layer 103) having the first concavo-convex pattern; preparing an array distribution concave-convex pattern on the photoresist layer 18 by adopting a high-precision photoetching process; and forming the inclined side wall of the concave-convex pattern by adopting a photoresist thermal reflow deformation technology.
As shown in fig. 3g, a layer of photoresist is first formed on the surface of the epitaxial layer 101 that has undergone the first patterning, actually, a layer of photoresist 18 is coated on the surface of the first semiconductor layer 13, and then a high-precision photolithography process is used to prepare a concave-convex pattern with a high-density uniform array distribution on the photoresist layer 18, wherein the shape of the concave-convex pattern is one of a circular, rectangular, diamond or other regular polygon, alone or in combination. And then, forming an inclined side wall on the concave-convex pattern by adopting a photoresist thermal reflux deformation technology, wherein the pattern is a second concave-convex pattern. For example, a nanoimprint lithography technique is used to produce circular and regular hexagons with a diameter of about 150nm on the photoresist layer 18 as a 1: 1 concave-convex patterns which are arranged at intervals in a combined mode, wherein the concave-convex patterns are arranged in a triangular array mode; and thermally refluxing for 30min at 150 ℃ by using an oven to form an inclined side wall on the concave-convex pattern structure.
The high-precision photoetching technology is one of stepping scanning type photoetching, nanosphere self-assembly photoetching and nanoimprint photoetching; the size range of the second concave-convex pattern is dozens of nanometers to hundreds of nanometers, and a triangular, square, rhombic, hexagonal or circular array arrangement mode is adopted; the thermal reflux temperature of the photoresist is 100-200 ℃, and the time range is 10-90 min.
In step S107, the second concave-convex pattern is transferred onto the epitaxial layer having the first concave-convex pattern using the photoresist layer as a mask.
The method specifically comprises the following steps: etching the epitaxial layer 101 by using the photoresist layer 18 with the second concave-convex pattern as a mask and adopting a dry etching process; a second concave-convex pattern is formed on the epitaxial layer 101 (first semiconductor layer 13) patterned by the first concave-convex pattern so that a light extraction structure is formed on the surface of the epitaxial layer 101.
Referring to fig. 3h, the photoresist layer 18 having the second concave-convex pattern is used as a mask, and the concave-convex pattern with a size of about 150nm is transferred onto the surface of the first semiconductor layer 13 of the epitaxial layer 101 having the first concave-convex pattern by using a dry etching process, so as to form a light extraction structure having a special array mode, thereby increasing the light extraction efficiency of the vertical LED chip.
With reference to fig. 3g and 3h, after the first pattern transfer, a first concave-convex pattern, such as a plurality of continuous pits, is formed on the surface of the first semiconductor layer 13, and then, after the second pattern transfer, etching is performed on the basis of the first concave-convex pattern to form a second concave-convex pattern, which is distributed on the entire surface of the first semiconductor layer 13, so that the second concave-convex pattern is formed not only on the bottoms of the pits, but also between the pits, and even on the sidewalls of the pits. The feature size of the second concave-convex pattern is smaller than that of the first concave-convex pattern, so that after the pattern transfer is performed twice, a light extraction structure is formed on the surface of the first semiconductor layer 13, and the light extraction efficiency is improved.
In step S108, a first electrode layer and a second electrode layer are formed.
As shown in fig. 3i, the via layer 17 is etched away using a thick photoresist as a protective mask to expose the underlying P-type ohmic contact layer 103. Thus, adjacent vertical structure LED units are separated, and subsequently a single vertical structure LED chip is formed.
Next, a second electrode layer 109 with a total thickness of 800nm was prepared on the first semiconductor layer 13 by photolithography and physical vapor deposition techniques, and the second electrode layer 109 was an N electrode.
Next, as shown in FIG. 3j, a layer of SiO with a thickness of 200nm is formed on the surface and sidewall of the epitaxial layer 101 by CVD process2A dielectric film serves as the protective layer 105. The bonded substrate 200 is then thinned by using a thinning apparatus, and a first electrode layer 108 is prepared on the back surface thereof, the first electrode layer 108 being, for example, a P electrode of a TiPtAu material.
In step S109, the vertical structure LED chip is diced by using a wafer dicing technique.
As shown in fig. 3j, the first electrode layer 108 and the bonding substrate 200 are respectively diced by a wafer dicing technique to complete the dicing of the chip, and finally the LED chip with the reverse-polarity vertical structure is obtained. The wafer cutting technology is one of water-guided laser, laser surface cutting or grinding wheel cutter processing modes, and the cutting scheme is one of single-sided cutting or double-sided cutting.
Compared with the prior wet etching coarsening process, the invention adopts high-precision photoetching to solve the problem of pattern consistency, uses the photoresist layer as a mask to realize quantitative production and solves the problems of process uniformity and repeatability; on the other hand, a nano-scale concave-convex pattern (a second concave-convex pattern) is formed by adopting photoresist backflow and transferred to the epitaxial layer with the first concave-convex pattern to form a light extraction structure, so that the problems of poor uniformity and repeatability of patterning of a light-emitting surface are remarkably improved, and the light extraction efficiency of the LED chip with the vertical structure is improved; the technical scheme can realize low-cost large-scale mass production under the condition of the existing equipment, and has great significance for industrial implementation.
Fig. 4a to 4j respectively show schematic cross-sectional views of a vertical structure LED chip according to a second embodiment of the present invention at various stages in the manufacturing process.
The vertical structure LED chip of the present embodiment is a positive polarity vertical structure LED chip, and the manufacturing method thereof is also applicable to the flowchart given in fig. 2. Specifically, the method comprises the following steps:
in step S101, an epitaxial layer is formed on the patterned growth substrate surface.
As shown in FIG. 4a, a sapphire substrate is provided, and a patterned SiO is formed on the sapphire substrate2(feature size is 6um) to form a growth substrate 300 having a concave-convex pattern, and an epitaxial layer 301 is prepared using an epitaxial growth method.
The total thickness of the epitaxial layer 301 is controlled to be 5-10 microns; the epitaxial layer 301 includes a buffer layer 31, an unintentional doping layer 32, a first semiconductor layer 33 (heavily doped n-GaN), a multiple quantum well layer 34, a carrier blocking layer 35(p-AlGaN), and a second semiconductor layer 36(p-GaN) formed in this order on the surface of a growth substrate 300. The epitaxial growth method may be metal chemical vapor deposition, laser assisted molecular beam epitaxy, laser sputtering, or hydride vapor phase epitaxy. The epitaxial layer 101 comprises one of reciprocating continuous progressive epitaxial structures composed of GaN/InGaN material systems, which is preferably an InGaN structure with different In compositions.
Further, contact through holes 37 distributed in an array are defined on the epitaxial layer 301 by using photolithography and dry etching techniques, and the contact through holes 37 penetrate through the second semiconductor layer 36, the carrier barrier layer 35 and the multiple quantum well layer 34 to expose the surface of the first semiconductor layer 33; and preparing an N-type ohmic contact layer 302 on the surface of the first semiconductor layer 33 at the bottom of the contact through hole 37 area by using photoetching and physical vapor deposition technologies, wherein the material of the N-type ohmic contact layer 302 is Al/Ti/Pt/Au, for example, and the thickness is 800nm, for example. And then irradiating the interface of the N-type ohmic contact layer 302 and the first semiconductor layer 33 by using laser with the wavelength of 532nm, so that the laser energy is absorbed to realize the annealing effect, and simultaneously, the flatness of the N-type ohmic contact layer 302 is kept high.
In step S102, a P-type ohmic contact layer, a mirror layer, and a metal bonding layer are sequentially formed on a surface of the epitaxial layer to form an epitaxial wafer.
As shown in fig. 4b, a P-type ohmic contact layer 303 and a mirror layer 304 are formed in the region outside the contact via 37 by using photolithography, wet etching and sputtering processes, wherein the material of the P-type ohmic contact layer 303 is, for example, ITO, and the material of the mirror layer 304 is, for example, AgTiWTi, and the thickness is, for example, 200 nm. Subsequently, a dielectric layer 305 is formed on the surface of the reflector layer 304 by using a CVD process, and the dielectric layer 305 also covers the side of the contact via 37The walls expose the surface of the epitaxial layer 301 and the surface of the N-type ohmic contact layer 302. The material of the dielectric layer 305 is, for example, SiNxEtc., with a thickness of, for example, 1 um. An opening 38 is formed in the dielectric layer 305 by photolithography and dry etching, and the N-type ohmic contact layer 302 is exposed through the opening 38.
Referring to fig. 4c, a first metal bonding layer 3061 is formed on the surface of the dielectric layer 305 by PVD method, the first metal bonding layer 3061 is made of, for example, AuSn binary metal (i.e., two metal layers), and a Ti adhesion layer (not shown) may be formed before the first metal bonding layer 3061 is formed. The first metal bonding layer 3061 fills the opening 38 and contacts the N-type ohmic contact layer 302. The resulting semiconductor structure is an epitaxial wafer 20.
In step S103, a bonding substrate is provided, and a metal bonding layer is formed on a surface of the bonding substrate.
Referring to fig. 4d, a bonded substrate 400 is provided, and a second metal bonding layer 3062 is formed thereon by PVD, and an adhesion layer (not shown) may be formed before forming the second metal bonding layer 3062. The bonded substrate 300 is, for example, a silicon substrate having a thickness of 400 um.
In step S104, the bonding substrate is bonded to the epitaxial wafer through the metal bonding layer.
As shown in fig. 4e, the epitaxial wafer 20 and the bonding substrate 400 are then bonded together at 300 ℃ by using a eutectic bonding process, and the first metal bonding layer 3061 and the second metal bonding layer 3062 jointly constitute the metal bonding layer 306.
In step S105, the growth substrate is peeled to expose the epitaxial layer having the first concave-convex pattern.
In this embodiment, after the growth substrate 300 is stripped and removed, the surface of the unintentional doping layer 32 having the first concave-convex pattern is exposed, and the surface of the epitaxial layer 301 where the light extraction structure is subsequently formed is also the surface of the unintentional doping layer 32.
The method specifically comprises the following steps: separating the growth substrate 300 from the epitaxial layer 301 by using a substrate transfer technique; the unintentionally doped layer 32 having the first concave-convex pattern is exposed.
As shown in fig. 4f, a KrF excimer laser with 240nm provides a small circular spot (spot size about 20um) with energy distributed in a flat-top manner, and the patterned sapphire substrate (growth substrate 300) and the epitaxial layer 301 are separated by spiral or linear scanning lift-off to obtain the unintentional doping layer 12 with the first rugged pattern. Since the buffer layer 31 is thin, the shape of the unintentional doping layer 32 conforms to the buffer layer 31, and when the substrate is transferred, the buffer layer 31 is simultaneously removed, leaving the unintentional doping layer 32 with a first concave-convex pattern corresponding to the concave-convex pattern on the patterned growth substrate 300.
In step S106, a photoresist layer having a second concave-convex pattern having inclined sidewalls is formed on the epitaxial layer.
Referring to fig. 4g, a photoresist layer 39 is coated on the unintentionally doped layer 32 having the first concave-convex pattern, and the photoresist layer 39 is uniformly coated with self-assembled nanospheres, such as 500nm SiO 22Nanospheres, wherein F-based and O-based gases are adopted to process the nanospheres and the photoresist layer 39 at the bottom of the nanospheres, concave-convex patterns in a close-packed array are firstly prepared on the photoresist layer 39, and residual SiO is removed and etched by hydrofluoric acid2And (4) after the nanospheres are arranged, thermally refluxing for 10min at 180 ℃ by using an oven to enable the concave-convex pattern structure to form an inclined side wall, wherein the pattern is the second concave-convex pattern.
In step S107, the second concave-convex pattern is transferred onto the epitaxial layer having the first concave-convex pattern using the photoresist layer as a mask.
As shown in fig. 4h, the second concave-convex pattern with the characteristic dimension smaller than 500nm is transferred onto the unintentional doping layer 32 of the epitaxial layer 301 with the first concave-convex pattern by using a dry etching process and a photoresist mask, so that a light extraction structure is formed, and the light extraction efficiency of the vertical structure LED chip is increased.
In an alternative embodiment, the unintentionally doped layer 32 is removed, such that a light extraction structure is formed on the first semiconductor layer 33. Specifically, after the step of fig. 4f, the unintentional doping layer 32 is etched to the first semiconductor layer 33 by using the dry etching process parameters with the physical etching characteristic, and the first concave-convex pattern is transferred to the surface of the first semiconductor layer 33 due to the physical etching characteristic. Then, steps S106 and S107 are performed, a photoresist layer 39 is coated on the surface of the first semiconductor layer 33, and a concave-convex pattern distributed in an array is prepared on the photoresist layer 39 by adopting a high-precision lithography process; and forming the concave-convex pattern into an inclined side wall by adopting a photoresist thermal reflow deformation technology so as to form a second concave-convex pattern. And etching the first semiconductor layer 33 by using the photoresist layer 39 with the second concave-convex pattern as a mask through a dry etching process to transfer the second concave-convex pattern to the first semiconductor layer 33, so that a light extraction structure is formed, and the light extraction efficiency of the LED chip with the vertical structure is improved.
In step S108, a first electrode layer and a second electrode layer are formed.
As shown in fig. 4i, the epitaxial layer 301 on the via position is etched and removed by using a thick photoresist as a protective mask, and the mirror layer 304 is exposed; a second electrode layer 308 is formed on the exposed area of the mirror layer 304 by photolithography and physical vapor deposition, and the second electrode layer 308 is a P electrode made of CrPtAu, for example.
Referring to FIG. 4j, a layer of SiO with a thickness of 200nm is formed on the surface and sidewall of the epitaxial layer 301 by CVD process2A dielectric film serves as the protective layer 107. The bonded substrate 400 is thinned by using a thinning device, and a first electrode layer 309 is prepared on the back surface of the bonded substrate, wherein the first electrode layer 309 is an N electrode made of, for example, TiPtAu.
In step S109, the vertical structure LED chip is diced by using a wafer dicing technique.
And respectively cutting the first electrode layer 309 and the bonding substrate 400 by adopting a water-guided laser cutting processing method to complete chip cutting, and finally obtaining the LED chip with the positive-polarity vertical structure.
In this embodiment, parts identical to those in the first embodiment are not described again, and the vertical structure LED chip of this embodiment can achieve the same advantageous effects as those in the first embodiment.
Fig. 5a to 5c respectively show simplified schematic plan views of several implementations of a light extraction structure of a vertical structure LED chip according to an embodiment of the present invention.
In this embodiment, the first concave-convex pattern of the light extraction structure has a pattern array manner of a plurality of rows arranged in a straight line, and includes a plurality of structural units, and each structural unit is circular in shape. And the second concave-convex pattern also comprises a plurality of same structural units, and each structural unit is circular.
As shown in fig. 5a, the first concavo-convex pattern includes a plurality of circular unit structures 510, the second concavo-convex pattern includes a plurality of circular unit structures 521, and a characteristic dimension of the unit structures 521 of the second concavo-convex pattern is smaller than a characteristic dimension of the unit structures 510 of the first concavo-convex pattern. The unit structures 510 are arranged in a linear array of multiple rows, and the structure units 510 in each row and the unit structures 510 in the previous row are staggered by a certain distance in the vertical direction; the unit structures 521 are in a regular array structure aligned in each row and each column in the horizontal and vertical directions, that is, the arrangement mode is a square array. The unit structures 521 are distributed between the gaps of the unit structures 510 and on the unit structures 510.
In fig. 5b, the unit structures 510 are arranged in a constant manner, the unit structures 522 are arranged in a plurality of straight lines, and the unit structures 522 in each line are staggered from the unit structures in the previous line, i.e., the unit structures are arranged in a triangular array.
In fig. 5c, the unit structures 510 are arranged in a constant manner, and the unit structures 523 are arranged in groups of every 5 units to form a plurality of groups of structures arranged in a circular array.
These are only a few possible examples and are not intended to limit the invention.
Fig. 6a and 6b show simplified schematic plan views of several implementations of light extraction structures of vertical structure LED chips, respectively, according to another embodiment of the present invention.
In this embodiment, the shape and arrangement of the unit structure 510 of the first uneven pattern are the same as those of fig. 5a to 5 c. And the second concave-convex pattern comprises two unit structures which are mutually combined and arranged.
As shown in fig. 6a, the second concave-convex pattern includes a plurality of circular unit structures 524 and a plurality of hexagonal pattern structures 531, the second concave-convex pattern is arranged in a plurality of rows, the first row is, for example, the unit structures 524, the second row of the pattern structures 524 and the pattern structures 531 are distributed in a staggered manner, the third row is the same as the first row, the fourth row is the same as the second row, and so on. And the structures of each row are mutually aligned in the vertical direction, namely the arrangement mode is a square array.
As shown in fig. 6b, the structure unit is the same as that of fig. 6a, but the arrangement is slightly different. In fig. 6b, the cell structures in each row are vertically offset from the cell structures in the previous row by a certain distance, i.e. the cell structures are arranged in a triangular array.
These are only a few possible examples of light extraction structures and are not intended to limit the invention.
In summary, according to the LED chip with a vertical structure and the method for manufacturing the LED chip with a vertical structure provided by the present invention, an epitaxial layer is formed on a growth substrate having a concave-convex pattern, then an epitaxial wafer and a bonding substrate are bonded together through a metal bonding layer, then the epitaxial layer and the growth substrate are separated by using a substrate transfer technique, a first pattern transfer is completed, so that a first concave-convex pattern is formed on the epitaxial layer, and then a second concave-convex pattern is formed on the surface of the epitaxial layer by using a high-precision photolithography process, so that light extraction structures arranged in an array are formed on the surface of the epitaxial layer, thereby increasing the light extraction efficiency of the LED chip with a vertical structure. Therefore, according to the vertical structure LED chip and the manufacturing method thereof, on one hand, the problem of graph consistency is solved through high-precision photoetching, so that a light extraction structure is formed on the surface of the vertical structure LED, the uniformity, repeatability and yield of a micro-nano processing technology are remarkably improved, on the other hand, a nanoscale concave-convex graph (a second concave-convex graph) is formed through a photoresist backflow technology, better light extraction efficiency and light emitting appearance can be obtained, the problem of poor uniformity and repeatability of light emitting surface patterning is remarkably improved, and finally, higher process yield of the vertical structure LED chip is obtained. The technical scheme can realize low-cost large-scale mass production under the condition of the existing equipment, and has great significance for industrial implementation.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims (31)

1. A vertical structure LED chip, comprising:
bonding the substrate;
the first electrode layer is attached to the surface of the first side of the bonding substrate;
the metal bonding layer is attached to the surface of the second side of the bonding substrate;
the reflecting mirror layer is positioned on the surface of one side of the metal bonding layer, which faces away from the bonding substrate;
the P-type ohmic contact layer is stacked on the surface of one side, away from the bonding substrate, of the reflector layer;
the epitaxial layer comprises a second semiconductor layer, a carrier barrier layer, a multi-quantum well layer and a first semiconductor layer which are sequentially stacked on the surface of the P-type ohmic contact layer, wherein the surface of the P-type ohmic contact layer is away from one side of the reflector layer;
a second electrode layer located on a side of the mirror layer facing away from the bonding substrate and disposed opposite to the first electrode layer,
the surface of the epitaxial layer, which deviates from the reflector layer, is provided with a light extraction structure, the light extraction structure is a concave-convex structure with inclined side walls and arranged in an array, and the light extraction structure comprises a second concave-convex pattern formed on the basis of the first concave-convex pattern.
2. The vertical structure LED chip of claim 1, wherein the metal bonding layers comprise two sets of bonding structures, each set comprising multiple metal layers.
3. The vertical structure LED chip according to claim 1, wherein the feature size of the unit structure of the second concave-convex pattern is smaller than the feature size of the unit structure of the first concave-convex pattern, and the second concave-convex pattern is distributed between the gaps of the unit structure of the first concave-convex pattern and on the unit structure of the first concave-convex pattern.
4. The vertical geometry LED chip of claim 1 wherein the first relief pattern and the second relief pattern are both regular patterns.
5. The vertical structure LED chip of claim 1, wherein the first concave-convex pattern and the second concave-convex pattern are distributed in an array, and the array of the first concave-convex pattern is one of linear or curved strip, quadrilateral and triangular arrangement.
6. The vertical structure LED chip of claim 5, wherein the second concave-convex pattern is arranged in one of a triangular, square, rhombic, hexagonal or circular array, and the second concave-convex pattern is arranged in one of a circular, rectangular, rhombic or other regular polygonal arrangement scheme alone or in combination.
7. The vertical geometry LED chip of claim 1 wherein the first relief pattern has a characteristic dimension on the order of micrometers and the second relief pattern has a characteristic dimension on the order of nanometers.
8. The vertical structure LED chip of claim 1, wherein the vertical structure LED chip is a reverse polarity vertical structure LED chip, the second electrode layer is on the surface of the epitaxial layer having the light extraction structure, and the epitaxial layer is between the second electrode layer and the P-type ohmic contact layer.
9. The vertical structure LED chip of claim 1, wherein the vertical structure LED chip is a positive polarity vertical structure LED chip, and the second electrode layer is located at the periphery of the epitaxial layer and on the surface of the mirror layer not covered by the epitaxial layer and the P-type ohmic contact layer.
10. The vertical geometry LED chip of claim 8 further comprising:
the step structure is positioned at the periphery of the epitaxial layer, the surface of the epitaxial layer is used as an upper step surface of the step structure, and the P-type ohmic contact layer is used as a lower step surface of the step structure;
and the protective layer is positioned on the surface and the side wall of the epitaxial layer.
11. The vertical geometry LED chip of claim 9 further comprising:
the contact through hole penetrates through the P-type ohmic contact layer, the reflector layer and part of the epitaxial layer to expose the first semiconductor layer;
the N-type ohmic contact layer is positioned on the first semiconductor layer at the bottom of the contact through hole, and the metal bonding layer is filled in the contact through hole and is connected with the N-type ohmic contact layer;
the dielectric layer is positioned between the reflector layer and the metal bonding layer, positioned on the side wall of the contact through hole and used for separating the metal bonding layer from the epitaxial layer;
and the protective layer is positioned on the surface and the side wall of the epitaxial layer.
12. A method for manufacturing a vertical structure LED chip is characterized by comprising the following steps:
forming an epitaxial layer on the surface of the patterned growth substrate;
sequentially forming a P-type ohmic contact layer, a reflector layer and a metal bonding layer on the surface of the epitaxial layer to form an epitaxial wafer;
providing a bonding substrate, and forming a metal bonding layer on the surface of the bonding substrate;
bonding the bonding substrate and the epitaxial wafer through the metal bonding layer;
stripping the growth substrate, and forming a light extraction structure on the surface of the epitaxial layer, wherein the light extraction structure is a concave-convex structure with inclined side walls and arranged in an array manner, and the light extraction structure comprises a second concave-convex pattern formed on the basis of the first concave-convex pattern;
a first electrode layer and a second electrode layer are formed.
13. The manufacturing method according to claim 12, further comprising: and cutting the LED chip with the vertical structure by using a wafer cutting technology.
14. The method of manufacturing of claim 12, wherein the growth substrate is stripped using a substrate transfer technique.
15. The method of manufacturing of claim 12, wherein the lifting off the growth substrate and the forming of the light extraction structure on the surface of the epitaxial layer comprises:
stripping the growth substrate to expose the epitaxial layer with a first concave-convex pattern, wherein the first concave-convex pattern corresponds to the concave-convex pattern on the growth substrate;
forming a photoresist layer with a second concave-convex pattern on the epitaxial layer, wherein the second concave-convex pattern is provided with an inclined side wall;
and transferring the second concave-convex pattern to the epitaxial layer with the first concave-convex pattern by taking the photoresist layer as a mask.
16. The manufacturing method according to claim 15, wherein forming a photoresist layer having a second concave-convex pattern on the epitaxial layer comprises:
coating a photoresist layer on the surface of the epitaxial layer with the first concave-convex pattern;
preparing second concave-convex patterns distributed in an array on the photoresist layer by adopting a high-precision photoetching process;
and forming an inclined side wall on the second concave-convex pattern by adopting a photoresist thermal reflow deformation technology.
17. The method of claim 15, wherein transferring the second relief pattern onto the epitaxial layer having the first relief pattern using the photoresist layer as a mask comprises:
etching the epitaxial layer by using the photoresist layer with the second concave-convex pattern as a mask and adopting a dry etching process;
and forming a second concave-convex pattern on the epitaxial layer with the first concave-convex pattern so as to form a light extraction structure on the surface of the epitaxial layer.
18. The manufacturing method according to claim 12, wherein the first concave-convex pattern and the second concave-convex pattern are both regular patterns.
19. The manufacturing method according to claim 12, wherein the first concave-convex pattern and the second concave-convex pattern are distributed in an array, and the array of the first concave-convex pattern is one of linear or curved stripe, quadrilateral and triangular arrangement.
20. The manufacturing method according to claim 12, wherein the second uneven pattern is arranged in one of a triangular, square, diamond, hexagonal or circular array, and the second uneven pattern is arranged in one of a circular, rectangular, diamond or other regular polygon in shape, alone or in combination.
21. The method of manufacturing of claim 16, wherein the high precision lithography process comprises a step-and-scan process, a nanosphere self-assembled array lithography process, and a nanoimprint process.
22. The manufacturing method according to claim 14, wherein the substrate transfer technique is one or more of laser lift-off, chemical wet etching and electrochemical etching.
23. The method of claim 13, wherein the wafer dicing technique is one of water-guided laser, laser surface cutting, or abrasive-wheel cutting.
24. The method of manufacturing of claim 12, wherein forming an epitaxial layer on the patterned growth substrate surface comprises:
providing a patterned growth substrate with a concave-convex pattern;
and growing a buffer layer, an unintended doping layer, a first semiconductor layer, a multi-quantum well layer, a carrier barrier layer and a second semiconductor layer on the surface of the growth substrate in sequence.
25. The manufacturing method according to claim 24, wherein the surface of the epitaxial layer on which the light extraction structure is formed is the surface of the first semiconductor layer;
stripping the growth substrate comprises:
separating the growth substrate from the epitaxial layer by adopting a substrate transfer technology, and exposing the unintentional doping layer with a first concave-convex pattern, wherein the first concave-convex pattern corresponds to the concave-convex pattern on the growth substrate;
and etching and transferring the first concave-convex pattern on the unintentional doping layer to the surface of the first semiconductor layer by adopting a dry etching process.
26. The manufacturing method according to claim 24, wherein the surface of the epitaxial layer on which the light extraction structure is formed is the surface of the unintentionally doped layer;
stripping the growth substrate comprises:
and separating the growth substrate from the epitaxial layer by adopting a substrate transfer technology, and exposing the unintentional doping layer with a first concave-convex pattern, wherein the first concave-convex pattern corresponds to the concave-convex pattern on the growth substrate.
27. The manufacturing method according to claim 12, wherein a characteristic dimension of the cell structure of the second uneven pattern is smaller than a characteristic dimension of the cell structure of the first uneven pattern, and the second uneven pattern is distributed between the gaps of the cell structure of the first uneven pattern and on the cell structure of the first uneven pattern.
28. The manufacturing method according to claim 12, wherein a characteristic dimension of the first concave-convex pattern is on a micrometer scale, and a characteristic dimension of the second concave-convex pattern is on a nanometer scale.
29. The method of manufacturing of claim 25, further comprising:
etching the epitaxial layer from the surface of the light extraction structure to form a step on the periphery of the epitaxial layer, wherein the surface of the epitaxial layer is used as the upper step surface of the step structure, and the P-type ohmic contact layer is used as the lower step surface of the step structure;
and forming a protective layer on the surface and the side wall of the epitaxial layer.
30. The method of manufacturing of claim 26, further comprising:
etching the multi-quantum well layer, the carrier barrier layer and the second semiconductor layer to form a plurality of contact through holes, wherein the bottoms of the contact through holes are exposed out of the surface of the first semiconductor layer;
forming an N-type ohmic contact layer at the bottom of the contact through hole;
depositing a dielectric layer on the bottom and the side wall of the contact through hole and the surface of the reflector layer to separate the N-type ohmic contact layer from the epitaxial layer, and the metal bonding layer from the epitaxial layer;
and forming the metal bonding layer on the surface of the dielectric layer, wherein the metal bonding layer is in contact with the N-type ohmic contact layer and fills the contact through hole.
31. The method of manufacturing of claim 30, further comprising:
etching the periphery of the epitaxial layer from the surface of one side where the light extraction structure is located until the reflector layer is exposed;
forming a protective layer on the surface and the side wall of the epitaxial layer;
a second electrode layer is formed on a surface of the mirror layer.
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