CN112186079A - Preparation method of LED chip with vertical structure - Google Patents
Preparation method of LED chip with vertical structure Download PDFInfo
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- CN112186079A CN112186079A CN202011044855.6A CN202011044855A CN112186079A CN 112186079 A CN112186079 A CN 112186079A CN 202011044855 A CN202011044855 A CN 202011044855A CN 112186079 A CN112186079 A CN 112186079A
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- H01—ELECTRIC ELEMENTS
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
Abstract
The invention provides a preparation method of a vertical structure LED chip, which adopts an ultrathin metal substrate as the substrate of the vertical structure LED chip, the metal substrate has excellent electric conduction and heat conduction capability, the electric conduction and heat dissipation capability of the chip can be obviously increased, and the ultimate working performance of the chip is improved; and a metal stress adjusting layer is formed on the second surface of the metal substrate, the metal stress adjusting layer is made of a material different from that of the metal substrate, stress applied to the metal substrate by the epitaxial layer can be compensated, the warping problem of a wafer for preparing the LED chip with the vertical structure is solved, the process yield of wafer scribing is improved, the yield of the LED chip with the vertical structure is improved, and the LED chip with the vertical structure has good technical popularization and application prospects. And the adoption of the ultrathin metal substrate can obviously reduce the size of the LED chip with the vertical structure and meet the requirements of miniaturization and thinning of the chip.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a preparation method of a vertical-structure LED chip.
Background
The vertical structure LED chip adopts the bonding substrate with good electric conduction and heat conduction capability, so that compared with the LED chip with a forward mounting structure and an inverted mounting structure, the vertical structure LED chip has good heat dissipation capability, can bear larger working current, and has remarkably improved brightness and light efficiency, thereby having remarkable technical advantages in the field of high-power illumination. With further advances in display, smart-wear, and lighting applications, chip miniaturization and thinning are required, which poses greater challenges for vertical LED chips.
Because the silicon substrate is low in cost, the conventional vertical-structure LED chip mainly adopts the silicon substrate, so that the conventional vertical-structure LED chip becomes a mainstream substrate transfer scheme of the conventional vertical-structure LED chip. However, as the packaging technology pursues miniaturization and ultra-thinning, the ultra-thin chip process brings serious technical challenges to the silicon-based vertical structure LED chip, and when the chip thickness is reduced to 150um or less, the warpage of the wafer for preparing the vertical structure LED chip is significantly increased due to serious lattice mismatch and thermal mismatch of the III-V group compound and the silicon material, resulting in a great reduction in the chip yield.
Disclosure of Invention
The invention aims to provide a preparation method of a vertical structure LED chip, which is used for improving the stress in the vertical structure LED chip and reducing the warping degree of the chip.
In order to achieve the above object, the present invention provides a method for manufacturing a vertical structure LED chip, comprising:
providing an epitaxial substrate, and forming an epitaxial layer on the epitaxial substrate, wherein the epitaxial layer comprises two semiconductor layers and a light-emitting layer positioned between the two semiconductor layers;
bonding a metal substrate, a metal stress adjusting layer and a supporting substrate on the epitaxial layer, wherein the metal stress adjusting layer is electrically connected with one semiconductor layer through the metal substrate to be used as a first electrode, and the material of the metal stress adjusting layer is different from that of the metal substrate;
separating the epitaxial substrate;
forming a bonding pad electrically connected with the other semiconductor layer to serve as a second electrode; and the number of the first and second groups,
separating the support substrate.
Optionally, before forming the epitaxial layer on the epitaxial substrate, the method further includes:
and forming an epitaxial stress adjusting layer on the epitaxial substrate, wherein the epitaxial stress adjusting layer is a plurality of film layers with gradually changed lattice constants.
Optionally, the two semiconductor layers are an N-type semiconductor layer and a P-type semiconductor layer, where the N-type semiconductor layer is closer to the epitaxial substrate than the P-type semiconductor layer, and before the metal substrate, the metal stress adjustment layer, and the support substrate are bonded on the epitaxial layer, the method further includes:
sequentially forming a P-type contact layer and a reflector layer on the epitaxial layer, wherein the metal substrate is electrically connected with the P-type semiconductor layer through the reflector layer and the P-type contact layer;
and forming the bonding pad on the N-type semiconductor layer after separating the epitaxial substrate.
Optionally, the step of bonding the metal substrate on the epitaxial layer includes:
respectively forming a first bonding material layer and a second bonding material layer on the reflector layer and the metal substrate; and the number of the first and second groups,
the first bonding material layer and the second bonding material layer are fused to bond the metal substrate on the reflector layer, and a bonding layer is formed between the metal substrate and the reflector layer after the first bonding material layer and the second bonding material layer are fused.
Optionally, before the bonding pad is formed on the N-type semiconductor layer, an N-type contact layer is further formed on the N-type semiconductor layer, so that the bonding pad is electrically connected to the N-type semiconductor layer through the N-type contact layer.
Optionally, the two semiconductor layers are an N-type semiconductor layer and a P-type semiconductor layer, where the N-type semiconductor layer is closer to the epitaxial substrate than the P-type semiconductor layer, and before the metal substrate, the metal stress adjustment layer, and the support substrate are bonded on the epitaxial layer, the method further includes:
forming a plurality of N through holes in the epitaxial layer, wherein the N through holes penetrate through the P type semiconductor layer and the light emitting layer and expose the N type semiconductor layer;
forming an N-type contact layer in the N through hole;
sequentially forming a P-type contact layer, a reflector layer, an insulating layer and a conducting layer on the epitaxial layer, wherein the P-type contact layer and the reflector layer are exposed out of the N through hole, the insulating layer also covers the inner wall and part of the bottom wall of the N through hole, and the conducting layer also fills the N through hole and is electrically connected with the N-type semiconductor layer through the N-type contact layer;
and, after separating the epitaxial substrate, further comprising:
forming an opening in the epitaxial layer, wherein the opening penetrates through the epitaxial layer and exposes the P-type contact layer;
and forming the bonding pad in the opening, wherein the bonding pad is electrically connected with the P-type semiconductor layer through the P-type contact layer.
Optionally, the step of bonding the metal substrate on the epitaxial layer includes:
forming a first bonding material layer and a second bonding material layer on the conductive layer and the metal substrate respectively; and the number of the first and second groups,
the first bonding material layer and the second bonding material layer are fused to bond the metal substrate on the conducting layer, and a bonding layer is formed between the metal substrate and the conducting layer after the first bonding material layer and the second bonding material layer are fused.
Optionally, the step of bonding the metal substrate on the epitaxial layer includes:
forming a second bonding material layer on the metal substrate; and the number of the first and second groups,
a portion of the conductive layer merges with the second bonding material layer to bond the metal substrate on the conductive layer, and a bonding layer is formed between the metal substrate and the conductive layer after the portion of the conductive layer merges with the second bonding material layer.
Optionally, the step of bonding the metal substrate, the metal stress adjustment layer, and the support substrate on the epitaxial layer includes:
bonding the metal substrate on the epitaxial layer;
forming the metal stress adjusting layer on the metal substrate; and the number of the first and second groups,
and bonding the supporting substrate on the metal stress adjusting layer.
Optionally, the step of bonding the metal substrate, the metal stress adjustment layer, and the support substrate on the epitaxial layer includes:
forming the metal stress adjusting layer on the metal substrate, and bonding the supporting substrate on the metal stress adjusting layer; and the number of the first and second groups,
bonding the metal substrate to the epitaxial layer.
Optionally, before forming the bonding pad, the surface of the N-type semiconductor layer is also roughened.
Optionally, before or after the pad is formed, a passivation protection material is further formed on the entire surface of the N-type semiconductor layer, so as to form the passivation protection layer, and the passivation protection layer further exposes at least a part of the top surface of the pad.
In the preparation method of the vertical structure LED chip provided by the invention, the ultrathin metal substrate is used as the substrate of the vertical structure LED chip, the electric conduction and heat conduction capability of the metal substrate is excellent, the electric conduction and heat dissipation capability of the chip can be obviously improved, and the ultimate working performance of the chip is improved; and a metal stress adjusting layer is formed on the second surface of the metal substrate, the metal stress adjusting layer is made of a material different from that of the metal substrate, stress applied to the metal substrate by the epitaxial layer can be compensated, the warping problem of a wafer for preparing the LED chip with the vertical structure is solved, the process yield of wafer scribing is improved, the yield of the LED chip with the vertical structure is improved, and the LED chip with the vertical structure has good technical popularization and application prospects.
Further, compared with the conventional semiconductor substrate, the thickness of the metal substrate can be made very thin, for example, 80um to 150um, so that the size of the vertical structure LED chip is significantly reduced, and the requirements for miniaturization and thinning of the chip are met.
Drawings
Fig. 1 is a flowchart of a method for manufacturing an LED chip with a vertical structure according to an embodiment of the present invention;
fig. 2 to fig. 11 are schematic structural diagrams corresponding to corresponding steps of a method for manufacturing an LED chip with a vertical structure according to an embodiment of the present invention, where fig. 11 is a schematic structural diagram of an LED chip with a vertical structure according to an embodiment of the present invention;
fig. 12 to fig. 24 are schematic structural diagrams corresponding to respective steps of a method for manufacturing an LED chip with a vertical structure according to a second embodiment of the present invention, where fig. 24 is a schematic structural diagram of an LED chip with a vertical structure according to the second embodiment of the present invention;
wherein the reference numerals are:
100-an epitaxial substrate; 101-a buffer layer; 200-an epitaxial layer; a 201-N type semiconductor layer; 202-a light emitting layer; 203-P type semiconductor layer; 301-P type contact layer; 302-a mirror layer; 303-N type contact layer; 304-an insulating layer; 305-a conductive layer; 400-a metal substrate; 401-metal stress adjustment layer; 402-a bonding layer; 500-a support substrate; 501-a bonding layer; 600-a pad; 700-passivation protective layer;
200a, 200 c-openings; 200b-N vias.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
Fig. 11 is a schematic structural diagram of the vertical LED chip provided in this embodiment. As shown in fig. 11, the vertical LED chip provided in this embodiment is an opposite-polarity LED chip, and includes a metal substrate 400, an epitaxial layer 200, a metal stress adjustment layer 401, and a bonding pad 600, wherein the epitaxial layer 200 and the metal stress adjustment layer 401 are respectively located on a first surface and a second surface of the metal substrate 400, and the bonding pad 600 is located on the epitaxial layer 200. It is understood that, in this embodiment, the first surface refers to an upper surface of the metal substrate 400, and the second surface refers to a lower surface of the metal substrate 400.
With reference to fig. 11, the metal substrate 400 is made of a metal material such as molybdenum (Mo), copper (Cu), molybdenum-copper alloy (CuMo), copper-tungsten alloy (CuW), or silicon-aluminum alloy (AlSi), and the thickness of the metal substrate 400 can be made very thin compared to a silicon substrate, thereby reducing the size of the chip. In this embodiment, the thickness of the metal substrate 400 is 80um to 150um, for example, 100um, 120um or 140 um.
The epitaxial layer 200 is located on a first surface of the metal substrate 400, and includes two semiconductor layers and a light emitting layer 202 located between the two semiconductor layers. Specifically, the two semiconductor layers are a P-type semiconductor layer 203 and an N-type semiconductor layer 201, respectively, and the P-type semiconductor layer 203, the light emitting layer 202 and the N-type semiconductor layer 201 are sequentially stacked from bottom to top. In this embodiment, the P-type semiconductor layer 203 is a P-GaN layer; the light emitting layer 202 is a multi-period quantum well layer (MQWS), the material of the quantum well layer is any one or combination of AlN, GaN, AlGaN, InGaN and AlInGaN, and the corresponding wavelength range is 365 nm-600 nm; the N-type semiconductor layer 201 is, for example, u-GaN or N-GaN superlattice structure, and specifically includes: between u-GaN and n-GaN, Al composition is gradually changed (gradually decreased) from u-GaN to n-GaN, and the superlattice structure of AlxGa1-xN/AlyGa1-yN is formed, wherein y is more than 0 and less than x is less than 1.
It should be understood that other film layers may also be formed in the epitaxial layer 200, for example, an EBL electron blocking layer may also be formed between the light emitting layer 202 and the P-type semiconductor layer 203.
Referring to fig. 11, the metal stress adjustment layer 401 is located on the second surface of the metal substrate 400, and is electrically connected to the P-type semiconductor layer 203 in the epitaxial layer 200 through the metal substrate 400 to serve as a first electrode of the vertical LED chip, and at this time, the first electrode is a P-electrode.
Further, the material of the metal stress adjustment layer 401 is different from the material of the metal substrate 400, so that the stress applied on the metal substrate 400 by the epitaxial layer 200 can be compensated, and the metal substrate 400 is prevented from warping. Optionally, the material of the metal stress adjustment layer 401 includes one or more of titanium (Ti), nickel (Ni), chromium (Cr), molybdenum (Mo), tungsten (W), or copper (Cu); and the thickness of the metal stress adjustment layer 401 is 0.5 um-10 um, for example 1um, 5um or 8um, etc., because the thickness of the metal stress adjustment layer 401 is thinner, the size of the chip is not increased too much.
In this embodiment, an epitaxial stress adjustment layer (not shown) is further formed on the N-type semiconductor layer 201, and the epitaxial stress adjustment layer is a plurality of film layers with gradually changed lattice constants, so as to further adjust stress in the epitaxial layer 200 and prevent the vertical-structure LED chip from warping or cracking. The epitaxial stress adjusting layer can be made of AlGaN and InGaN, and the gradient of the lattice constant can be realized by adjusting the proportion of Al and In each film layer of the epitaxial stress adjusting layer, so that the stress of the film layer In the epitaxy is compensated. Optionally, the thickness of the epitaxial stress adjustment layer is 0.2um to 1 um.
With reference to fig. 11, a mirror layer 302 and a P-type contact layer 301 are sequentially stacked from bottom to top between the metal substrate 400 and the P-type semiconductor layer 203, and the metal substrate 400 is actually electrically connected to the P-type semiconductor layer 203 through the mirror layer 302 and the P-type contact layer 301. In this embodiment, the P-type contact layer 301 is made of materials such as nickel gold, nickel silver, ITO, etc., so as to realize ohmic contact between the metal substrate 400 and the P-type semiconductor layer 203; the mirror layer 302 is a mirror made of metal such as silver (Ag), platinum (Pt), tungsten (W), or titanium (Ti), and reflects light emitted from the epitaxial layer 200 toward the metal substrate 400.
With reference to fig. 11, the bonding pad 600 is disposed on the epitaxial layer 200, and more particularly on the N-type semiconductor layer 201 of the epitaxial layer 200, the bonding pad 600 is electrically connected to the N-type semiconductor layer 201 to serve as a second electrode of the vertical LED chip, and at this time, the second electrode is an N-electrode. Alternatively, the material of the bonding pad 600 may be a metal material such as chromium (Cr), platinum (Pt), or Au (gold).
As an alternative embodiment, an N-type contact layer may be further formed between the bonding pad 600 and the N-type semiconductor layer 201, so as to realize ohmic contact between the bonding pad 600 and the N-type semiconductor layer 201. The material of the N-type contact layer may be one or more of chromium (Cr), aluminum (Al), titanium (Ti), or gold (Au). It is understood that the N-type contact layer may actually be omitted.
Further, a bonding layer 402 is further disposed between the metal substrate 400 and the mirror layer 302, and the bonding layer 402 is used for achieving bonding between the metal substrate 400 and the mirror layer 302. Alternatively, the material of the bonding layer 402 may be a metal alloy, such as one of binary eutectic metal systems composed of high-melting-point metals, such as gold (Au), nickel (Ni), copper (Cu), and silver (Ag), and low-melting-point metals, such as tin (Sn) and indium (In).
With reference to fig. 11, the epitaxial layer 200 has an opening 200a, the opening 200a is located at an edge of the epitaxial layer 200 and exposes the P-type contact layer 301, that is, the opening 200a has only one sidewall. The N-type semiconductor layer 201 is further provided with a passivation protection layer 700, the passivation protection layer 700 covers the surface of the N-type semiconductor layer 201 and extends to cover the side wall and the bottom wall of the opening 200a, that is, the passivation protection layer 700 covers the entire surface of the chip, so as to protect the structures such as the N-type semiconductor layer 201 in the vertical LED chip, and the passivation protection layer 700 is made of, for example, silicon oxide and has a thickness of 200nm to 500 nm. It should be understood that at least a portion of the top surface of the pad 600 is exposed from the passivation protection layer 700.
Fig. 1 is a flowchart of a method for manufacturing an LED chip with a vertical structure according to this embodiment. As shown in fig. 1, the method for manufacturing the vertical structure LED chip includes:
step S100: providing an epitaxial substrate, and forming an epitaxial layer on the epitaxial substrate, wherein the epitaxial layer comprises two semiconductor layers and a light-emitting layer positioned between the two semiconductor layers;
step S200: bonding a metal substrate, a metal stress adjusting layer and a supporting substrate on the epitaxial layer, wherein the metal stress adjusting layer is electrically connected with one semiconductor layer through the metal substrate to be used as a first electrode, and the material of the metal stress adjusting layer is different from that of the metal substrate;
step S300: separating the epitaxial substrate;
step S400: forming a bonding pad electrically connected with the other semiconductor layer to serve as a second electrode; and the number of the first and second groups,
step S500: separating the support substrate.
Fig. 2 to fig. 11 are schematic structural diagrams corresponding to corresponding steps of the method for manufacturing an LED chip with a vertical structure according to this embodiment. Next, a method for manufacturing the vertical structure LED chip provided in this embodiment will be described in detail with reference to fig. 2 to 11.
Referring to fig. 2, step S100 is performed to provide an epitaxial substrate 100, wherein the epitaxial substrate 100 is one of heterogeneous substrates, which may be gallium oxide (Ga)2O3) Substrate, silicon carbide (SiC) substrate, silicon (Si) substrate, sapphire (Al)2O3) A substrate, a zinc oxide (ZnO) single crystal substrate, and a high temperature resistant metal substrate 400 with a pre-deposited AlN film, etc., in this embodiment, the epitaxial substrate 100 is a mirror sapphire substrate or a micron/nanometer patterned sapphire substrate. The epitaxial substrate 100 may be a 1-8 inch wafer with a thickness of 300um to 2 mm.
Next, a buffer layer 101 is formed on the epitaxial substrate 100, the material of the buffer layer 101 may be GaN/AlN grown at a low temperature, or may also be AlN prepared by sputtering, and the buffer layer 101 serves as a buffer structure between the epitaxial substrate 100 and the subsequently formed epitaxial layer 200, so as to facilitate separation of the epitaxial substrate 100 and the subsequently formed epitaxial layer 200 through the buffer layer 101 in a subsequent process.
Next, an epitaxial stress adjustment layer (not shown) is formed on the buffer layer 101, and the method for forming the epitaxial stress adjustment layer may be: and depositing an epitaxial stress film on the buffer layer 101 by adopting the technologies of metal chemical vapor deposition, laser-assisted molecular beam epitaxy, laser sputtering or hydride vapor phase epitaxy and the like, thereby forming the epitaxial stress adjustment layer. In this embodiment, the epitaxial stress adjustment layer adopts AlGaN or InGaN materials with gradually changed compositions according to the lattice constant of the epitaxial substrate 100 and the lattice constant difference of three materials (AlN, GaN, InN) in the epitaxial layer formed later, so that the lattice constants of the buffer layer 101 and the epitaxial layer are substantially close to each other from a larger difference, thereby reducing the stress difference between the buffer layer 101 and the epitaxial layer.
Next, an epitaxial layer 200 is formed on the epitaxial stress adjustment layer, the epitaxial layer 200 includes an N-type semiconductor layer 201, a light emitting layer 202, and a P-type semiconductor layer 203 stacked in sequence from bottom to top, and a method for forming the epitaxial layer 200 may be: and depositing an epitaxial film with a polycrystalline or single-crystal structure on the epitaxial stress adjustment layer by adopting the technologies of metal chemical vapor deposition, laser-assisted molecular beam epitaxy, laser sputtering or hydride vapor phase epitaxy and the like. In this embodiment, the thickness of the epitaxial layer 200 is 5 μm to 8 μm.
Referring to fig. 3, a P-type contact layer 301 and a mirror layer 302 are sequentially formed on the epitaxial layer 200. The method for forming the P-type contact layer 301 and the mirror layer 302 may be: and forming a contact layer material and a reflector layer material on the epitaxial layer 200 by adopting an electron beam evaporation process, thereby forming the P-type contact layer 301 and the reflector layer 302.
Referring to fig. 4, step S200 is performed to provide a metal substrate 400, and the first surface of the metal substrate 400 is bonded to the upper surface of the mirror layer 302. Specifically, the method for bonding the metal substrate 400 may be: forming a first bonding material layer and a second bonding material layer on the upper surface of the mirror layer 302 and the first surface of the metal substrate 400, respectively, then bonding the first bonding material layer and the second bonding material layer together, and then fusing the first bonding material layer and the second bonding material layer together at a certain temperature by using a liquid phase transient bonding process to realize the permanent bonding of the metal substrate 400 and the mirror layer 302. After the first bonding material layer and the second bonding material layer are fused, a bonding layer 402 is formed between the mirror layer 302 and the metal substrate 400.
Optionally, the first bonding material layer and the second bonding material layer may be made of the same material, for example, a binary bonding layer made of an alloy of a high melting point metal and a low melting point metal; of course, the materials of the first bonding material layer and the second bonding material layer may be different, for example, one of the upper surface of the mirror layer 302 and the first surface of the metal substrate 400 forms a high melting point metal layer, and the other forms a low melting point metal layer.
Optionally, before forming the first bonding material layer and the second bonding material layer on the upper surface of the mirror layer 302 and the first surface of the metal substrate 400, an adhesion layer (not shown) may be formed on the upper surface of the mirror layer 302 and the first surface of the metal substrate 400, so as to enhance adhesion between the first bonding material layer and the upper surface of the mirror layer 302 and between the second bonding material layer and the first surface of the metal substrate 400, and avoid delamination. The adhesion layer material may be titanium.
Next, a metal stress adjustment layer 401 is formed on the second surface of the metal substrate 400. The method for forming the metal stress adjustment layer 401 may be: forming a metal stress adjustment layer material on the second surface of the metal substrate 400 by using sputtering, physical vapor deposition, chemical plating, or electroplating, thereby forming the metal stress adjustment layer 401. It is understood that, at this time, the metal stress adjustment layer 401 is electrically connected to the P-type semiconductor layer 203 through the metal substrate 400, the mirror layer 302 and the P-type contact layer 301, and can be subsequently used as a P-electrode of the vertical LED chip without forming an additional pad.
Referring to fig. 5, a supporting substrate 500 is provided, and the supporting substrate 500 is bonded to the metal stress adjustment layer 401, and the supporting substrate 500 can provide support after the epitaxial substrate 100 is separated, and can also limit the deformation of the metal substrate 400, so as to prevent the metal substrate 400 from warping. Specifically, the method of bonding the supporting substrate 500 may be: forming an adhesive layer 501 on the supporting substrate 500, and adhering the surface of the supporting substrate 500 and the surface of the metal stress adjustment layer 401 together to achieve temporary bonding of the metal stress adjustment layer 401 and the supporting substrate 500.
Further, the support substrate 500 may be a high-purity quartz glass support substrate, a silicon substrate, a sapphire substrate, or the like; the thickness of the support substrate 500 is 300 um-10 mm. The material of the bonding layer 501 may be a metal material with a low melting point, such as indium and tin, or an organic bonding material, such as PDMS, PMMA or PET, as long as temporary bonding and separation are achieved, and the invention is not limited; the thickness of the bonding layer 501 is 0.5um to 10 um.
In this embodiment, the metal substrate 400 is bonded first, then the metal stress adjustment layer 401 is formed on the metal substrate 400, and then the supporting substrate 500 is bonded on the metal stress adjustment layer 401, so that the difficulty in manufacturing is low, and the metal substrate 400 is bonded first, which can also prevent the metal substrate 400 from warping caused by the stress adjustment layer 401 being manufactured first; but the invention is not limited thereto. As an alternative embodiment, the metal stress adjustment layer 401 may be formed on the metal substrate 400, the supporting substrate 500 may be bonded on the metal stress adjustment layer 401, and then the metal substrate 400, the metal stress adjustment layer 401, and the supporting substrate 500 may be bonded to the mirror layer 302 as a whole.
Referring to fig. 6, step S300 is performed to separate the epitaxial substrate 100 with the support substrate 500 as a support. In this embodiment, ultraviolet laser with a certain wavelength (for example, 248nm) is used, a small spot with a certain size (for example, 200um) is used to irradiate the buffer layer 101 on the epitaxial substrate 100, and under the irradiation of the ultraviolet laser, the buffer layer 101 is decomposed, so that the epitaxial substrate 100 and the epitaxial layer 200 are separated.
Further, since a part of the u-GaN in the N-type semiconductor layer 201 is decomposed into metal Ga after the irradiation of the ultraviolet laser, the present embodiment also uses a dilute hydrochloric acid solution to remove the metal Ga formed by the decomposition, thereby avoiding the metal Ga from causing adverse effects on the vertical LED chip. Next, the epitaxial layer 200 may be etched to the heavily doped N-GaN in the N-type semiconductor layer 201 using, for example, an ICP dry etching process to reveal the heavily doped N-GaN in the N-type semiconductor layer 201.
It should be understood that, since the buffer layer 101 in this embodiment is made of GaN or AlN material, the method of ultraviolet laser irradiation is used to separate the epitaxial substrate 100, when the material of the epitaxial substrate 100 is changed, the epitaxial substrate 100 may also be separated by other methods such as etching, for example, the epitaxial substrate 100 is replaced by a silicon substrate, after the support substrate 500 is bonded, the epitaxial substrate 100 may be thinned by a grinding process, and then the support substrate 500 is removed by a silicon etchant, so that the separation of the epitaxial substrate 100 is achieved.
Referring to fig. 7, the upper surface of the N-type semiconductor layer 201 (specifically, the upper surface of N-GaN) is etched by a hot KOH solution (e.g., 50-70 ℃) with a certain concentration (e.g., 2-6 mol/L) to roughen the N-type semiconductor layer 201, thereby improving the light emitting efficiency.
Referring to fig. 8, an opening 200a is formed in the epitaxial layer 200, where the opening 200a is located at an edge of the epitaxial layer 200, penetrates through the epitaxial layer 200, and exposes the P-type contact layer 301, that is, the opening 200a has only one sidewall. The openings 200a serve as scribe lanes for assisting scribing in a subsequent step. Optionally, an inclination angle between the side wall and the bottom wall of the opening 200a may be 30 ° to 60 °, and the inclination angle is preferably 40 °, so that the light extraction efficiency of the LED chip in the horizontal direction may be increased, thereby increasing the light emission of the LED chip.
Referring to fig. 9, step S400 is performed to form a bonding pad 600 on the N-type semiconductor layer 201, wherein the bonding pad 600 is electrically connected to the N-type semiconductor layer 201 to serve as an N electrode. The steps of forming the pad 600 may be: a metal material is prepared on the N-type semiconductor layer 201 using photolithography and an electron beam evaporation process, thereby forming the pad 600.
As an alternative embodiment, before forming the bonding pad 600, an N-type contact layer may be formed on the N-type semiconductor layer 201, the N-type contact layer covers a portion of the surface of the N-type semiconductor layer 201, and then the bonding pad 600 is formed on the N-type contact layer, the N-type contact layer is located between the bonding pad 600 and the N-type semiconductor layer 201, so that the bonding pad 600 may form an ohmic contact with the N-type semiconductor layer 201.
Next, a passivation protection material may be deposited on the entire surface to form a passivation protection layer 700, and the passivation protection layer 700 may cover the entire surface of the N-type semiconductor layer 201 and cover the sidewalls and the bottom wall of the opening 200a, so as to isolate the epitaxial layer 200 from the outside to protect the epitaxial layer 200. It should be understood that at least a portion of the top surface of the pad 600 needs to be exposed to the passivation protection layer 700, so as to serve as a lead-out terminal for a subsequent packaging process, therefore, after the passivation protection layer 700 is formed, an etching process may be performed to remove a portion of the passivation protection layer 700, so as to expose at least a portion of the top surface of the pad 600.
As an alternative embodiment, the passivation protection layer 700 may also be formed before the bonding pad 600 is formed, so that the passivation protection layer 700 needs to be etched to form an opening for accommodating the bonding pad 600 before the bonding pad 600 is formed.
Referring to fig. 10, step S500 is performed to separate the supporting substrate 500. Specifically, the bonding layer 501 may be dissolved by an organic solution, so that the supporting substrate 500 is separated from the metal stress adjustment layer 401. As an alternative embodiment, the adhesive layer 501 may also be removed by physical means such as heating, laser, etc., and a person skilled in the art may select a specific manner for separating the supporting substrate 500 according to the material of the adhesive layer 501, which will not be explained herein.
Referring to fig. 11, a scribing process is performed, and a grinding wheel or a laser (water-guided laser, laser surface cutting) is used to cut down along the opening 200a to divide the wafer into individual vertical LED chips, wherein the cutting scheme may be single-sided cutting or double-sided cutting. Since the metal stress adjusting layer 401 is provided to compensate the stress applied by the epitaxial layer 200, the wafer is not easy to warp.
Example two
Fig. 24 is a schematic structural diagram of the vertical LED chip provided in this embodiment. As shown in fig. 24, the difference from the first embodiment is that, in the present embodiment, the vertical LED chip is a positive LED chip, the first electrode is an N electrode, and the second electrode is a P electrode.
With reference to fig. 24, a conductive layer 305, an insulating layer 304, a mirror layer 302 and a P-type contact layer 301 are sequentially stacked from bottom to top between the metal substrate 400 and the N-type semiconductor layer 201. The epitaxial layer 200 has a plurality of N vias 200b and openings 200c therein.
Specifically, the N-via 200b penetrates the mirror layer 302, the P-type contact layer 301, the P-type semiconductor layer 203, and the light emitting layer 202 and exposes the N-type semiconductor layer 201. An N-type contact layer 303 is formed in the N-via 200b, and a gap is formed between the N-type contact layer 303 and a sidewall of the N-via 200 b. The insulating layer 304 further covers the sidewall and a part of the bottom wall (the part other than the N-type contact layer 303) of the N-via 200b and at least fills the gap, so as to prevent a short circuit between the N-type semiconductor layer 201 and the P-type semiconductor layer 203 exposed in the N-via 200b, the conductive layer 305 further fills the N-via 200b, and the metal substrate 400 is electrically connected to the N-type semiconductor layer 201 through the conductive layer 305 and the N-type contact layer 303. In this way, the metal stress adjustment layer 401 can be used as the first electrode of the vertical LED chip, and the first electrode is an N electrode.
In this embodiment, the thickness of the conductive layer 305 is 500nm to 5000 nm.
Further, the opening 200c penetrates through the epitaxial layer 200 and exposes the P-type contact layer 301, and the opening 200c is located at the edge of the epitaxial layer 200, that is, the opening 200c has only one sidewall. The pad 600 is located in the opening 200 c. The pad 600 is located in the opening 200c and electrically connected to the P-type semiconductor layer 203 through the P-type contact layer 301. In this way, the bonding pad 600 can serve as the second electrode of the vertical LED chip, and the second electrode is a P electrode.
Alternatively, the material of the insulating layer 304 may be an insulating material such as silicon nitride.
Further, a bonding layer 402 is further disposed between the metal substrate 400 and the conductive layer 305, and the bonding layer 402 is used for achieving bonding between the metal substrate 400 and the conductive layer 305. Optionally, the material of the bonding layer 402 may be one of binary eutectic metal systems composed of high-melting-point metals such as gold (Au), nickel (Ni), copper (Cu), silver (Ag), and low-melting-point metals such as tin (Sn), indium (In).
With reference to fig. 24, the N-type semiconductor layer 201 further has a passivation layer 700 thereon, and the passivation layer 700 covers the surface of the N-type semiconductor layer 201 and extends to cover the sidewall of the opening 200c and the bottom wall except the bonding pad 600, that is, the passivation layer 700 covers the entire chip, so as to protect the N-type semiconductor layer 201 inside the vertical LED chip. It is to be understood that at least a portion of the top surface of the pad 600 needs to be exposed from the passivation protection layer 700.
Fig. 12 to fig. 24 are schematic structural diagrams corresponding to respective steps of the method for manufacturing an LED chip with a vertical structure according to this embodiment. Next, a method for manufacturing the vertical structure LED chip provided in the present embodiment will be described in detail with reference to fig. 12 to 24.
Referring to fig. 12, different from the method for manufacturing the vertical LED chip according to the first embodiment, in this embodiment, after the epitaxial layer 200 is formed, a plurality of N through holes 200b are further formed in the epitaxial layer 200, and the N through holes 200b penetrate through the P-type semiconductor layer 203 and the light emitting layer 202 and expose the N-type semiconductor layer 201.
Referring to fig. 13, an N-type contact layer 303 is formed in the N-via 200 b. A gap is formed between the N-type contact layer 303 and the sidewall of the N-via 200b, so as to accommodate an insulating layer later.
Referring to fig. 14, a P-type contact layer 301 and a mirror layer 302 are sequentially formed on the epitaxial layer 200, and the method for forming the P-type contact layer 301 and the mirror layer 302 may be the same as that of the first embodiment. It should be understood that when the P-type contact layer 301 and the mirror layer 302 are formed, a photoresist may be covered on the N-via 200b, thereby preventing the materials of the P-type contact layer 301 and the mirror layer 302 from entering into the N-via 200 b. After the P-type contact layer 301 and the mirror layer 302 are formed, the N-via 200b extends upward to the upper surface of the mirror layer 302, and at this time, the N-type semiconductor layer 201 and the P-type semiconductor (the P-type contact layer 301 and the P-type semiconductor layer 203) are partially exposed in the N-via 200 b.
Next, an insulating layer 304 is formed on the mirror layer 302, the insulating layer 304 covers the mirror layer 302, covers the sidewall and a part of the bottom wall (a part other than the N-type contact layer 303) of the N-via 200b, and fills at least the gap, and the insulating layer 304 insulates the P-type semiconductor layer 201 from the N-type semiconductor layer exposed in the N-via 200 b.
Referring to fig. 15, a conductive layer 305 is formed on the insulating layer 304, the conductive layer 305 covers the insulating layer 304 and fills the N-via 200b, and at this time, the conductive layer 305 is electrically connected to the N-type semiconductor layer 201 through the N-type contact layer 303.
Referring to fig. 16, a first surface of the metal substrate 400 and an upper surface of the conductive layer 305 are bonded together, and a stress adjustment layer is formed on a second surface of the metal substrate 400. As in the first embodiment, the bonding may also be achieved by forming a first bonding material layer and a second bonding material layer on the first surface of the metal substrate 400 and the conductive layer 305, respectively. The first bonding material layer and the second bonding material layer are fused to form a bonding layer 402 between the metal substrate 400 and the conductive layer 305.
As an alternative embodiment, the material of the conductive layer 305 may be a bonding material, so that the conductive layer 305 not only can achieve the electrical connection between the metal substrate 400 and the N-type semiconductor layer 201, but also can serve as a bonding material layer to achieve the bonding between the metal substrate 400 and the mirror layer 302. For example, the material of the conductive layer 305 is, for example, gold, after the conductive layer 305 is formed, a second bonding material layer is formed on the metal substrate 400, the material of the second bonding material layer is, for example, a silicon material with a nanometer thickness prepared by a sputtering method, and then the conductive layer 305 is bonded to the metal substrate 400, a part of the conductive layer 305 reacts with silicon to generate a compound, so that a bonding layer 402 is formed between the conductive layer 305 and the metal substrate 400, and thus, a step of forming a first bonding material layer on the conductive layer 305 can be omitted, and the process is simplified.
Optionally, before forming the second bonding material layer on the first surface of the metal substrate 400 or before forming the conductive layer 305 on the insulating layer 304, an adhesion layer (not shown) may be formed on the first surface of the metal substrate 400 and the insulating layer 304 to increase adhesion. The thickness of the adhesion layer is 500 nm-5000 nm.
Referring to fig. 17, the supporting substrate 500 is bonded to the metal stress adjustment layer 401 through an adhesive layer 501.
Referring to fig. 18 to 19, the epitaxial substrate 100 is separated from the epitaxial layer 200.
Referring to fig. 20, the surface of the N-type semiconductor layer 201 is roughened, so as to increase the light extraction efficiency.
Referring to fig. 21, an opening 200c is formed in the epitaxial layer 200, and the opening 200c penetrates through the epitaxial layer 200 and exposes the P-type contact layer 301. The width of the opening 200c may be appropriately large to accommodate a pad 600 to be formed later, and also to serve as a scribe line.
Referring to fig. 22, a pad 600 is formed in the opening 200c, and the pad 600 is electrically connected to the P-type semiconductor layer 203 through the P-type contact layer 301 to serve as a second electrode, which is a P-electrode. A passivation protection material is then deposited over the entire surface to form a passivation protection layer 700, wherein the passivation protection layer 700 covers the N-type semiconductor layer 201 and extends to cover the sidewalls of the opening 200c and the bottom wall except the pad 600.
Referring to fig. 23 to 24, the second substrate supporting substrate 500 is separated from the metal stress adjustment layer 401, and a dicing process is performed to obtain the vertical LED chip.
In conclusion, in the preparation method of the vertical structure LED chip provided by the invention, the ultrathin metal substrate is adopted as the substrate of the vertical structure LED chip, the electric conduction and heat conduction capability of the metal substrate is excellent, the electric conduction and heat dissipation capability of the chip can be obviously improved, and the ultimate working performance of the chip is improved; and a metal stress adjusting layer is formed on the second surface of the metal substrate, the metal stress adjusting layer is made of a material different from that of the metal substrate, stress applied to the metal substrate by the epitaxial layer can be compensated, the warping problem of a wafer for preparing the LED chip with the vertical structure is solved, the process yield of wafer scribing is improved, the yield of the LED chip with the vertical structure is improved, and the LED chip with the vertical structure has good technical popularization and application prospects.
Further, compared with the conventional semiconductor substrate, the thickness of the metal substrate can be made very thin, for example, 80um to 150um, so that the size of the vertical structure LED chip is significantly reduced, and the requirements for miniaturization and thinning of the chip are met.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (12)
1. A preparation method of a vertical structure LED chip is characterized by comprising the following steps:
providing an epitaxial substrate, and forming an epitaxial layer on the epitaxial substrate, wherein the epitaxial layer comprises two semiconductor layers and a light-emitting layer positioned between the two semiconductor layers;
bonding a metal substrate, a metal stress adjusting layer and a supporting substrate on the epitaxial layer, wherein the metal stress adjusting layer is electrically connected with one semiconductor layer through the metal substrate to be used as a first electrode, and the material of the metal stress adjusting layer is different from that of the metal substrate;
separating the epitaxial substrate;
forming a bonding pad electrically connected with the other semiconductor layer to serve as a second electrode; and the number of the first and second groups,
separating the support substrate.
2. The method for manufacturing a vertical structure LED chip according to claim 1, further comprising, before forming the epitaxial layer on the epitaxial substrate:
and forming an epitaxial stress adjusting layer on the epitaxial substrate, wherein the epitaxial stress adjusting layer is a plurality of film layers with gradually changed lattice constants.
3. The method according to claim 1, wherein the two semiconductor layers are an N-type semiconductor layer and a P-type semiconductor layer, respectively, the N-type semiconductor layer is closer to the epitaxial substrate than the P-type semiconductor layer, and the method further comprises, before bonding the metal substrate, the metal stress adjustment layer, and the support substrate on the epitaxial layer:
sequentially forming a P-type contact layer and a reflector layer on the epitaxial layer, wherein the metal substrate is electrically connected with the P-type semiconductor layer through the reflector layer and the P-type contact layer;
and forming the bonding pad on the N-type semiconductor layer after separating the epitaxial substrate.
4. The method for manufacturing a vertical structure LED chip according to claim 3, wherein the step of bonding the metal substrate on the epitaxial layer comprises:
respectively forming a first bonding material layer and a second bonding material layer on the reflector layer and the metal substrate; and the number of the first and second groups,
the first bonding material layer and the second bonding material layer are fused to bond the metal substrate on the reflector layer, and a bonding layer is formed between the metal substrate and the reflector layer after the first bonding material layer and the second bonding material layer are fused.
5. The method for manufacturing a vertical structure LED chip according to claim 3, wherein an N-type contact layer is further formed on the N-type semiconductor layer before the bonding pad is formed on the N-type semiconductor layer, so that the bonding pad is electrically connected to the N-type semiconductor layer through the N-type contact layer.
6. The method according to claim 1, wherein the two semiconductor layers are an N-type semiconductor layer and a P-type semiconductor layer, respectively, the N-type semiconductor layer is closer to the epitaxial substrate than the P-type semiconductor layer, and the method further comprises, before bonding the metal substrate, the metal stress adjustment layer, and the support substrate on the epitaxial layer:
forming a plurality of N through holes in the epitaxial layer, wherein the N through holes penetrate through the P type semiconductor layer and the light emitting layer and expose the N type semiconductor layer;
forming an N-type contact layer in the N through hole;
sequentially forming a P-type contact layer, a reflector layer, an insulating layer and a conducting layer on the epitaxial layer, wherein the P-type contact layer and the reflector layer are exposed out of the N through hole, the insulating layer also covers the inner wall and part of the bottom wall of the N through hole, and the conducting layer also fills the N through hole and is electrically connected with the N-type semiconductor layer through the N-type contact layer;
and, after separating the epitaxial substrate, further comprising:
forming an opening in the epitaxial layer, wherein the opening penetrates through the epitaxial layer and exposes the P-type contact layer;
and forming the bonding pad in the opening, wherein the bonding pad is electrically connected with the P-type semiconductor layer through the P-type contact layer.
7. The method for manufacturing a vertical structure LED chip according to claim 6, wherein the step of bonding the metal substrate on the epitaxial layer comprises:
forming a first bonding material layer and a second bonding material layer on the conductive layer and the metal substrate respectively; and the number of the first and second groups,
the first bonding material layer and the second bonding material layer are fused to bond the metal substrate on the conducting layer, and a bonding layer is formed between the metal substrate and the conducting layer after the first bonding material layer and the second bonding material layer are fused.
8. The method for manufacturing a vertical structure LED chip according to claim 6, wherein the step of bonding the metal substrate on the epitaxial layer comprises:
forming a second bonding material layer on the metal substrate; and the number of the first and second groups,
a portion of the conductive layer merges with the second bonding material layer to bond the metal substrate on the conductive layer, and a bonding layer is formed between the metal substrate and the conductive layer after the portion of the conductive layer merges with the second bonding material layer.
9. The method for manufacturing an LED chip having a vertical structure according to any one of claims 1 to 8, wherein the step of bonding the metal substrate, the metal stress adjustment layer, and the support substrate on the epitaxial layer comprises:
bonding the metal substrate on the epitaxial layer;
forming the metal stress adjusting layer on the metal substrate; and the number of the first and second groups,
and bonding the supporting substrate on the metal stress adjusting layer.
10. The method for manufacturing an LED chip having a vertical structure according to any one of claims 1 to 8, wherein the step of bonding the metal substrate, the metal stress adjustment layer, and the support substrate on the epitaxial layer comprises:
forming the metal stress adjusting layer on the metal substrate, and bonding the supporting substrate on the metal stress adjusting layer; and the number of the first and second groups,
bonding the metal substrate to the epitaxial layer.
11. The method for manufacturing a vertical structure LED chip according to any one of claims 3 to 8, wherein the surface of the N-type semiconductor layer is also roughened before the bonding pad is formed.
12. The method for manufacturing a vertical structure LED chip according to any one of claims 3 to 8, wherein a passivation protective material is further formed on the entire surface of the N-type semiconductor layer before or after the formation of the bonding pad, thereby forming the passivation protective layer, and the passivation protective layer also exposes at least a part of the top surface of the bonding pad.
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