JP2012142401A - Semiconductor chip manufacturing method and semiconductor wafer division method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor chip manufacture method which allows a semiconductor chip used in a face-down (FD) mounting to be more easily manufactured.SOLUTION: A manufacturing method of a light-emitting element 20 as an example of a semiconductor element comprises: a semiconductor element formation step of forming the light-emitting element 20 on a substrate 10; a protruded electrode formation step of forming a first protruded electrode 210 on a first electrode 170 and a second protruded electrode 220 on a second electrode 180 of the light-emitting element 20; a brittle region formation step (FIG.7(a)) of forming a brittle region 321 in a division scheduled surface of the substrate 10; and a division step (FIG.7(b) and (c)) of dividing a wafer 30 in which the light-emitting element 20 is formed on the substrate 10 into light-emitting chips 1 starting at the brittle region 321.

Description

  The present invention relates to a method for manufacturing a semiconductor chip and a method for dividing a semiconductor wafer.

Semiconductor elements such as light emitting diodes (LEDs) and integrated circuits (LSIs) are divided (cut) into a semiconductor wafer in which a plurality of semiconductor elements are collectively formed on a substrate so that each includes the semiconductor elements. The processed semiconductor chip is used.
As a method of dividing a semiconductor wafer into semiconductor chips, a stealth dicing method in which a laser beam is condensed by an objective lens optical system and irradiated to the inside of the substrate to form a weak region in the substrate with a lower strength than before irradiation. There is. In this method, a semiconductor wafer is divided (cut) into semiconductor chips starting from a fragile region formed in the substrate.
In addition, these semiconductor chips are mounted on a package, a wiring board, or the like with the side on which the semiconductor element is provided facing away from the side of the package or the like (referred to as face-up (FU) mounting), or the semiconductor element. It is used by being mounted so that the side faces a package or the like (referred to as face-down (FD) mounting or flip-chip (FC) mounting).

  Patent Document 1 discloses a resin layer forming step of forming an insulating resin layer on a circuit surface so that the protruding electrode is embedded in a semiconductor wafer having a protruding electrode on the circuit surface, and a support tape on the surface of the insulating resin layer. A support tape fixing process for attaching and fixing, and in a state of being fixed to the support tape, a laser beam is irradiated from the opposite side of the circuit surface of the semiconductor wafer to form a fragile layer inside the semiconductor wafer along the dicing pattern A fragile layer forming step, and a dicing step of dividing the semiconductor wafer including the insulating resin layer along the dicing pattern by extending the supporting tape in the in-plane direction, and dividing the semiconductor wafer into a plurality of semiconductor chips, A method for dicing a semiconductor wafer comprising:

JP 2009-260214 A

By the way, even if the weak region is formed inside the substrate by the stealth dicing method, since the weak region is provided inside the substrate, the semiconductor wafer is not always easily started from the weak region formed inside the substrate. And it was not necessarily divided into chips. If the chip cannot be easily divided, the pn junction portion of the semiconductor chip is forcibly divided by applying a large load (when the chip is a semiconductor light emitting element chip, the regions of the n-type semiconductor layer, the light-emitting layer, and the p-type semiconductor layer are Can cause many defective chips that generate leakage current.
Therefore, a groove (trench or groove) having a U-shaped or V-shaped cross-section is formed on one surface of the semiconductor wafer corresponding to the fragile region to be formed by laser light irradiation, dry etching, wet etching, or the like. It is provided. In this case, the semiconductor wafer is more easily divided into chips, with the groove on the surface of the semiconductor wafer being the starting point of the division. Further, when a groove is provided by irradiating the surface of the semiconductor wafer with laser light, the semiconductor wafer constituent material in the groove portion may scatter and contaminate the surface of the semiconductor element.
From such a background, it is necessary to make the groove deep and wide in order to easily divide with a small load. However, deepening the groove is costly due to an increase in process time, and the semiconductor wafer constituent material in the groove portion may scatter and contaminate the surface of the semiconductor element. In addition, increasing the width of the groove reduces the number of chips obtained from a single wafer.
Therefore, in order to divide a semiconductor chip at a low cost without surface contamination, a method for dividing the semiconductor chip with a shallow dividing groove and having a narrow width can be easily obtained.

  The objective of this invention is providing the manufacturing method of the semiconductor chip which can manufacture the semiconductor chip used for face down (FD) mounting more easily.

A semiconductor chip manufacturing method to which the present invention is applied includes a semiconductor element forming step of forming a semiconductor wafer having a semiconductor element formed on a substrate, and an electrode provided on the semiconductor element, the most A protruding electrode forming process for forming a protruding electrode on the semiconductor wafer on the semiconductor wafer rather than a distant surface, and weaker than other regions in the substrate of the semiconductor wafer along the planned dividing line provided on the semiconductor wafer A weak region forming process for forming a region, and a blade is pressed against the substrate of the semiconductor wafer along the planned dividing line from the side opposite to the side on which the protruding electrode of the semiconductor wafer is formed, so that the semiconductor wafer is divided into a plurality of semiconductor chips. And a dividing step of dividing into two.
The fragile region formed in the fragile region forming step of such a semiconductor chip manufacturing method can be characterized in that it is formed by a laser beam condensed inside the substrate. In addition, the fragile region formed in the fragile region forming step may be formed in the substrate along the planned division line of the substrate at a plurality of distances from one surface of the substrate. .
Furthermore, the protruding electrode formed in the protruding electrode forming step of the semiconductor chip manufacturing method may be made of gold (Au) or an alloy containing gold (Au).
Furthermore, the substrate may be made of sapphire.
The semiconductor element of the semiconductor chip manufactured by such a semiconductor chip manufacturing method can be characterized by being a light emitting element or a light receiving element.
From another point of view, the method for dividing a semiconductor wafer to which the present invention is applied includes a semiconductor element forming step of forming a semiconductor wafer having a semiconductor element formed on a substrate, and an electrode provided in the semiconductor element. A protruding electrode forming step for forming a protruding electrode on the semiconductor wafer, the protruding electrode having a surface protruding beyond the surface farthest from the substrate of the semiconductor element, and the semiconductor wafer substrate along a predetermined division line provided on the semiconductor wafer From the side opposite to the side where the protruding electrode of the semiconductor wafer is formed, the blade is pressed against the substrate of the semiconductor wafer along the planned dividing line from the side where the protruding electrode is formed on the semiconductor wafer. A dividing step of dividing the semiconductor wafer into a plurality of semiconductor chips.

  According to the present invention, a semiconductor chip used for face-down (FD) mounting can be manufactured more easily. The present invention also provides a method for dividing a semiconductor wafer with little damage to the semiconductor layer.

It is a figure which shows an example of the cross-sectional schematic diagram of the light emitting chip to which this Embodiment is applied. It is a figure which shows an example of the plane schematic diagram which looked at the light emitting chip from the direction of arrow II of FIG. It is a figure which shows an example of the cross-sectional schematic diagram of the laminated semiconductor layer which comprises a light emitting chip. It is an example of the flowchart explaining the method of manufacturing a light emitting chip. It is a figure explaining a semiconductor element formation process and a protruding electrode formation process. It is the top view of the wafer seen from the side in which the 1st protrusion electrode and the 2nd protrusion electrode were formed. It is a figure explaining a weak region formation process and a division process. It is a figure which shows an example of a structure of the light-emitting device which mounted the light-emitting chip shown in FIG. 1 on the wiring board. It is a figure which shows an example of the cross-sectional schematic diagram of the light emitting chip to which this Embodiment is applied. It is a figure which shows an example of the plane schematic diagram which looked at the light emitting chip from the direction of arrow X of FIG. It is the figure which showed the height of the protrusion electrode in an Example and a comparative example, the shape of a light emitting chip, LED characteristic, and IR defect rate (%).

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In the attached drawings, wafers, chips, and the like are schematically shown, and the scale is not accurate.
In this specification, a semiconductor wafer having a plurality of semiconductor elements on a substrate is referred to as a semiconductor wafer (sometimes simply referred to as a wafer), and a semiconductor chip is obtained by dividing the wafer so that each has a semiconductor element. (It may be described simply as a chip.). When the semiconductor element of a semiconductor chip is a light emitting element, it may be described as a light emitting chip in the specification. When the semiconductor element of the semiconductor chip is a light receiving element, it may be described as a light receiving chip in the specification.
Examples of the semiconductor element include a light emitting element, a light receiving element, an integrated circuit, a MEMS (Micro Electro Mechanical Systems) in which a mechanical system is incorporated together with an electric / electronic circuit. Here, a light-emitting element is described as an example of a semiconductor element. That is, the semiconductor chip is described as a light emitting chip.

[Light emitting chip 1]
FIG. 1 is a diagram illustrating an example of a schematic cross-sectional view of a light-emitting chip 1 to which the exemplary embodiment is applied. FIG. 2 is a diagram showing an example of a schematic plan view of the light emitting chip 1 viewed from the direction of the arrow II in FIG. 1 is a cross-sectional view taken along the line II of FIG.

First, the cross-sectional structure of the light emitting chip 1 will be described.
As shown in FIG. 1, the light emitting chip 1 includes a substrate 10, an intermediate layer 120 stacked on the surface 10 a of the substrate 10, and a base layer 130 stacked on the intermediate layer 120. The light emitting chip 1 includes an n-type semiconductor layer 140 stacked on the base layer 130, a light-emitting layer 150 stacked on the n-type semiconductor layer 140, and a p-type semiconductor layer 160 stacked on the light-emitting layer 150. And. In the following description, the n-type semiconductor layer 140, the light emitting layer 150, and the p-type semiconductor layer 160 are collectively referred to as the laminated semiconductor layer 100 as necessary. In addition, the intermediate layer 120 and the base layer 130 may be referred to as the laminated semiconductor layer 100.

  The light-emitting chip 1 includes the first electrode 170 formed on the upper surface 160c of the p-type semiconductor layer 160 (the surface opposite to the substrate 10 of the p-type semiconductor layer 160), the stacked p-type semiconductor layer 160, and the light emission. And the second electrode 180 formed on the semiconductor layer exposed surface 140c of the n-type semiconductor layer 140 exposed by cutting out part of the layer 150 and the n-type semiconductor layer 140.

  Furthermore, the light emitting chip 1 includes the first electrode 170 and the second electrode 180, the region where the first electrode 170 on the upper surface 160c of the p-type semiconductor layer 160 is not provided, and the second electrode 180 on the exposed surface 140c of the semiconductor layer. A protective layer 190 is provided so as to cover a region that is not provided and a side surface of the laminated semiconductor layer 100 exposed by providing the semiconductor layer exposed surface 140c. However, the protective layer 190 is formed on the upper surface 170c of the first electrode 170 (the surface of the first electrode 170 on the side opposite to the substrate 10), the region where the first protruding electrode 210 described later is formed, and the upper surface of the second electrode 180. In 180c (the surface of the second electrode 180 opposite to the substrate 10), the first electrode 170 and the second electrode 180 are laminated so as to cover a region where a second protruding electrode 220 described later is provided.

  Furthermore, the light emitting chip 1 includes a first protruding electrode 210 provided on the upper surface 170 c of the first electrode 170 and a second protruding electrode 220 provided on the upper surface 180 c of the second electrode 180.

In the light-emitting chip 1, the first protruding electrode 210 is a positive electrode and the second protruding electrode 220 is a negative electrode, and the stacked semiconductor layer 100 (more specifically, the p-type semiconductor layer 160, the light-emitting layer 150, and the n-type semiconductor layer is interposed therebetween. 140), the light emitting layer 150 emits light.
Here, it is assumed that the light emitting element 20 includes the intermediate layer 120, the base layer 130, the stacked semiconductor layer 100, the first electrode 170, and the second electrode 180. That is, the light emitting chip 1 includes the substrate 10, the light emitting element 20, the first protruding electrode 210, and the second protruding electrode 220.

Next, the planar shape of the light emitting chip 1 will be described.
As shown in FIG. 2, the planar shape of the light emitting chip 1 is a square of 350 μm × 350 μm, for example. The planar shape of the light emitting chip 1 is not limited to a square, but may be other shapes such as a rectangle.

As shown in FIG. 2, the semiconductor layer exposed surface 140 c is formed so as to go around the periphery of the light emitting chip 1. In addition, when the light emitting chip 1 is viewed from the direction of the arrow II in FIG. 1, the semiconductor layer exposed surface 140 c is provided so as to spread from the periphery toward the inside at one of the four corners of the square. Then, the second electrode 180 is provided on the semiconductor layer exposed surface 140c that is provided to expand.
On the other hand, the first electrode 170 is provided on the upper surface 160 c of the p-type semiconductor layer 160. As shown in FIG. 1, since the light emitting chip 1 emits light from the light emitting layer 150, the first electrode 170 has a larger amount of light as its area increases. Therefore, the first electrode 170 is configured to occupy the surface (planar shape) of the light emitting chip 1.
In addition, the shape and arrangement of the first electrode 170 and the second electrode 180 are not limited to those shown in FIG. 2, but may be other shapes and arrangements.

  Furthermore, a first protruding electrode 210 is provided on the first electrode 170, and a second protruding electrode 220 is provided on the second electrode 180. In FIG. 2, the cross-sectional shape of the first protruding electrode 210 is a shape having an arc-shaped portion in which the outline of the outer peripheral portion of the first electrode 170 is substantially reduced, and the second protruding electrode 220 is circular. However, the cross-sectional shape may be elliptical, square, rectangular or other shapes.

Next, each component of the light emitting chip 1 will be described in more detail.
<Substrate 10>
The substrate 10 is not particularly limited as long as the group III nitride semiconductor crystal is epitaxially grown on the surface, and various substrates can be selected and used. However, since the light-emitting chip 1 according to the present embodiment is mounted face-down (FD) so as to extract light from the back surface 10b side of the substrate 10 as will be described later, the light-emitting chip 150 transmits light emitted from the light-emitting layer 150. It is preferable to have a light property. Therefore, for example, sapphire, zinc oxide, magnesium oxide, zirconium oxide, magnesium aluminum oxide, gallium oxide, indium oxide, lithium gallium oxide, lithium aluminum oxide, neodymium gallium oxide, lanthanum strontium aluminum tantalum, strontium titanium oxide, titanium oxide, etc. A substrate 10 made of can be used.
Among the above materials, it is particularly preferable to use sapphire having the C-plane as the main surface as the substrate 10. When sapphire is used as the substrate 10, an intermediate layer 120 (buffer layer) is preferably formed on the C surface of sapphire.
Furthermore, the back surface 10b of the substrate 10 is preferably subjected to a surface roughening process in order to suppress warpage of the substrate 10.

<Intermediate layer 120>
The intermediate layer 120 laminated on the surface 10a of the substrate 10 is preferably made of polycrystalline Al _x Ga _1-x N (0 ≦ x ≦ 1), and single crystal Al _x Ga _1-x N (0 ≦ x ≦ 1) is more preferable.
As described above, the intermediate layer 120 can be, for example, made of polycrystalline Al _x Ga _1-x N (0 ≦ x ≦ 1) and having a thickness of 0.01 to 0.5 μm. If the thickness of the intermediate layer 120 is less than 0.01 μm, the effect of alleviating the difference in lattice constant between the substrate 10 and the base layer 130 may not be sufficiently obtained by the intermediate layer 120. In addition, when the thickness of the intermediate layer 120 exceeds 0.5 μm, the film formation time of the intermediate layer 120 becomes long and the productivity may be lowered although the function as the intermediate layer 120 is not changed. is there.

  The intermediate layer 120 alleviates the difference in lattice constant between the substrate 10 and the base layer 130, and in particular, when the substrate 10 is made of sapphire having a C plane as a main surface, the (0001) plane (C plane) of the substrate 10. ) To facilitate the formation of a c-axis oriented single crystal layer on top. Therefore, when the single crystal base layer 130 is stacked on the intermediate layer 120, the base layer 130 with higher crystallinity can be stacked. In the present invention, it is preferable to form the intermediate layer 120, but it is not always necessary.

  The intermediate layer 120 may have a hexagonal crystal structure made of a group III nitride semiconductor. Further, the group III nitride semiconductor crystal forming the intermediate layer 120 may have a single crystal structure, and preferably has a single crystal structure. By controlling the growth conditions, the group III nitride semiconductor crystal grows not only in the upward direction but also in the in-plane direction to form a single crystal structure. Therefore, by controlling the film forming conditions of the intermediate layer 120, the intermediate layer 120 made of a crystal of a group III nitride semiconductor having a single crystal structure can be obtained. When the intermediate layer 120 having such a single crystal structure is formed on the substrate 10, the buffer function of the intermediate layer 120 works effectively, so that the group III nitride semiconductor formed thereon has a good orientation. The crystal film has the property and crystallinity.

  Furthermore, the group III nitride semiconductor crystals forming the intermediate layer 120 can be formed into columnar crystals (polycrystals) having a texture based on hexagonal columns by controlling the film forming conditions. In addition, the columnar crystal consisting of the texture here is a crystal that is separated by forming a crystal grain boundary between adjacent crystal grains, and is itself a columnar shape as a longitudinal sectional shape. Say.

<Underlayer 130>
As the underlayer 130, Al _x Ga _y In _z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) can be used, but Al _x Ga _1-x N It is preferable to use (0 ≦ x <1) because the base layer 130 with good crystallinity can be formed.
The film thickness of the underlayer 130 is preferably 0.1 μm or more, more preferably 0.5 μm or more, and most preferably 1 μm or more. An Al _x Ga _1-x N layer with good crystallinity is more easily obtained when the thickness is increased.
In order to improve the crystallinity of the underlayer 130, it is desirable that the underlayer 130 is not doped with impurities. However, when p-type or n-type conductivity is required, acceptor impurities or donor impurities can be added.

<Laminated semiconductor layer 100>
The laminated semiconductor layer 100 is a layer made of a group III nitride semiconductor, and as shown in FIG. 1, the n-type semiconductor layer 140, the light-emitting layer 150, and the p-type semiconductor layer 160 are formed on the base layer 130. They are stacked in this order.
Here, the n-type semiconductor layer 140 conducts electricity in the first conductivity type using electrons as carriers, and the p-type semiconductor layer 160 serves as the second conductivity type that uses holes as carriers. Conducts electricity.

FIG. 3 is a diagram showing an example of a schematic cross-sectional view of the laminated semiconductor layer 100 constituting the light emitting chip 1. The n-type semiconductor layer 140 in FIG. 1 includes an n-contact layer 140a and an n-cladding layer 140b. The light emitting layer 150 has a multiple quantum well structure in which barrier layers 150a and well layers 150b are alternately stacked. The p-type semiconductor layer 160 includes a p-cladding layer 160a and a p-contact layer 160b.
Note that although the stacked semiconductor layer 100 can be formed with good crystallinity when formed by the MOCVD method, the stacked semiconductor layer 100 having crystallinity superior to that of the MOCVD method can be obtained by optimizing the conditions also by the sputtering method. Can be formed.
Hereinafter, the layers constituting the laminated semiconductor layer 100 will be described.

(N-type semiconductor layer 140)
The n-type semiconductor layer 140 includes an n-contact layer 140a and an n-cladding layer 140b.
The n contact layer 140 a is a layer for providing the second electrode 180. The n contact layer 140a is preferably composed of an Al _x Ga _1-x N layer (0 ≦ x <1, preferably 0 ≦ x ≦ 0.5, more preferably 0 ≦ x ≦ 0.1). .

The n-contact layer 140a is preferably doped with an n-type impurity, and the n-type impurity is preferably 1 × 10 ¹⁷ to 1 × 10 ²⁰ / cm ³ , preferably 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm. ³ is preferable in that a good ohmic contact with the second electrode 180 can be maintained. Although it does not specifically limit as an n-type impurity, For example, Si, Ge, Sn, etc. are mentioned, Preferably Si and Ge are mentioned.

  The thickness of the n contact layer 140a is preferably 0.5 to 5 μm, and more preferably set to a range of 1 to 3 μm. When the thickness of the n-contact layer 140a is in the above range, the crystallinity of the semiconductor is maintained well.

An n-clad layer 140b is preferably provided between the n-contact layer 140a and the light emitting layer 150. The n-cladding layer 140b is a layer that injects carriers into the light emitting layer 150 and confines carriers. The n-clad layer 140b can be formed of AlGaN, GaN, GaInN, or the like. Alternatively, a heterojunction of these structures or a superlattice structure in which a plurality of layers are stacked may be used. In the case where the n-cladding layer 140b is formed of GaInN, it is desirable to make it larger than the band gap energy of GaInN of the light emitting layer 150. In the present specification, the composition ratio of each element may be omitted and described as AlGaN or GaInN.
The thickness of the n-clad layer 140b is not particularly limited, but is preferably 5 to 500 nm, and more preferably 5 to 100 nm. The n-type impurity concentration of the n-clad layer 140b is preferably 1 × 10 ¹⁷ to 1 × 10 ²⁰ / cm ³ , more preferably 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ³ . An impurity concentration within this range is preferable in terms of maintaining good crystallinity and reducing the operating voltage of the device.

When the n-cladding layer 140b is a layer including a superlattice structure, a detailed illustration is omitted, but an n-side first layer made of a group III nitride semiconductor having a thickness of 10 nm or less; It may include a structure in which an n-side second layer made of a group III nitride semiconductor having a composition different from that of the n-side first layer and having a film thickness of 10 nm or less is stacked.
Further, the n-cladding layer 140b may include a structure in which n-side first layers and n-side second layers are alternately and repeatedly stacked. The GaInN and GaN alternate structures or GaInN having different compositions. It is preferable that they have an alternating structure.

(Light emitting layer 150)
As the light emitting layer 150 stacked on the n-type semiconductor layer 140, a single quantum well structure, a multiple quantum well structure, or the like can be employed. In the present embodiment, as shown in FIG. 3, the light emitting layer 150 has a multiple quantum well structure in which barrier layers 150a and well layers 150b are alternately stacked. The light emitting layer 150 is a barrier layer 150a on the side in contact with the n-cladding layer 140b and the side in contact with the p-cladding layer 160a.

Here, the well layer _150b, III nitride semiconductor layer made of _{Ga 1-y In y N (} 0 <y <0.4) is usually used. The film thickness of the well layer 150b can be set to a film thickness that provides a quantum effect, for example, 1 to 10 nm, and preferably 2 to 6 nm, from the viewpoint of light emission output.
In the case of the light emitting layer 150 having a multiple quantum well structure, the Ga _1-y In _y N is used as the well layer 150b, and Al _z Ga _1-z N (0 ≦ z <0), which has a larger band gap energy than the well layer 150b. .3) is defined as a barrier layer 150a. The well layer 150b and the barrier layer 150a may or may not be doped with impurities by design.
In the present embodiment, the light emitting layer 150 outputs blue light (emission wavelength λ = about 400 to 465 nm).

(P-type semiconductor layer 160)
As shown in FIG. 3, the p-type semiconductor layer 160 normally includes a p-cladding layer 160a and a p-contact layer 160b. However, the p contact layer 160b can also serve as the p clad layer 160a.

The p-cladding layer 160a is a layer that performs confinement of carriers in the light emitting layer 150 and injection of carriers. The p-cladding layer 160a is not particularly limited as long as it has a composition larger than the band gap energy of the light-emitting layer 150 and can confine carriers in the light-emitting layer 150, but is preferably Al _x Ga _1-x N. (0 <x ≦ 0.4).

It is preferable that the p-cladding layer 160a is made of such AlGaN from the viewpoint of confining carriers in the light-emitting layer 150. The film thickness of the p-cladding layer 160a is not particularly limited, but is preferably 1 to 400 nm, more preferably 5 to 100 nm.
The p-type impurity concentration in the p-cladding layer 160a is preferably 1 × 10 ¹⁸ to 1 × 10 ²¹ / cm ³ , more preferably 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ³ . When the p-type impurity concentration is in the above range, a good p-type crystal can be obtained without reducing the crystallinity.
Further, the p-cladding layer 160a may have a superlattice structure similar to the above-described n-cladding layer 140b. In this case, AlGaN and GaN having different structures or different compositions of AlGaN and other AlGaN having different composition ratios. It is preferable that this is an alternate structure.

The p contact layer 160 b is a layer for providing the first electrode 170. The p contact layer 160b is preferably Al _x Ga _1-x N (0 ≦ x ≦ 0.4). When the Al composition is in the above range, it is preferable in that good crystallinity and good ohmic contact with the first electrode 170 can be maintained.
When p-type impurities are contained at a concentration of 1 × 10 ¹⁸ to 1 × 10 ²¹ / cm ³ , preferably 5 × 10 ^{19 to} 5 × 10 ²⁰ / cm ³ , good ohmic contact can be maintained, cracking It is preferable in terms of prevention of generation and maintaining good crystallinity. Although it does not specifically limit as a p-type impurity, For example, Preferably Mg is mentioned.
The thickness of the p contact layer 160b is not particularly limited, but is preferably 0.01 to 0.5 μm, and more preferably 0.05 to 0.2 μm. When the film thickness of the p-contact layer 160b is within this range, it is preferable in terms of light emission output.

<First electrode 170>
Next, the configuration of the first electrode 170 will be described with reference to FIG.
The first electrode 170 is preferably a first conductive layer 171 stacked on the upper surface 160 c of the p-type semiconductor layer 160, a metal reflective layer 172 stacked on the first conductive layer 171, and the metal reflective layer 172. A first bonding layer 174 stacked on the first bonding layer 174, and a first adhesion layer 175 stacked on the first bonding layer 174 except for a portion where a first protruding electrode 210 described later is provided on the first bonding layer 174. I have.
A first diffusion prevention layer 173 may be provided between the metal reflection layer 172 and the first bonding layer 174. FIG. 1 shows a case where the first diffusion prevention layer 173 is provided.
Hereinafter, each layer constituting the first electrode 170 will be described.

(First conductive layer 171)
It is preferable that the first conductive layer 171 is stacked on the upper surface 160 c of the p-type semiconductor layer 160. As shown in FIGS. 1 and 2, the first conductive layer 171 is provided so as to cover almost the entire upper surface 160 c of the p-type semiconductor layer 160 except for the peripheral portion of the upper surface 160 c of the p-type semiconductor layer 160. Yes. In FIG. 2, the first conductive layer 171 is formed in the range described as the first electrode 170.
The central portion of the first conductive layer 171 has a certain film thickness. The surface (surface) opposite to the surface in contact with the p-type semiconductor layer 160 at the center of the first conductive layer 171 is flat and substantially parallel to the upper surface 160 c of the p-type semiconductor layer 160. On the other hand, the end portion of the first conductive layer 171 is inclined with respect to the upper surface 160c of the p-type semiconductor layer 160 so that the film thickness gradually decreases as approaching the end. However, the first conductive layer 171 is not limited to the above shape, and may be a lattice shape or a tree shape. Further, the cross-sectional shape (cross-sectional shape) of the first conductive layer 171 may be a rectangular shape.

The first conductive layer 171 preferably has an ohmic contact with the p-type semiconductor layer 160 and has a low contact resistance with the p-type semiconductor layer 160. In the light emitting chip 1, the light emitted from the light emitting layer 150 and directed to the first electrode 170 side is reflected by the metal reflective layer 172 and extracted from the back surface 10 b of the substrate 10. It is preferable to use a material excellent in translucency. Furthermore, in order to uniformly diffuse the current over the entire surface of the p-type semiconductor layer 160, it is preferable that the first conductive layer 171 has excellent conductivity and has a small resistance distribution.
In the present embodiment, the thickness of the central portion of the first conductive layer 171 is set to 5 nm, for example. Note that the thickness of the first conductive layer 171 can be selected from a range of 2 to 500 nm. Here, if the thickness of the first conductive layer 171 is less than 2 nm, it may be difficult to make ohmic contact with the p-type semiconductor layer 160. If the thickness of the first conductive layer 171 is greater than 500 nm, In some cases, the light emitted from the light emitting layer 150 and transmitted to the first electrode 170 side and the light reflected from the metal reflective layer 172 and transmitted to the substrate 10 side are not preferable.

An example of the first conductive layer 171 is a transparent conductive layer. For example, in this embodiment, as the first conductive layer 171, an oxide conductive material that has high translucency with respect to the wavelength of light emitted from the light-emitting layer 150 is used. In particular, a part of the oxide containing In is preferable in that both translucency and conductivity are excellent as compared with other transparent conductive materials. As the conductive oxide containing In, for example, ITO (indium tin oxide (In ₂ O ₃ —SnO ₂ )), IZO (indium zinc oxide (In ₂ O ₃ —ZnO)), IGO (indium gallium oxide (In _{2 O 3 -Ga 2 O 3)} ), ICO ( indium cerium oxide _{(In 2 O 3 -CeO 2)} ) , and the like. For example, a dopant such as fluorine may be added thereto. Further, for example, an oxide not containing In, for example, a conductive material such as SnO ₂ , ZnO ₂ , or TiO ₂ doped with carriers may be used.
The first conductive layer 171 can be formed by providing these materials with a film forming unit described later. In addition, after the first conductive layer 171 is formed, heat treatment for the purpose of making the first conductive layer 171 transparent and reducing resistance may be performed.

In the present embodiment, a crystallized structure may be used for the first conductive layer 171, and in particular, a light-transmitting material including an In ₂ O ₃ crystal having a hexagonal crystal structure or a bixbite structure (for example, , ITO, IZO, etc.) can be preferably used.
For example, when IZO containing hexagonal structure In ₂ O ₃ crystal is used as the first conductive layer 171, it can be processed into a specific shape using an amorphous IZO film having excellent etching properties, and then heat treatment, etc. By transferring from an amorphous state to a structure including a crystal, the electrode can be processed into a light-transmitting electrode better than an amorphous IZO film.

In addition, as the IZO film used for the first conductive layer 171, it is preferable to use a composition having the lowest specific resistance.
For example, the ZnO concentration in the IZO film is preferably 1 to 20% by mass, more preferably 5 to 15% by mass, and particularly preferably 10% by mass.

Heat treatment of the IZO film used for the first conductive layer 171 is desirably performed in an atmosphere containing no O _2, as the atmosphere containing no O _2, or an inert gas atmosphere such as N ₂ atmosphere, or such as N ₂ A mixed gas atmosphere of an inert gas and H ₂ can be given, and it is preferable to use an N ₂ atmosphere or a mixed gas atmosphere of N ₂ and H ₂ . Note that when the heat treatment of the IZO film is performed in an N ₂ atmosphere or a mixed gas atmosphere of N ₂ and H ₂ , for example, the IZO film is crystallized into a film containing In ₂ O ₃ crystals having a hexagonal structure, It is possible to effectively reduce the sheet resistance of the IZO film.
Further, the heat treatment temperature of the IZO film is preferably 500 to 1000 ° C. When the heat treatment is performed at a temperature lower than 500 ° C., there is a possibility that the IZO film cannot be sufficiently crystallized, and the translucency of the IZO film may not be sufficiently high. When heat treatment is performed at a temperature higher than 1000 ° C., the IZO film is crystallized, but the translucency of the IZO film may not be sufficiently high. In addition, when heat treatment is performed at a temperature exceeding 1000 ° C., the laminated semiconductor layer 100 under the IZO film may be deteriorated.

  In particular, as described above, an IZO film crystallized by heat treatment is effective in this embodiment because it has better adhesion to the p-type semiconductor layer 160 than an amorphous IZO film. In addition, an IZO film crystallized by heat treatment has a lower resistance value than an amorphous IZO film, and thus is preferable in that the forward voltage Vf of the light emitting element 20 in the light emitting chip 1 can be reduced.

(Metal reflective layer 172)
As shown in FIG. 1, a metal reflective layer 172 is stacked on the first conductive layer 171.
The metal reflection layer 172 is formed so as to cover the entire surface of the first conductive layer 171 when viewed in plan. And the center part of the metal reflective layer 172 has a fixed film thickness. The surface opposite to the surface in contact with the first conductive layer 171 at the center of the metal reflective layer 172 is substantially flat. On the other hand, the end portion of the metal reflection layer 172 is provided to be inclined with respect to the upper surface 160c of the p-type semiconductor layer 160 so that the film thickness gradually decreases as the end is approached.

The metal reflection layer 172 is made of, for example, Ag (silver). The reason why Ag is used as the metal reflection layer 172 is that it has high reflectivity with respect to light in a blue to green region emitted from the light emitting layer 150. Further, as will be described later, the metal reflection layer 172 also has a function of supplying power to the p-type semiconductor layer 160 through the first conductive layer 171. Therefore, the metal reflective layer 172 needs to have a low resistance value and a low contact resistance with the first conductive layer 171.
The thickness of the metal reflection layer 172 in the present embodiment is set to 150 nm, for example. The thickness of the metal reflective layer 172 can be preferably selected from a range of 50 nm or more. Here, when the thickness of the metal reflective layer 172 is less than 50 nm, it may be undesirable in that the reflectivity of light emitted from the light emitting layer 150 is lowered.
In this embodiment, single Ag is used as the metal reflection layer 172, but an alloy containing Ag may be used. Alternatively, a highly reflective platinum group such as Al (aluminum), Al alloy, Rh, Pt, Ir, or an alloy thereof may be used.

(First diffusion prevention layer 173)
As shown in FIG. 1, a first diffusion preventing layer 173 is preferably laminated on the metal reflective layer 172. The first diffusion preventing layer 173 is provided in order to suppress the metal (Ag in this embodiment) constituting the metal reflective layer 172 in a contact state from diffusing into the first bonding layer 174.
The first diffusion preventing layer 173 is provided so as to cover the entire surface of the metal reflective layer 172 when viewed in plan. And the center part of the 1st diffusion prevention layer 173 has a fixed film thickness. The surface opposite to the surface in contact with the metal reflection layer 172 at the center of the first diffusion prevention layer 173 is substantially flat. On the other hand, the thickness of the end portion of the first diffusion prevention layer 173 gradually decreases as the end approaches the end, so that the surface of the end portion of the first diffusion prevention layer 173 is compared with the upper surface 160 c of the p-type semiconductor layer 160. Inclined. Further, the first diffusion prevention layer 173 is configured not to directly contact the p-type semiconductor layer 160.

It is preferable that the first diffusion preventing layer 173 has an ohmic contact with the metal reflective layer 172 and has a low contact resistance with the metal reflective layer 172. However, unlike the first conductive layer 171, the first diffusion prevention layer 173 does not need to have a light-transmitting property because the first diffusion prevention layer 173 does not require a function of transmitting light emitted from the light emitting layer 150.
Further, the first diffusion prevention layer 173 has a function of supplying power to the p-type semiconductor layer 160 through the metal reflection layer 172 and the first conductive layer 171, and thus has excellent conductivity, and It is preferable that the resistance distribution is small.

  In the present embodiment, the thickness of the first diffusion prevention layer 173 is set to 50 nm, for example. If the thickness of the first diffusion preventing layer 173 is 50 nm or more, it is preferable in that the diffusion of Ag constituting the metal reflective layer 172 is easily suppressed. On the other hand, if the thickness of the first diffusion preventing layer 173 is less than 50 nm, it is not preferable from the viewpoint of preventing diffusion of Ag into the first bonding layer 174 formed on the first diffusion preventing layer 173. Further, if the thickness of the first diffusion preventing layer 173 is thicker than 5 μm, it is not preferable in terms of cost increase.

  In the present embodiment, Ta (tantalum) is used as the first diffusion prevention layer 173.

As the first diffusion preventing layer 173, Ta (tantalum), IZO, ITO, IGO, ICO, or the like can be used. Further, for example, a conductive material such as SnO ₂ , ZnO ₂ , or TiO ₂ doped with carriers may be used. Further, a metal material such as Ni (nickel) or Ti (titanium) may be used.

(First bonding layer 174)
As shown in FIG. 1, a first bonding layer 174 is stacked on the first diffusion prevention layer 173. The first bonding layer 174 is provided so as to cover the entire surface of the first diffusion prevention layer 173 when viewed in plan. The central portion of the first bonding layer 174 has a certain film thickness. The surface opposite to the surface in contact with the first diffusion prevention layer 173 at the center of the first bonding layer 174 (the upper surface 170c of the first electrode 170) is substantially flat. On the other hand, the end portion of the first bonding layer 174 gradually decreases in thickness as it approaches the end, so that the surface of the end portion of the first bonding layer 174 is inclined with respect to the upper surface 160 c of the p-type semiconductor layer 160. ing.

The first bonding layer 174 includes at least one layer. In this case, Au (gold) is generally used for the layer (the outermost layer) provided farthest from the first diffusion preventing layer 173. In this embodiment, a single layer film of Au (gold) is used as the first bonding layer 174. For example, a Ni (nickel) layer as a first layer provided in contact with the first diffusion prevention layer 173, A structure having a Pt (platinum) layer as a second layer provided on the Ni layer and an Au (gold) layer as a third layer (outermost layer) provided on the second Pt layer is adopted. May be.
In the present embodiment, the entire thickness of the first bonding layer 174 is set to 300 nm, for example. Any thickness of the first bonding layer 174 can be used without limitation as long as the first protruding electrode 210 described later can be provided. The total thickness of the first bonding layer 174 is preferably 50 to 8000 nm.

  In the case where the first bonding layer 174 is composed of a plurality of metal layers, the material constituting the first layer in contact with the first diffusion prevention layer 173 includes Ta (tantalum) in addition to the above-described Ni (nickel), Ti (titanium), NiTi (nickel titanium) alloy, and nitrides thereof can be used.

(First adhesion layer 175)
As shown in FIG. 1, a first adhesion layer 175 is preferably laminated on the first bonding layer 174. The first adhesion layer 175 is provided to improve the physical adhesion between the first bonding layer 174 made of Au (gold) and the protective layer 190.
The first adhesion layer 175 is provided so as to cover the surface of the first bonding layer 174 except for a portion where the first protruding electrode 210 is provided on the first bonding layer 174 when viewed in plan. Note that the first adhesion layer 175 is provided so that the end thereof is in contact with the upper surface 160 c of the p-type semiconductor layer 160.

  In the present embodiment, the first adhesion layer 175 is made of Ta (tantalum). However, as the material of the first adhesion layer 175, for example, Ti (titanium), Ni (nickel), or W (tungsten) can be used in addition to Ta (tantalum). In the present embodiment, the thickness of the first adhesion layer 175 is set to 10 nm, for example. The thickness of the first adhesion layer 175 is preferably 5 to 400 nm, more preferably 5 to 300 nm, and even more preferably 7 to 100 nm. If the thickness of the first adhesion layer 175 is less than 5 nm, the adhesion between the first bonding layer 174 and the protective layer 190 is not preferable.

<Second electrode 180>
Next, the configuration of the second electrode 180 will be described with reference to FIG.
The second electrode 180 is preferably a second conductive layer 181 stacked on the semiconductor layer exposed surface 140c of the n-type semiconductor layer 140, a second bonding layer 183 stacked on the second conductive layer 181; A second adhesion layer 184 is provided on the second bonding layer 183 except for a portion where a second protruding electrode 220 described later is provided on the second bonding layer 183.
Note that a second diffusion prevention layer 182 may be provided between the second conductive layer 181 and the second bonding layer 183. FIG. 1 shows a case where the second diffusion preventing layer 182 is provided as a preferred example.

(Second conductive layer 181)
As shown in FIG. 1, a second conductive layer 181 is preferably stacked on the n-type semiconductor layer 140.
The second conductive layer 181 has a circular shape (planar shape) when viewed in plan (in the range of the second electrode 180 in FIG. 2). And the center part of the 2nd conductive layer 181 has a fixed film thickness. The surface (surface) opposite to the surface in contact with the semiconductor layer exposed surface 140c at the center of the second conductive layer 181 is substantially flat with respect to the semiconductor layer exposed surface 140c. On the other hand, the end portion of the second conductive layer 181 is inclined with respect to the semiconductor layer exposed surface 140c of the n-type semiconductor layer 140 by gradually decreasing the film thickness as approaching the end.
However, the planar shape of the second conductive layer 181 is not limited to the above shape, and may be a lattice shape or a tree shape. The cross-sectional shape of the second conductive layer 181 may be a rectangular shape.

The second conductive layer 181 preferably has an ohmic contact with the n-type semiconductor layer 140 and a low contact resistance with the n-type semiconductor layer 140.
In this embodiment, Al (aluminum) is used for the second conductive layer 181. Al (aluminum) constituting the second conductive layer 181 corresponds to the light in the blue to green region emitted from the light emitting layer 150, as is the case with Ag (silver) constituting the metal reflective layer 172 of the first electrode 170. It has high reflectivity and functions as a metal reflection layer.
The thickness of the second conductive layer 181 in the present embodiment is set to 150 nm, for example. The thickness of the second conductive layer 181 can be selected from the range of 50 to 1000 nm. Here, if the thickness of the second conductive layer 181 is less than 50 nm, the light extraction efficiency decreases due to the transmission of the light. On the other hand, if the thickness of the second conductive layer 181 is greater than 1000 nm, the film formation time becomes long, and the resist used to form the second conductive layer 181 is hardened by heating, and a resist residue is likely to be generated. In some cases, it is not preferable in terms of reliability.

  Further, the second conductive layer 181 may be made of Ag (silver) similarly to the metal reflective layer 172. At this time, if the thickness of the second conductive layer 181 and the metal reflective layer 172 is the same, the second conductive layer 181 and the metal reflective layer 172 can be formed at the same time, as will be described later.

(Second diffusion prevention layer 182)
As shown in FIG. 1, the second diffusion prevention layer 182 is preferably laminated in contact with the second conductive layer 181. The second diffusion preventing layer 182 is provided in order to prevent the metal (Al in this embodiment) constituting the second conductive layer 181 from diffusing into the second bonding layer 183.
The second diffusion prevention layer 182 is provided so as to cover the entire surface of the second conductive layer 181 when viewed in plan. And the center part of the 2nd diffusion prevention layer 182 has a fixed film thickness. The surface (surface) opposite to the surface in contact with the second conductive layer 181 at the center of the second diffusion preventing layer 182 is substantially flat. On the other hand, the end portion of the second diffusion prevention layer 182 gradually decreases in thickness as it approaches the end, so that the surface of the end portion of the second diffusion prevention layer 182 is the semiconductor layer exposed surface of the n-type semiconductor layer 140. It is inclined with respect to 140c. Further, the second diffusion preventing layer 182 is configured not to directly contact the n-type semiconductor layer 140.

  The second diffusion prevention layer 182 is preferably in ohmic contact with the second conductive layer 181 and has a low contact resistance with the second conductive layer 181. In addition, since the second diffusion prevention layer 182 has a function of supplying power to the n-type semiconductor layer 140 through the second conductive layer 181, it has excellent conductivity and has a small resistance distribution. Is preferred.

In the present embodiment, Pt (platinum) is used as the second diffusion preventing layer 182.
The second diffusion prevention layer 182 may be made of Rh (rhodium), W (tungsten), etc. in addition to Pt.
And the thickness of the 2nd diffusion prevention layer 182 in this embodiment is set as 50 nm, for example. If the thickness of the second diffusion preventing layer 182 is 50 nm or more, it is preferable in that diffusion of Al constituting the second conductive layer 181 to the second bonding layer 183 is easily suppressed. On the other hand, if the thickness of the second diffusion preventing layer 182 is less than 50 nm, it is not preferable from the viewpoint of preventing diffusion of Al constituting the second conductive layer 181 into the second bonding layer 183. Further, if the thickness of the second diffusion prevention layer 182 is thicker than 5000 nm, it is not preferable from the viewpoint of increasing the cost of the material.

  In the case where the second conductive layer 181 is made of Ag, the second diffusion prevention layer 182 may be made of IZO. At this time, if the second diffusion prevention layer 182 and the first diffusion prevention layer 173 have the same thickness, the second diffusion prevention layer 182 and the first diffusion prevention layer 173 are formed at the same time as described later. Can do.

(Second bonding layer 183)
As shown in FIG. 1, a second bonding layer 183 is laminated on the second diffusion prevention layer 182.
The second bonding layer 183 is provided so as to cover the entire surface of the second diffusion prevention layer 182. The central portion of the second bonding layer 183 has a certain film thickness. The surface opposite to the surface in contact with the second diffusion prevention layer 182 at the center of the second bonding layer 183 (the upper surface 180c of the second electrode 180) is substantially flat. On the other hand, the end portion of the first bonding layer 174 gradually decreases in thickness as it approaches the end, so that the surface of the end portion of the first bonding layer 174 is exposed to the semiconductor layer exposed surface 140c of the n-type semiconductor layer 140. Inclined.

Similar to the first bonding layer 174 of the first electrode 170 described above, the second bonding layer 183 includes at least one metal layer. In this case, Au (gold) is generally used for the layer (the outermost layer) provided farthest from the second diffusion preventing layer 182. In the present embodiment, a single layer film of Au is used as the second bonding layer 183, similarly to the first bonding layer 174, but as described in the first diffusion prevention layer 173, the second bonding layer 183 is used. Can be a laminated structure composed of a plurality of metal layers.
In the present embodiment, the entire thickness of the second bonding layer 183 is set to 300 nm, for example. The entire thickness of the second bonding layer 183 can be used without limitation as long as the second protruding electrode 220 described later can be provided. The total thickness of the second bonding layer 183 is preferably 50 to 8000 nm.

  Note that if the second bonding layer 183 and the first bonding layer 174 have the same configuration and the same film thickness, the second bonding layer 183 and the first bonding layer 174 can be formed simultaneously as described later.

(Second adhesion layer 184)
As shown in FIG. 1, the second adhesion layer 184 is preferably laminated on the second bonding layer 183. The second adhesion layer 184 is provided to improve the physical adhesion between the second bonding layer 183 made of Au and the protective layer 190, similarly to the first adhesion layer 175 of the first electrode 170 described above. It has been.
The second adhesion layer 184 is provided so as to cover the surface of the second bonding layer 183 except for a portion where the second protruding electrode 220 is provided on the second bonding layer 183 when viewed in plan. Note that the second adhesion layer 184 is provided so that the end thereof is in contact with the semiconductor layer exposed surface 140 c of the n-type semiconductor layer 140.

  In the present embodiment, the second adhesion layer 184 is made of Ta (tantalum) like the first adhesion layer 175. However, Ti (titanium), Ni (nickel), or W (tungsten) can be used as the material of the second adhesion layer 184 in addition to Ta (tantalum), for example. In the present embodiment, the thickness of the second adhesion layer 184 is set to 10 nm, for example. The thickness of the second adhesion layer 184 is preferably 5 to 400 nm, more preferably 5 to 300 nm, and even more preferably 7 to 100 nm. If the thickness of the second adhesion layer 184 is less than 5 nm, the adhesion between the second bonding layer 183 and the protective layer 190 is not preferable.

<Protective layer 190>
As shown in FIG. 1, the protective layer 190 includes a region where the first electrode 170 is not provided on the upper surface 160c of the p-type semiconductor layer 160, and a region where the second electrode 180 is not provided on the exposed surface 140c of the semiconductor layer. The semiconductor layer exposed surface 140c is laminated so as to cover the side surface of the laminated semiconductor layer 100 exposed. However, the protective layer 190 is a region where a first protruding electrode 210 described later is formed on the upper surface 170c of the first electrode 170, and a region where a second protruding electrode 220 described later is provided on the upper surface 180c of the second electrode 180. Except for the first electrode 170 and the second electrode 180 are stacked.
The protective layer 190 has a function of preventing water or the like from entering the stacked semiconductor layer 100, the first electrode 170, and the second electrode 180 from the outside. In the present embodiment, protective layer 190 is made of SiO ₂ (silicon dioxide).

<First protruding electrode 210>
The first protruding electrode 210 is provided on the first electrode 170.
In the present embodiment, the planar shape of the first projecting electrode 210 is a shape having an arc-shaped portion in which the outline of the outer peripheral portion of the first electrode 170 is substantially reduced as shown in FIG. The area when viewed from above the first protruding electrode 210 is, for example, 30% of the area surrounded by the outline of the outer peripheral portion of the first electrode 170. The planar shape of the first protruding electrode 210 may be a circle or a rectangle.
As shown in FIG. 1, the first protruding electrode 210 includes a first base portion 211 stacked on the first bonding layer 174 and a first connection portion 212 stacked on the first base portion 211. Yes.
In the present embodiment, the first base 211 is made of the same Au (gold) as the first bonding layer 174. The first connection part 212 is made of an AuSn (gold tin) alloy.
The reason why the AuSn alloy is provided for the first connection portion 212 is that the AuSn alloy has a melting point of 300 ° C. or lower and a positive electrode 511 provided on the surface of the wiring substrate 500 on which the light emitting chip 1 is mounted (see FIG. 8 described later). ) For easy thermocompression bonding. The first connecting portion 212 may not be provided on the first protruding electrode 210, and an AuSn alloy layer may be provided on the positive electrode 511 (see FIG. 8 described later) of the wiring board 500.
In the present embodiment, the total thickness T1 of the first protruding electrode 210 is, for example, 15 μm. The thickness of the 1st connection part 212 is 1-3 micrometers.

<Second protruding electrode 220>
The second protruding electrode 220 is provided on the second electrode 180.
In the present embodiment, the planar shape of the second protruding electrode 220 is circular (see FIG. 2). The diameter of the second protruding electrode 220 is also 100 μm, for example. Note that the planar shape of the second protruding electrode 220 may not be circular.
The second protruding electrode 220 includes a second base portion 221 stacked on the second bonding layer 183 and a second connection portion 222 stacked on the second base portion 221.
In the present embodiment, the second protruding electrode 220 has the same configuration as the first protruding electrode 210. That is, the second base portion 221 is made of the same Au (gold) as the second bonding layer 183. And the 2nd connection part 222 is comprised with the AuSn (gold tin) alloy.
The reason for providing the AuSn alloy for the second connection portion 222 is the same as that for the first connection portion 212. Alternatively, the second connecting portion 222 may not be provided on the second protruding electrode 220, and an AuSn alloy layer may be provided on the negative electrode 512 (see FIG. 8 described later) of the wiring board 500.
In the present embodiment, the entire thickness T2 of the second protruding electrode 220 is, for example, 15 μm, as with the first protruding electrode 210. The thickness of the second connection part 222 is 1 to 3 μm.

  As described above, since the first protruding electrode 210 and the second protruding electrode 220 have the same configuration, they can be formed simultaneously in the manufacturing process of the light-emitting chip 1 described later. Further, when formed simultaneously, the total thickness T1 of the first protruding electrode 210 is the same as the total thickness T2 of the second protruding electrode 220 (T1 = T2).

In the present embodiment, the total thickness T2 of the second protruding electrode 220 (15 μm in the present embodiment) is the depth D at which the stacked semiconductor layer 100 is removed by etching to provide the semiconductor layer exposed surface 140c. (T2> D) is set larger than (in this embodiment, 0.6 to 0.7 μm).
Then, the metal reflective layer 172 (150 nm) of the first electrode 170, the second conductive layer 181 (150 nm) of the second electrode 180, the first diffusion prevention layer 173 (50 nm) of the first electrode 170, and the second electrode 180. The second diffusion prevention layer 182 (50 nm), the first bonding layer 174 (300 nm) of the first electrode 170, and the second bonding layer 183 (300 nm) of the second electrode 180 have the same thickness. The thickness of the first conductive layer 171 of the first electrode 170 is 5 nm, which is thinner than other layers. Therefore, the thickness (505 nm) of the first electrode 170 from the upper surface 160 c of the p-type semiconductor layer 160 to the upper surface 170 c of the first bonding layer 174, and the first thickness from the semiconductor layer exposed surface 140 c to the upper surface 180 c of the second bonding layer 183. There is almost no difference from the thickness of the two electrodes 180 (500 nm).
Therefore, the surface 220c of the second protruding electrode 220 (the surface opposite to the surface in contact with the second base portion 221 of the second connection portion 222) is the first portion where the distance from the substrate 10 of the protective layer 190 is the largest. It protrudes from the surface 190 c on the second adhesion layer 184 of the electrode 170.

  In the present embodiment, the distance between the surface 220c of the second protruding electrode 220 and the surface 210c of the first protruding electrode 210 (the surface opposite to the surface in contact with the first base 211 of the first connecting portion 212) with the substrate 10. Is substantially the same as the depth D at which the stacked semiconductor layer 100 is removed by etching to provide the semiconductor layer exposed surface 140c. That is, the surface 220c of the second protruding electrode 220 and the surface 210c of the first protruding electrode 210 are different in distance from the back surface 10b of the substrate 10.

  For example, when the thickness of the second conductive layer 181 constituting the second electrode 180 is 100 nm, the thickness of the second diffusion prevention layer 182 is 100 nm, and the thickness of the second bonding layer 183 is 1 μm, the exposed surface of the semiconductor layer The thickness of the second electrode 180 from 140 c to the upper surface 180 c of the second bonding layer 183 is 1.2 μm. This thickness is a depth D (0.6 to 0.7 μm in this embodiment) from which the stacked semiconductor layer 100 is removed by etching to provide the semiconductor layer exposed surface 140c, and the upper surface of the p-type semiconductor layer 160. A value obtained by adding the thickness (505 nm) of the first electrode 170 from 160 c to the upper surface 170 c of the first bonding layer 174. In this case, the difference in distance between the surface 220c of the second protruding electrode 220 and the surface 210c of the first protruding electrode 210 (the surface opposite to the surface in contact with the first base 211 of the first connecting portion 212) with the substrate 10 is calculated. Can be set small.

[Method for Manufacturing Light-Emitting Chip 1]
Next, an example of a method (manufacturing method) for manufacturing the light emitting chip 1 shown in FIG. 1 will be described.
The wafer 30 is in a state in which a plurality of light emitting elements 20 are collectively provided on the substrate 10 and is in a state before being divided into individual light emitting chips 1. Here, also in the process in the middle of manufacturing the wafer 30, it is called the wafer 30.

FIG. 4 is an example of a flowchart illustrating a method for manufacturing the light emitting chip 1. As shown in FIG. 4A, the method for manufacturing the light emitting chip 1 includes a semiconductor element forming step (step 101) for forming the light emitting element 20 provided with the first electrode 170 and the second electrode 180 on the substrate 10. A projecting electrode forming step (step 102) for forming the first projecting electrode 210 on the first electrode 170 and the second projecting electrode 220 on the second electrode 180 of the light emitting element 20, and a planned dividing line of the substrate 10 after step 102 A fragile region forming step (step 103) for forming a fragile region 321 in the substrate 10 along H1 to H5 and V1 to V5 (see FIG. 6 described later), and a wafer in which the light emitting element 20 is formed on the substrate 10 30 includes a dividing step (step 104) in which the light emitting chip 1 is divided starting from the fragile region 321.
Then, in the semiconductor element formation step (step 101), as shown in FIG. 4B, the laminated semiconductor layer 100 including the intermediate layer 120, the base layer 130, the light emitting layer 150, and the p-type semiconductor layer 160 on the substrate 10 is formed. A semiconductor layer stacking step to be formed (step 201), a semiconductor layer exposed surface forming step (step 202) in which a part of the stacked semiconductor layer 100 is cut away and removed to form the semiconductor layer exposed surface 140c, and the stacked semiconductor layer 100 A first electrode forming step (step 203) for forming the first electrode 170 on the upper surface 160c, a second electrode forming step (step 204) for forming the second electrode 180 on the semiconductor layer exposed surface 140c, and the protective layer 190. Forming a protective layer (step 205).

  In the method for manufacturing the light-emitting chip 1 to which the present exemplary embodiment is applied, the wafer is subjected to heat treatment (annealing) after the first electrode formation step (step 203) and the second electrode formation step (step 204) as necessary. There may be a case where an annealing process is further performed.

Hereinafter, each process is demonstrated in order.
FIG. 5 is a diagram for explaining the semiconductor element formation step (step 101 in FIG. 4A) and the protruding electrode formation step (step 102 in FIG. 4A). FIG. 5 shows a cross-sectional view of the diameter of the wafer 30 (VV line of the wafer 30 shown in FIG. 6 described later). In FIG. 5, it is assumed that four light emitting chips 1 are arranged on the diameter (VV line) of the wafer 30 as an example.

(Semiconductor layer lamination process)
The semiconductor layer stacking step shown in FIG. 5A (step 201 in FIG. 4B) will be described.
First, the intermediate layer 120 is laminated on the surface 10a of the substrate 10 by sputtering.
When the intermediate layer 120 having a single crystal structure is formed by sputtering, the flow rate ratio between nitrogen gas and inert gas in the chamber is set to 50 to 100%, preferably 75%, of nitrogen gas. Is desirable.
When the intermediate layer 120 having columnar crystals (polycrystals) is formed by sputtering, the flow rate ratio between nitrogen gas and inert gas in the chamber is 1 to 50%, preferably 25%. It is desirable to be Note that the intermediate layer 120 can be formed not only by the sputtering method described above but also by the MOCVD method.

After the formation of the intermediate layer 120, a single crystal base layer 130 is formed on the intermediate layer 120. The underlayer 130 may be formed by sputtering or MOCVD.
After the foundation layer 130 is formed, the n-type semiconductor layer 140 is formed by laminating the n-contact layer 140a and the n-cladding layer 140b on the foundation layer 130. The n contact layer 140a and the n clad layer 140b may be formed by a sputtering method or an MOCVD method.

  The light emitting layer 150 can be formed by either sputtering or MOCVD, but MOCVD is particularly preferable. Specifically, the barrier layers 150a and the well layers 150b may be alternately and repeatedly stacked, and the barrier layers 150a may be stacked in the order in which the barrier layers 150a are disposed on the n-type semiconductor layer 140 side and the p-type semiconductor layer 160 side. .

  The p-type semiconductor layer 160 may be formed by either sputtering or MOCVD. Specifically, a p-cladding layer 160a and a p-contact layer 160b may be sequentially stacked on the light emitting layer 150.

(Semiconductor layer exposed surface forming process)
Next, the semiconductor layer exposed surface forming step (step 202 in FIG. 4B) shown in FIG. 5B will be described.
On the upper surface 160c of the p-type semiconductor layer 160 of the wafer 30 in which the intermediate layer 120, the base layer 130, and the laminated semiconductor layer 100 are formed on the surface 10a of the substrate 10, a conventionally known photolithography method or the like is used. A resist film (not shown) in which a portion where the semiconductor layer exposed surface 140c is formed becomes an opening is formed, and a part of the laminated semiconductor layer 100 is removed by a technique such as etching, which is subsequently performed, and the n contact layer 140a A part is exposed to form a semiconductor layer exposed surface 140c. Thereafter, the resist film is removed.

(First electrode forming step)
The first electrode forming step (step 203 in FIG. 4B) shown in FIG. 5C will be described.
A resist film 251 having a portion where the first electrode 170 on the upper surface 160c of the p-type semiconductor layer 160 is formed is formed by a conventionally known photolithography method or the like.
Note that, at the opening of the resist film 251, it is preferable that the side wall of the resist film 251 has an overhang shape (a state indicated by an arrow A).
Thereafter, the material of the first conductive layer 171, the metal reflective layer 172, the first diffusion prevention layer 173, and the first bonding layer 174 is formed on the wafer 30 by a conventionally known sputtering method or vacuum deposition method. Deposit continuously by technique.
Thereafter, by immersing the wafer 30 in a resist stripping solution (registry mover), the first conductive layer 171, the metal reflective layer 172, the first diffusion prevention layer 173, the first diffusion layer 173, and the resist film 251 are deposited together with the resist film 251. The film of the material of one bonding layer 174 is removed (lift-off method). Thereby, the first conductive layer 171, the metal reflection layer 172, the first diffusion prevention layer 173, and the first bonding layer 174 are formed.

The material constituting each layer is difficult to adhere to the upper surface 160c of the p-type semiconductor layer 160 in the overhanging (arrow A) portion of the opening of the resist film 251 due to the shadow effect. For this reason, in the edge part of each layer, a film thickness becomes thin as it approaches the edge. In this manner, the thicknesses of the respective end portions of the first conductive layer 171, the metal reflective layer 172, the first diffusion prevention layer 173, and the first bonding layer 174 can be reduced as approaching the ends.
In addition, since the first conductive layer 171, the metal reflective layer 172, the first diffusion prevention layer 173, and the first bonding layer 174 are sequentially deposited, the first conductive layer 171, the metal reflective layer 172, the first The positions of the ends of the 1 diffusion preventing layer 173 and the first bonding layer 174 are the same.

Note that when the heat treatment is performed on the first conductive layer 171, the formation of the first conductive layer 171 and the formation of the metal reflection layer 172, the first diffusion prevention layer 173, and the first bonding layer 174 may be performed separately.
That is, after the first conductive layer 171 is deposited, the resist film is removed and heat treatment is performed. A resist film may be provided again, and films of materials of the metal reflection layer 172, the first diffusion prevention layer 173, and the first bonding layer 174 may be sequentially deposited. At this time, an opening portion of the resist film for forming the metal reflection layer 172, the first diffusion prevention layer 173, and the first bonding layer 174 is formed so that the end portion of the metal reflection layer 172 does not contact the p-type semiconductor layer 160. The first conductive layer 171 may be provided.

(Second electrode forming step)
The second electrode formation step (step 204 in FIG. 4B) shown in FIG. 5D will be described.
Similar to the first electrode formation step for forming the first electrode 170, the second electrode 180 is formed. That is, a resist film 252 in which the side wall of the opening is formed in an overhang shape is formed, and then a film of the material of the second conductive layer 181, the second diffusion prevention layer 182, and the second bonding layer 183 is formed by a conventionally known sputtering method Or it deposits continuously by film-forming techniques, such as a vacuum evaporation method.
Thereafter, by immersing the wafer 30 in a resist stripping solution, the resist film 252 and the second conductive layer 181, the second diffusion prevention layer 182, and the second bonding layer 183 deposited on the resist film 252 are formed. Remove (lift-off method). Thereby, the second conductive layer 181, the second diffusion prevention layer 182, and the second bonding layer 183 are formed.
In the first electrode formation step, if the formation of the first conductive layer 171 and the formation of the metal reflection layer 172, the first diffusion prevention layer 173, and the first bonding layer 174 are performed separately, the second electrode 180 of the second electrode 180 is formed. Two conductive layers 181 and a metal reflection layer 172 of the first electrode 170 are formed simultaneously; a second diffusion prevention layer 182 of the second electrode 180 and a first diffusion prevention layer 173 of the first electrode 170 are formed simultaneously; The second bonding layer 183 of the second electrode 180 and the first bonding layer 174 of the first electrode 170 can be formed simultaneously.

  Although not shown, a first adhesion layer 175 in the first electrode 170 and a second adhesion layer 184 in the second electrode 180 are formed simultaneously thereafter. The first adhesion layer 175 and the second adhesion layer 184 are formed by depositing a film of a material constituting the first adhesion layer 175 and the second adhesion layer 184 on the entire surface of the wafer 30, and then a conventionally known photolithography method or the like. The resist film may be formed by the method described above, followed by a conventionally known method such as etching. In addition, the resist film is formed by a conventionally known photolithography method, the subsequent deposition of the material of the material constituting the first adhesion layer 175 and the second adhesion layer 184, the removal of the resist film, and the resist film. Alternatively, the material constituting the first adhesion layer 175 and the second adhesion layer 184 may be lifted off.

(Protective layer forming step)
Although not shown in FIG. 5, the protective layer forming step (step 205 in FIG. 4B) will be described.
After a film constituting the protective layer 190 made of SiO ₂ is formed on the wafer 30, a resist film 253 is formed on the film constituting the protective layer 190 by a conventionally known photolithography method or the like (FIG. 5). (See (e)). The resist film 253 has an opening in a region where the first protruding electrode 210 is formed on the first electrode 170 and a region where the second protruding electrode 220 is formed on the second electrode 180.
Then, the protective layer 190, the first adhesive layer 175, and the second adhesive layer 184 in the region where the first protruding electrode 210 and the second protruding electrode 220 are formed are removed by etching using a conventionally known method such as etching, and then the resist The film 253 is removed.

(Projection electrode formation process)
A protruding electrode forming step (step 102 in FIG. 4A) for forming the first protruding electrode 210 and the second protruding electrode 220 shown in FIG. 5E will be described.
A TiW alloy layer composed of Ti or Ti and W (not shown) and an under bump metal layer composed of an Au layer (abbreviated as UBM film) are formed on the entire surface of the wafer 30, and then a resist film 253 is formed again. Similarly to the above, the resist film 253 is provided with openings in a region where the first protruding electrode 210 is formed on the first electrode 170 and a region where the second protruding electrode 220 is formed on the second electrode 180. Yes.
Next, a material (Au (gold) in the present embodiment) constituting the first base 211 of the first protruding electrode 210 and the second base 221 of the second protruding electrode 220 is formed by a known electrolytic plating method.
Next, a material (AuSn (gold-tin) alloy in the present embodiment) constituting the first connection portion 212 of the first protruding electrode 210 and the second connection portion 222 of the second protruding electrode 220 is formed by a conventionally known sputtering method. The film is deposited by a film forming technique such as vacuum evaporation.
Next, the resist film 253 is removed, and subsequently, the UBM film exposed by removing the resist film 253 is removed by etching. As the etching solution, for example, a mixed solution of KI and I ₂ can be used for Au, and a sulfuric acid hydrolyzed solution can be used for Ti or TiW alloy.
As described above, the wafer 30 before being divided into the light emitting chips 1 is manufactured.

The wafer 30 thus obtained may be heat-treated at 150 to 300 ° C., more preferably 200 to 250 ° C. in a reducing atmosphere such as nitrogen.
This heat treatment is performed between the first conductive layer 171, the metal reflective layer 172, the first diffusion prevention layer 173, the first bonding layer 174, the first adhesion layer 175, the protective layer 190, the first base portion 211, the first connection portion 212, and Improved adhesion and electrical contact between the second conductive layer 181, the second diffusion prevention layer 182, the second bonding layer 183, the second adhesion layer 184, the protective layer 190, the second base portion 221, and the second connection portion 222. This is to reduce the resistance. Note that heat treatment is not necessarily performed, but it is preferable to perform the heat treatment in order to improve adhesion and reduce electrical contact resistance.

Next, the weak region forming step (step 103 in FIG. 4A) and the dividing step (step 104 in FIG. 4A) for dividing the semiconductor chip will be described.
FIG. 6 is a plan view of the wafer 30 as viewed from the side where the first protruding electrode 210 and the second protruding electrode 220 are formed.
In FIG. 6, a plurality of light emitting chips 1 are formed side by side on the wafer 30 at an X direction pitch px and a Y direction pitch py. In FIG. 6, for example, four light emitting chips 1 are arranged along the diameter of the wafer 30 in the X direction, and four light emitting chips 1 are arranged along the diameter of the wafer 30 in the Y direction. . In addition, the wafer manufacturing process shown in FIG. 5 is sectional drawing in the VV line.
Then, it is assumed that the wafer 30 is divided into the light emitting chips 1 along the planned dividing lines H1 to H5 and the divided planned lines V1 to V5. In FIG. 6, the planned dividing lines H <b> 1 to H <b> 5 and the planned dividing lines V <b> 1 to V <b> 5 are shown as lines, but are vertical surfaces extending from the front surface of the wafer 30 to the back surface of the wafer 30 (back surface 10 b of the substrate 10). Surface). Therefore, below, the division | segmentation planned line (H1-H5 and V1-V5) is also called a division | segmentation planned surface (H1-H5 and V1-V5).
In FIG. 6, the number of light emitting chips 1 on the wafer 30 is 4 × 4. However, the number of light emitting chips 1 on the wafer 30 is determined by the diameter of the wafer 30 and px and py of the light emitting chip 1.

FIG. 7 is a diagram for explaining the fragile region forming step (step 103 in FIG. 4A) and the dividing step (step 104 in FIG. 4A).
In the weak region forming step, the weak region 321 is formed inside the substrate 10 of the wafer 30. In the dividing step, the wafer 30 is divided into the light emitting chips 1 starting from the fragile region 321.
(Vulnerable area formation process)
The fragile region forming step shown in FIG. 7A (step 103 in FIG. 4A) will be described.
The side on which the first protruding electrode 210 and the second protruding electrode 220 are formed on the wafer 30 is attached to one surface of the dicing tape 315 and the surface to which the adhesive is applied.
The surface 210c of the first protruding electrode 210 and the surface 220c of the second protruding electrode 220 of the wafer 30 are different in distance from the surface 10a of the substrate 10. However, as described above, the distance difference in the present embodiment is 0.6 to 0.7 μm. Further, the dicing tape 315 is a flexible plastic film and is coated with an adhesive. Therefore, the surface 210c of the first protruding electrode 210 and the surface 220c of the second protruding electrode 220 of the wafer 30 are bonded and fixed to the dicing tape 315 regardless of the difference in the distance from the surface 10a of the substrate 10.

Next, a metal wafer ring 316 is attached and fixed to the surface of the dicing tape 315 to which the adhesive has been applied. The wafer ring 316 functions as a fixing jig for the wafer 30 during dicing.
Then, with the wafer ring 316 and the wafer 30 fixed, the surface of the dicing tape 315 opposite to the surface on which the wafer ring 316 and the wafer 30 are fixed is placed on the stage 317 of the dicing apparatus.
Note that before the wafer 30 is attached to the dicing tape 315, the thickness of the substrate 10 may be reduced by polishing (grinding).

Next, as shown in FIG. 7A, a laser beam 345 focused on the inside of the substrate 10 is irradiated along the planned dividing lines H1 to H5 and V1 to V5 from the back surface 10b of the substrate 10. FIG. 7A shows that the fragile region 321 is formed inside the substrate 10 along the planned division line H <b> 2 of the substrate 10.
Specifically, the laser beam 345 is fixed, and the stage 317 of the dicing apparatus is moved at a predetermined speed so that the laser beam 345 moves along the planned dividing lines H1 to H5 and V1 to V5.
As the laser beam 345, a YAG laser beam can be used. When a pulse laser is used for the laser beam 345, the fragile region 321 is formed in a dotted shape inside the substrate 10 along the planned dividing lines H1 to H5 and V1 to V5. At this time, after forming the fragile region 321 along the planned division line H1 in the X direction, the stage 317 is moved to form the fragile region 321 along the planned division line H2. Similarly, a fragile region 321 is formed along the planned dividing lines H3, H4, and H5. Thereafter, the fragile region 321 is formed along the planned dividing lines V1 to V5 in the Y direction.

  Note that the fragile region 321 may be provided at a different distance from the back surface 10 b of the substrate 10. In this case, it is preferable to provide the fragile region 321 first at a large distance from the back surface 10 b of the substrate 10. If the fragile region 321 is provided at a small distance from the back surface 10b of the substrate 10 and then the fragile region 321 is provided at a large distance from the back surface 10b of the substrate 10, the fragile region provided at a small distance from the back surface 10b of the substrate 10 The laser beam 345 is disturbed by the beam 321, and the condensing of the laser beam 345 is hindered, making it difficult to form the fragile region 321 at a large distance from the back surface 10 b of the substrate 10.

(Division process)
The dividing process shown in FIGS. 7B and 7C (step 104 in FIG. 4A) will be described.
As shown in FIG. 7B, the wafer 30 on which the fragile region 321 is formed is a surface opposite to the surface on which the wafer ring 316 and the wafer 30 are fixed in a state where the dicing tape 315 and the wafer ring 316 are provided. Is set to the stage 318 of the cutting device.
The stage 318 of the braking device includes a ring-shaped ring stage 318c and two sub-stages 318a and 318b that are provided at the center of the ring stage 318c and are arranged with a linear gap (gap) therebetween. Yes. Therefore, the wafer 30 is arranged so that any one of the division lines H1 to H5 and V1 to V5 corresponds to the gap. In FIG. 7B, the planned division line H3 is arranged so as to coincide with the gap between the two substages 318a and 318b.
Then, as shown in FIG. 7C, the blade 320 is pressed against the back surface 10b of the substrate 10 along the planned division line (any one of H1 to H5 and V1 to V5).
At this time, both the surface 210c of the first protruding electrode 210 and the surface 220c of the second protruding electrode 220 protrude from the surface 190c of the protective layer 190 when viewed from the substrate 10 side (see FIG. 1). And the division | segmentation planned line (any of H1-H5, V1-V5) is provided between the protruding electrodes (the 1st protruding electrode 210 and the 2nd protruding electrode 220), as shown in FIG. Therefore, when the blade 320 is pressed against the back surface 10b of the substrate 10, the wafer 30 has the front surface 210c of the first protruding electrode 210 adjacent to each other across the planned dividing line (any one of H1 to H5 and V1 to V5). And a portion of the planned dividing line (any one of H1 to H5 and V1 to V5) sinks with the surface of the second protruding electrode 220 as a fulcrum. At this time, if the sinking amount is large, a force (moment) for cutting the wafer 30 is large and the wafer 30 is easily cut.
In the present embodiment, the projecting electrodes (first projecting electrode 210 and second projecting electrode 220) are provided to increase the sinking amount, so that the wafer 30 can be easily divided into the light emitting chips 1.
Therefore, in the present embodiment, since it is not necessary to provide the surface groove of the wafer 30, in the step of forming the groove, the surface of the wafer 30, that is, the surface of the semiconductor element is contaminated by scattering of the material constituting the groove. It will not be done.

[Usage of Light-Emitting Chip 1]
Next, a method for using the light emitting chip 1 shown in FIG. 1 will be described.
FIG. 8 is a diagram illustrating an example of a configuration of the light emitting device 3 in which the light emitting chip 1 illustrated in FIG. 1 is mounted on the wiring substrate 500.
The wiring board 500 includes a positive electrode 511 and a negative electrode 512 as terminals on the surface 500a. When the positive electrode 511 and the negative electrode 512 of the wiring substrate 500 are opposed to the first protruding electrode 210 and the second protruding electrode 220 of the light emitting chip 1 shown in FIG. 1, the positive electrode 511 and the first protruding electrode 210 are connected. The negative electrode 512 and the second protruding electrode 220 are provided at a position where they can be connected.
Further, a plurality of wirings for supplying current to the positive electrode 511 and the negative electrode 512 are provided on the front surface 500a or the front surface 500a and the back surface 500b of the wiring substrate 500, although not shown.
The wiring board 500 is a multilayer wiring having one or more layers (wiring layers) provided with wirings connected to the positive electrode 511 and the negative electrode 512 through via holes inside the wiring board 500. It may be a substrate.

Then, the first protruding electrode 210 and the second protruding electrode 220 of the light emitting chip 1 are brought into contact with the positive electrode 511 and the negative electrode 512 of the wiring substrate 500, respectively, and the first connection portion 212 and the second connection of the light emitting chip 1 are connected. The light emitting chip 1 is pressed against the wiring board 500 in a state where the part 222 is heated to a temperature at which the part 222 can be melted. Thus, the positive electrode 511 and the first protruding electrode 210 are electrically connected, and the negative electrode 512 and the second protruding electrode 220 are electrically connected.
A method of mounting the light emitting chip 1 on the wiring substrate 500 is called face-down (FD) mounting.

In FIG. 8, the light emitting chip 1 is mounted such that the back surface 10 b of the substrate 10 is inclined with respect to the front surface 500 a of the wiring substrate 500. This is because the distance between the surface 220c of the second protruding electrode 220 and the surface 210c of the first protruding electrode 210 from the back surface 10b of the substrate 10 is different from each other. However, in FIG. 8, the light emitting chip 1 is shown to be greatly inclined with respect to the wiring substrate 500, but as described above, the distance difference is 0.6 to 0.7 μm, and the length of one side of the light emitting chip 1. The inclination of the light emitting chip 1 with respect to the wiring substrate 500 is small compared to 350 μm.
As described above, by adjusting the thicknesses of the second conductive layer 181, the second diffusion prevention layer 182, and the second bonding layer 183 that constitute the second electrode 180, the surface 220 c of the second protruding electrode 220 and A difference in distance between the front surface 210c of the first protruding electrode 210 and the back surface 10b of the substrate 10 can be suppressed.

The operation of the light emitting device 3 in which the light emitting chip 1 is mounted face down (FD) on the wiring substrate 500 will be described.
When a potential is applied between the positive electrode 511 and the negative electrode 512 via a wiring provided on the wiring substrate 500 to flow a current from the positive electrode 511 to the negative electrode 512, the first protruding electrode 210 and the first electrode 2 Current flows through the stacked semiconductor layer 100 of the light emitting chip 1 through the protruding electrode 220, and blue light is emitted from the light emitting layer 150. In the first electrode 170, a uniform current is supplied to the p-type semiconductor layer 160 through the first bonding layer 174, the first diffusion prevention layer 173, the metal reflection layer 172, and the first conductive layer 171. .

  Of the light emitted from the light emitting layer 150, the light traveling toward the substrate 10 is transmitted through the n-type semiconductor layer 140, the base layer 130, the intermediate layer 120, and the substrate 10, and in the direction indicated by the arrow shown in FIG. To exit.

  On the other hand, the light emitted from the light emitting layer 150 toward the first electrode 170 side reaches the metal reflection layer 172 via the p-type semiconductor layer 160 and the first conductive layer 171 and is reflected by the metal reflection layer 172. Is done. The light reflected by the metal reflective layer 172 passes through the first conductive layer 171, the p-type semiconductor layer 160, the light emitting layer 150, the n-type semiconductor layer 140, the base layer 130, the intermediate layer 120, and the substrate 10, and FIG. It emits in the direction of the arrow shown in FIG.

[Light emitting chip 2]
Next, the light emitting chip 2 will be briefly described.
FIG. 9 is a diagram showing an example of a schematic cross-sectional view of the light-emitting chip 2 to which the present exemplary embodiment is applied. FIG. 10 is a diagram illustrating an example of a schematic plan view of the light emitting chip 2 as viewed from the direction of the arrow X in FIG. 9. 9 is a cross-sectional view taken along line IX-IX in FIG.
The chip size of this embodiment is a square type with a side of 350 μm. Structure and manufacturing method other than that a metal reflection layer 172 having a diameter of 60 μm to 110 μm, a first diffusion prevention layer 173, a first bonding layer 174, and a first adhesion layer 175 are sequentially formed on the first conductive layer 171, and The method of use is the same as that of the light emitting chip 1.

Hereinafter, the present invention will be specifically described based on examples relating to a semiconductor element (light emitting element 20) having the light emitting layer 150, but the present invention is not limited to these examples.
Example 1
As shown below, a group III nitride semiconductor light-emitting device 20 having a light-emitting layer 150 made of a gallium nitride-based compound semiconductor (the shape of the device is the same as that of the light-emitting chip 1 shown in FIGS. 1 and 2) was produced.

As shown in FIG. 1, a 4 μm-thick underlayer 130 made of undoped GaN was formed on a C-plane sapphire single crystal substrate 10 through an intermediate layer 120 made of AlN. Then, an n-contact layer 140a having a thickness of 3 μm made of Si-doped (concentration 1 × 10 ¹⁹ / cm ³ ) GaN, Si-doped (concentration 1 × 10 ¹⁸ / cm ³ ) In _0.1 Ga _0. n-cladding layer 140b with a thickness of 13nm made of ₉ n (n-contact layer 140a and n n-type semiconductor layer 140 from the cladding layer 140b is formed.), the barrier layer 150a and the _{in 0.2} the thickness 16nm of GaN After the 2.5 nm-thick well layers 150b made of Ga _0.8 N are alternately stacked six times, the light-emitting layer 150 having a multiple quantum well structure in which a barrier layer 150a is finally provided, Mg doped (concentration 1 × 10) _{^{20 / cm 3) Al 0.07 Ga}} 0.93 p -cladding layer 160a and the Mg-doped thick 3nm consisting N (concentration 8 × ¹⁰ 19 ^/ cm 3) or GaN A stack made of a group III nitride semiconductor having a thickness of 9 μm, which is formed by sequentially stacking a p contact layer 160b having a thickness of 0.18 μm. A semiconductor layer 100 was formed.

  Next, a first conductive layer 171 (translucent positive electrode) made of IZO was formed at a predetermined position on the p-contact layer 160b of the laminated semiconductor layer 100 using a known photolithography technique and lift-off technique. Next, using a known photolithography technique, a metal reflective layer (Ag) 172, a first diffusion prevention layer (Ta) 173, and a first bonding layer (Pt / Au) are formed on the first conductive layer 171 (translucent positive electrode). 174 and a first adhesion layer (Ta) 175 were sequentially formed, and a first electrode 170 having an Ag / Ta / Pt / Au / Ta structure was formed on the first conductive layer 171 (translucent positive electrode).

Next, using the known photolithography technique and reactive etching technique, the n contact layer 140a is exposed in a semicircular shape to form the semiconductor layer exposed surface 140c in the stacked semiconductor layer 100 formed up to the first electrode 170. did. Further, a second conductive layer (Al) 181, a second diffusion prevention layer (Ta) 182, a second bonding layer (Pt / Au) 183, and a second adhesion layer (Ta) 184 are sequentially formed on the semiconductor layer exposed surface 140 c. Then, the second electrode 180 having an Al / Ta / Pt / Au / Ta structure was formed on the semiconductor layer exposed surface 140c by a known method.
Next, a protective layer 190 made of SiO _{2 is formed} , and Au of the first bonding layer 174 of the first electrode 170 and the second bonding layer 183 of the second electrode 180 is formed using a known photolithography technique and reactive etching technique. The surface was exposed.
Next, after a TiW / Au laminated film was formed on the entire surface of the wafer 30 by a known sputtering method, a resist film having exposed portions of the first bonding layer 174 and the second bonding layer 183 was formed. Au of 13 μm was grown on the exposed portions of the first bonding layer 174 and the second bonding layer 183 by a known electrolytic plating method, and then 2 μm of AuSn was formed by vapor deposition. The resist film and AuSn were removed by a known lift-off method, and Au and TiW were removed by an etching method to form the first protruding electrode 210 and the second protruding electrode 220.

  Next, by lapping and polishing the back surface 10b of the substrate 10, the total thickness of the semiconductor layer including the intermediate layer 120, the base layer 130, and the laminated semiconductor layer 100 and the thickness of the substrate 10 is 150 μm. Thus, the sapphire single crystal substrate 10 was thinned.

  Next, a fragile region forming step (see step 103 in FIG. 4A and FIG. 7A) for forming a fragile region by laser light irradiation was performed. First, the dicing tape 315 was affixed on the side of the wafer 30 on which the first protruding electrode 210 and the second protruding electrode 220 were provided, and placed on the stage 317 of the dicing apparatus. Next, two locations at different distances from the back surface 10b of the substrate 10 along the planned dividing lines (corresponding to H1 to H5 and V1 to V5 in FIG. 6) in which the planar size of the light emitting chip 1 is a 350 μm × 350 μm square shape. Was irradiated with a laser beam to form a two-stage weakened region 321.

Next, the blade 320 is pushed in from the back surface 10b side of the substrate 10 while the dicing tape 315 is adhered to the side where the first protruding electrode 210 and the second protruding electrode 220 of the wafer 30 are provided, and cracks are effectively generated. Thus, the light emitting chip 1 including the light emitting element 20 made of a group III nitride semiconductor was obtained.
Finally, the light emitting chip 1 is placed over the wiring substrate 500 using the AlN substrate, and the positive electrode 511 on the wiring substrate 500 and the first protruding electrode 210 of the light emitting chip 1 are connected to the negative electrode on the wiring substrate 500. The light emitting chip 1 and the wiring substrate 500 are aligned so that 512 corresponds to the second protruding electrode 220 of the light emitting chip 1, and then the light emitting chip 1 is pressed against the wiring substrate 500 while being heated to 300 ° C. The positive electrode 511 on the wiring substrate 500 and the first protruding electrode 210 of the light emitting chip 1 are electrically connected to the negative electrode 512 on the wiring substrate 500 and the second protruding electrode 220 of the light emitting chip 1, respectively. The light emitting device 3 (see FIG. 8) was obtained.
The wiring board 500 (light emitting device 3) on which the light emitting chip 1 was mounted was placed on the TO 18 and connected by a wire.
The LED characteristics of the light-emitting chip 1 obtained in Example 1 are as follows. When the forward voltage Vf is 3.11 V (forward current If is 20 mA), the emission wavelength is 452 nm and the emission output Po is 24.5 mW. It was.

  Next, with respect to the plurality of light emitting chips 1, 5 V was applied as the reverse voltage Vr, and the evaluation was made that the reverse current Ir is 2 μA or more as defective (NG). As a result, the occurrence rate of defects (NG) ( IR failure rate) was 0.5%.

(Examples 2 to 4, Comparative Examples 1 and 2)
The second embodiment is configured as shown in FIGS. 9 and 10, and has a metal reflective layer 172 having a diameter of 100 μm on the first conductive layer 171, a first diffusion prevention layer 173 thereon, and a first bonding layer 174 thereon. A light emitting device 20 was manufactured in the same manner as in Example 1 except that the films were sequentially formed.
Further, Examples 3 and 4 were carried out except that the height T1 of the first protruding electrode 210 described in Example 1 (= the height T2 of the second protruding electrode 220) was changed to the conditions described in FIG. In the same manner as in Example 1, a light-emitting element 20 (chip shape is the light-emitting chip 1 shown in FIGS. 1 and 2) was manufactured.
On the other hand, in Comparative Example 1, the light emitting device 20 was manufactured in the same manner as in Example 1 except that the first protruding electrode 210 and the second protruding electrode 220 were not formed.
Furthermore, in Comparative Example 2, the light emitting device 20 was manufactured in the same manner as in Example 2 except that the first protruding electrode 210 and the second protruding electrode 220 were not formed.
FIG. 11 shows the characteristics of Example 1 (the height T1 of the first protruding electrode 210 and the height T2 of the second protruding electrode 220, the shape of the light emitting chip), LED characteristics (forward voltage Vf (V), emission wavelength). The characteristics, LED characteristics, and IR defect rate (%) of Examples 2 to 4 and Comparative Examples 1 and 2 are shown together with λ (nm), light emission output Po (mW)), and IR defect rate (%). In FIG. 11, the height T1 of the first projecting electrode 210 and the height T2 of the second projecting electrode 220 are shown as projecting electrode height T1 = T2.

As can be seen from FIG. 11, in Examples 1 to 4, the IR defect rate (defect occurrence rate) was good within 2%. On the other hand, in Comparative Example 1 and Comparative Example 2, the IR defect rate was 5% or higher, which was a significantly higher value than Examples 1-4. As a result, in the case of Comparative Example 1 and Comparative Example 2, there is a high possibility that some damage has occurred in the pn junction portion (the region of the n-type semiconductor layer 140, the light emitting layer 150, and the p-type semiconductor layer 160) in the chip. This is considered to be caused by a high IR defect rate indicating the number of defective chips having a large leakage current.
As can be seen from the above implementation results, in Examples 1 to 4, the first projecting electrode 210 and the second projecting electrode 220 having the same height (T1 = T2) are present in the light emitting chip 1 (or the light emitting chip 2). As a result, the surface of these protruding electrodes becomes a fulcrum of force when the wafer 30 is divided, and the wafer 30 is easily divided.
More precisely, even if the first protruding electrode 210 and the second protruding electrode 220 are formed at the same height (T1 = T2), the height from the back surface 10b of the substrate 10 is different. It is also conceivable that the wafer 30 can be easily divided by the difference in the moment of the pressing force up to the two fulcrums (see FIG. 8).
Thus, according to the present invention, before the blade 320 is pressed against the substrate of the semiconductor wafer to divide the semiconductor wafer into a plurality of chips, the protruding electrodes are formed on the semiconductor wafer, so that the chips can be remarkably efficiently formed. It becomes possible to divide (separate).

  The present invention can provide a method for manufacturing a semiconductor element (or chip) having a pn junction portion, which has a low IR failure rate (failure occurrence rate) without damaging the pn junction portion. In particular, by forming the protruding electrode on the chip before dividing the semiconductor wafer into chips, it is possible to efficiently provide a semiconductor chip manufacturing method that increases the division yield per semiconductor wafer. Therefore, it can be widely used for a method of manufacturing a chip having a semiconductor element structure other than the semiconductor light emitting element and the light receiving element.

DESCRIPTION OF SYMBOLS 1, 2 ... Light-emitting chip, 3 ... Light-emitting device, 10 ... Substrate, 100 ... Laminated semiconductor layer, 120 ... Intermediate layer, 130 ... Underlayer, 140 ... N-type semiconductor layer, 150 ... Light-emitting layer, 160 ... P-type semiconductor layer , 170 ... first electrode, 180 ... second electrode, 210 ... first protruding electrode, 220 ... second protruding electrode, 315 ... dicing tape, 316 ... wafer ring, 317,318 ... stage, 320 ... blade, 321 ... fragile Area, 345 ... Laser beam, 500 ... Wiring substrate, 511 ... Positive electrode, 512 ... Negative electrode

Claims (7)

A semiconductor element forming step of forming a semiconductor wafer having a semiconductor element formed on the substrate;
A protruding electrode forming step of forming a protruding electrode on the semiconductor wafer, the protruding electrode being connected to an electrode provided on the semiconductor element and having a surface protruding from a surface of the semiconductor element farthest from the substrate;
A fragile region forming step for forming a fragile region in the substrate of the semiconductor wafer as compared with other regions along a predetermined division line provided on the semiconductor wafer;
A dividing step of dividing the semiconductor wafer into a plurality of semiconductor chips by pressing a blade against the substrate of the semiconductor wafer along the planned dividing line from the side opposite to the side where the protruding electrodes are formed of the semiconductor wafer. A method for manufacturing a semiconductor chip including:   2. The method of manufacturing a semiconductor chip according to claim 1, wherein the fragile region formed in the fragile region forming step is formed by a laser beam condensed inside the substrate.   The fragile region formed in the fragile region forming step is formed in a plurality of distances from one surface of the substrate in the substrate along a planned division line of the substrate. A method for manufacturing a semiconductor chip according to claim 1.   4. The semiconductor chip according to claim 1, wherein the protruding electrode formed in the protruding electrode forming step is made of gold (Au) or an alloy containing gold (Au). 5. Production method.   The method for manufacturing a semiconductor chip according to claim 1, wherein the substrate is made of sapphire.   6. The method of manufacturing a semiconductor chip according to claim 1, wherein the semiconductor element is a light emitting element or a light receiving element. A semiconductor element forming step of forming a semiconductor wafer having a semiconductor element formed on the substrate;
A protruding electrode forming step of forming a protruding electrode on the semiconductor wafer, the protruding electrode being connected to an electrode provided on the semiconductor element and having a surface protruding from a surface of the semiconductor element farthest from the substrate;
A fragile region forming step for forming a fragile region in the substrate of the semiconductor wafer as compared with other regions along a predetermined division line provided on the semiconductor wafer;
A dividing step of dividing the semiconductor wafer into a plurality of semiconductor chips by pressing a blade against the substrate of the semiconductor wafer along the planned dividing line from the side opposite to the side where the protruding electrodes are formed of the semiconductor wafer. A method for dividing a semiconductor wafer including:

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