CN112510126B - Deep ultraviolet light emitting diode and manufacturing method thereof - Google Patents

Deep ultraviolet light emitting diode and manufacturing method thereof Download PDF

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Publication number
CN112510126B
CN112510126B CN202011283746.XA CN202011283746A CN112510126B CN 112510126 B CN112510126 B CN 112510126B CN 202011283746 A CN202011283746 A CN 202011283746A CN 112510126 B CN112510126 B CN 112510126B
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layer
semiconductor layer
ohmic contact
emitting diode
deep ultraviolet
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CN112510126A (en
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范伟宏
李东昇
张晓平
马新刚
高默然
赵进超
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Hangzhou Silan Azure Co Ltd
Xiamen Silan Advanced Compound Semiconductor Co Ltd
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Hangzhou Silan Azure Co Ltd
Xiamen Silan Advanced Compound Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
    • H01L33/18—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector

Abstract

The deep ultraviolet light emitting diode comprises an epitaxial layer, wherein the epitaxial layer comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer, the epitaxial layer comprises a first step, one step surface of the first step is the surface of the second semiconductor layer, the side wall of the first step is the side wall of the multi-quantum well layer and the second semiconductor layer, and the other step surface of the first step is the surface of the first semiconductor layer; a first ohmic contact layer contacting the first semiconductor layer; and a second ohmic contact layer contacting the second semiconductor layer. This application is through forming the first step of array distribution in deep ultraviolet emitting diode's epitaxial layer to form the coarsing surface at the lateral wall of first step, increase deep ultraviolet emitting diode's lateral wall area ratio, thereby improve deep ultraviolet emitting diode's light extraction efficiency.

Description

Deep ultraviolet light emitting diode and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductor chips, in particular to a deep ultraviolet light-emitting diode and a manufacturing method thereof.
Background
Deep ultraviolet LED (light emitting diode) applications have seen explosive growth in recent years. The deep ultraviolet has broad-spectrum bactericidal effect on various germs. Airborne pathogenic microorganisms, such as influenza virus (flu), rhinovirus (common cold) and more dangerous pathogens (coronaviruses, etc.), are responsible for many diseases. The deep ultraviolet ray can not only kill bacteria on the surface of an object directly, but also penetrate air and water to kill the bacteria in the object, and the application scene is very wide.
However, deep ultraviolet LED products still face serious problems, and the related art needs to be improved significantly. At present, the quantum efficiency of deep ultraviolet LED products is very low, generally not more than 10%, and the difference is large compared with blue-green LED products, and the reasons mainly include the following points: firstly, the epitaxial quality of the deep ultraviolet LED is not ideal enough, and the defect density is high, so that the internal quantum efficiency is low; secondly, P-GaN is adopted as ohmic contact, so that a serious deep ultraviolet light absorption phenomenon exists; thirdly, as the Al component in the quantum well increases, the deep ultraviolet LED light emission is mainly in a TM-Transverse Magnetic mode (parallel to the light emitting surface), the TM light is difficult to enter an escape cone of the light emitting surface and is emitted out of the LED device, and the TM light extraction efficiency is only one tenth of the TE-Transverse electrical Transverse mode light extraction efficiency. These problems severely restrict the performance improvement of deep ultraviolet LED chips. If the light emitting efficiency of the deep ultraviolet LED product in TM and TE modes can be improved, the performance of the deep ultraviolet LED can be improved.
Disclosure of Invention
In order to solve the above problems, an object of the present invention is to provide a deep ultraviolet light emitting diode and a method for manufacturing the same, in which first steps are formed in an epitaxial layer of the deep ultraviolet light emitting diode in an array, and a roughened surface is formed on sidewalls of the first steps, so that a sidewall area ratio of the deep ultraviolet light emitting diode is increased, thereby improving light extraction efficiency of the deep ultraviolet light emitting diode.
According to an aspect of the present invention, there is provided a deep ultraviolet light emitting diode including: the epitaxial layer comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer, wherein the epitaxial layer comprises a first step, one step surface of the first step is the surface of the second semiconductor layer, the side wall of the first step is the side walls of the multi-quantum well layer and the second semiconductor layer, and the other step surface of the first step is the surface of the first semiconductor layer; a first ohmic contact layer contacting the first semiconductor layer; and a second ohmic contact layer contacting the second semiconductor layer.
Optionally, the sidewall of the first step is a roughened surface.
Optionally, the side wall of the first step is formed with a concave-convex structure.
Optionally, the concave-convex structure is a convex structure or a concave structure.
Optionally, the shape of the convex structure or the concave structure is any one or more of a triangle, a circle, a trapezoid or a regular pattern with convex or concave features.
Optionally, the first step includes a plurality of first steps, and the plurality of first steps are uniformly distributed in an array manner.
Optionally, the first step includes a plurality of mesas formed of the mqw layer and the second semiconductor layer, and the plurality of mesas are spaced apart from each other.
Optionally, the first step includes a via hole penetrating the multiple quantum well layer and the second semiconductor layer, the via holes being separated from each other.
Optionally, the shape of the boss is any one of a circular truncated cone, a regular polygon frustum or other polygon frustums.
Optionally, the shape of the through hole is any one of a circular truncated cone, a regular polygon frustum or other polygon frustums.
Optionally, the first step has a sidewall inclination of 30 ° to 60 °.
Optionally, the area of the MQW layer occupies 50% to 85% of the area of the substrate.
Optionally, the method further comprises: the semiconductor device comprises a buffer layer, an unintentional doping layer and a superlattice layer which are sequentially stacked, wherein a first semiconductor layer is located on the superlattice layer; the buffer layer, the unintentional doping layer, the superlattice layer, the first semiconductor layer, the multiple quantum well and the second semiconductor layer are sequentially stacked on the first substrate from bottom to top.
Optionally, the epitaxial layer includes a second step, an upper step surface of the second step and a lower step surface of the first step are the first semiconductor layer, a sidewall of the second step is a sidewall of the buffer layer, the unintentional doping layer, the superlattice layer and the first semiconductor layer, and a lower step surface of the second step is the first substrate.
Optionally, the method further comprises: and the dielectric layer is positioned on the side wall of the second step, the side wall of the first step, the surfaces of the first semiconductor layer and the second semiconductor layer, and the dielectric layer also covers part of the surface of the substrate.
Optionally, the method further comprises: and the reflector layer covers the first ohmic contact layer, the dielectric layer and part of the surface of the substrate.
Optionally, the method further comprises: and the passivation layer is positioned on the reflector layer and the second ohmic contact layer and comprises through holes respectively exposing the surfaces of the reflector layer and the second ohmic contact layer.
Optionally, the method further comprises: the first electrode is positioned in the through hole of the passivation layer exposing the surface of the reflector layer and the surface of the passivation layer, and the first electrode is an N electrode; and the second electrode is positioned in the through hole of the passivation layer exposing the surface of the second ohmic contact layer and the surface of the passivation layer, and is a P electrode.
Optionally, the method further comprises: a mirror layer on the second ohmic contact layer.
Optionally, the method further comprises: and the dielectric layer is positioned on the surfaces of the first semiconductor layer and the reflector layer and on the side walls of the first step, the second ohmic contact layer and the reflector layer, and the dielectric layer comprises through holes which respectively expose the surfaces of the first ohmic contact layer and the reflector layer.
Optionally, the method further comprises: the first electrode is positioned in the through hole of the dielectric layer exposed on the surface of the first ohmic contact layer and on the surface of the dielectric layer, and the first electrode is an N electrode; and the second electrode is positioned in the through hole of the dielectric layer exposing the surface of the reflector layer and the surface of the dielectric layer, and is a P electrode.
Optionally, the method further comprises: the second substrate is positioned on one side of the second semiconductor layer, and the second ohmic contact layer is positioned between the second semiconductor layer and the second substrate.
Optionally, between the second ohmic contact layer and the second substrate, further comprising: the bonding layer, the dielectric layer and the reflector layer are sequentially stacked from bottom to top; the dielectric layer also covers the side walls of the first step, the second ohmic contact layer and the reflector layer and separates the bonding layer from the epitaxial layer, the second ohmic contact layer and the reflector layer; the bonding layer is in contact with the first ohmic contact layer, the second substrate is electrically connected with the first ohmic contact layer through the bonding layer, the second substrate is a first electrode, and the first electrode is an N electrode.
Optionally, the method further comprises: and the second electrode is positioned in a third step area, the third step penetrates through the first semiconductor layer, the multiple quantum well layer, the second semiconductor layer and the second ohmic contact layer and exposes the surface of the reflector layer, the second electrode is positioned on the surface of the reflector layer, and the second electrode is a P electrode.
Optionally, a surface of one side of the first semiconductor layer, which is far away from the second substrate, is a roughened surface.
Optionally, the method further comprises: a passivation layer covering a surface of the first semiconductor layer and sidewalls of the third step.
Optionally, the dielectric layer is made of a high thermal conductive material.
According to another aspect of the present invention, there is provided a method of manufacturing a deep ultraviolet light emitting diode, including: forming an epitaxial layer on a first substrate, wherein the epitaxial layer sequentially comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer from bottom to top; etching to form a first step in the epitaxial layer, wherein an upper step surface of the first step is the second semiconductor layer, a side wall of the first step is a side wall of the MQW layer and the second semiconductor layer, and a lower step surface of the first step is the first semiconductor layer; forming a first ohmic contact layer on the surface of the first semiconductor layer; and forming a second ohmic contact layer on the surface of the second semiconductor layer.
Optionally, between the steps of forming a first step in the epitaxial layer by etching and forming a first ohmic contact layer on the surface of the first semiconductor layer, the method further includes: and carrying out roughening treatment on the side wall of the first step.
Optionally, the sidewall of the first step is roughened to form a concave-convex structure.
Optionally, the relief structure is a raised structure or a recessed structure.
Optionally, the shape of the protrusions or the depressions in the concave-convex structure is any one or more of a triangle, a circle, a trapezoid, or a regular pattern with protrusions or depressions.
Optionally, the first step includes a plurality of first steps, and the plurality of first steps are uniformly distributed in an array manner.
Optionally, the first step includes a plurality of mesas formed of the mqw layer and the second semiconductor layer, and the plurality of mesas are spaced apart from each other.
Optionally, the first step includes a via hole penetrating the multiple quantum well layer and the second semiconductor layer, the via holes being separated from each other.
Optionally, the shape of the boss is any one of a circular truncated cone, a regular polygon frustum or other polygon frustums.
Optionally, the shape of the through hole is any one of a circular truncated cone, a regular polygon frustum or other polygon frustums.
Optionally, the first step has a sidewall inclination of 30 ° to 60 °.
Optionally, the area of the MQW layer occupies 50% to 85% of the area of the substrate.
Optionally, the epitaxial layer formed on the first substrate further comprises: and sequentially forming a buffer layer, an unintended doping layer and a superlattice layer on the first substrate, wherein the first semiconductor layer is positioned on the superlattice layer.
Optionally, between the steps of forming a first step in the epitaxial layer by etching and forming a first ohmic contact layer on the surface of the first semiconductor layer, the method further includes: etching the epitaxial layer to form a second step, wherein an upper step surface of the second step and a lower step surface of the first step are the first semiconductor layer, a side wall of the second step is the buffer layer, the unintentional doping layer, the superlattice layer and the first semiconductor layer, and the lower step surface of the second step is the first substrate.
Optionally, after the step of forming a second ohmic contact layer on the surface of the second semiconductor layer, the method further includes: and forming a dielectric layer on the side wall of the second step, the side wall of the first step, the surfaces of the first semiconductor layer and the second semiconductor layer, wherein the dielectric layer exposes the first ohmic contact layer and the second ohmic contact layer.
Optionally, after the step of forming the dielectric layer, the method further includes: and forming a reflector layer on the dielectric layer and the first ohmic contact layer, wherein the second ohmic contact layer is exposed out of the reflector layer, and the reflector layer is not in contact with the second ohmic contact layer.
Optionally, after the step of forming a mirror layer on the surfaces of the dielectric layer and the first ohmic contact layer, the method further includes: forming a passivation layer on the surfaces of the reflector layer and the second ohmic contact layer; forming through holes in the passivation layer to expose surfaces of the mirror layer and the second ohmic contact layer, respectively.
Optionally, after the step of forming a via hole in the passivation layer, the method further includes: forming a first electrode and a second electrode on the passivation layer, wherein the first electrode fills a through hole of the passivation layer exposing the surface of the reflector layer, and the first electrode is an N electrode; and the second electrode is filled in the through hole of the passivation layer exposing the surface of the second ohmic contact layer, and is a P electrode.
Optionally, after the step of forming a second ohmic contact layer on the surface of the second semiconductor layer, the method further includes: and forming a reflecting mirror layer on the surface of the second ohmic contact layer.
Optionally, after the step of forming a mirror layer on the surface of the second ohmic contact layer, the method further includes: forming dielectric layers on the surfaces of the first semiconductor layer and the reflector layer and on the side walls of the first step, the second ohmic contact layer and the reflector layer; and forming through holes respectively exposing the surfaces of the first ohmic contact layer and the reflector layer in the dielectric layer.
Optionally, after the step of forming the via hole in the dielectric layer, the method further includes: forming a first electrode and a second electrode on the dielectric layer, wherein the first electrode fills the through hole of the dielectric layer exposed on the surface of the first ohmic contact layer, and the first electrode is an N electrode; the second electrode is filled in the through hole of the dielectric layer exposing the surface of the reflector layer, and the second electrode is a P electrode.
Optionally, after the step of forming a mirror layer on the surface of the second ohmic contact layer, the method further includes: forming dielectric layers on the surfaces of the first semiconductor layer and the reflector layer and on the side walls of the first step, the second ohmic contact layer and the reflector layer; and forming a through hole exposing the surface of the first ohmic contact layer in the dielectric layer.
Optionally, after the step of forming the via hole in the dielectric layer, the method further includes: forming a bonding layer on the surface of the dielectric layer and in the through hole to obtain a first semiconductor structure; forming a bonding layer on the surface of the second substrate to obtain a second semiconductor structure; bonding the first semiconductor structure with the second semiconductor structure; and removing the first substrate, and exposing the surface of the first semiconductor layer, wherein the second substrate is a first electrode which is an N electrode.
Optionally, after the step of removing the first substrate, the method further includes: and roughening the surface of the first semiconductor layer to form a roughened surface.
Optionally, after the step of performing the roughening treatment on the surface of the first semiconductor layer, the method further includes: etching the edge area of the epitaxial layer to form a third step, wherein the third step penetrates through the first semiconductor layer, the multi-quantum well layer, the second semiconductor layer and the second ohmic contact layer and exposes the surface of the reflector layer.
Optionally, after the step of forming the third step, the method further includes: and roughening the surfaces of the first semiconductor layer, the multi-quantum well layer, the second semiconductor layer and the second ohmic contact layer on the side wall of the third step to form a roughened surface.
Optionally, after the step of forming the roughened surface, the method further comprises: and forming a passivation layer on the surface of the first semiconductor layer and the side wall of the third step.
Optionally, after the step of forming a passivation layer on the surface of the first semiconductor layer and the sidewall of the third step, the method further includes: and forming a second electrode on the surface of the reflecting mirror layer, wherein the second electrode is a P electrode.
Optionally, the dielectric layer is made of a high thermal conductive material.
According to the deep ultraviolet light emitting diode and the manufacturing method thereof, the first steps distributed in an array mode are formed in the epitaxial layer of the deep ultraviolet light emitting diode, the roughened surface is formed on the light emitting surface of the side wall of each first step, and the area ratio of the side wall of the deep ultraviolet light emitting diode is increased. Because the light emitting direction of the deep ultraviolet light emitting diode is mainly in the horizontal direction, the light extraction efficiency of the light emitting diode can be obviously improved by increasing the area ratio of the side wall, and the current spreading effect can be improved by the coarsened surface of the side wall of the first step.
Furthermore, the first steps in the deep ultraviolet light-emitting diode are bosses or through holes distributed in an array manner, and the shape of each boss or through hole is any one of a circular truncated cone, a regular polygon terrace with edges or other polygon terrace with edges; the area of the multi-quantum well layer accounts for 50% -85% of the whole substrate area.
In the preferred embodiment, the high heat-conducting medium layer is adopted to replace the traditional medium layer, so that the heat dissipation performance of the deep ultraviolet light-emitting diode is effectively improved, and the reliability of the deep ultraviolet light-emitting diode is improved.
In a preferred embodiment, the deep ultraviolet light emitting diode further adopts a first ohmic contact layer and a second ohmic contact layer with a reflection function, and the first ohmic contact layer and the second ohmic contact layer are combined with the reflector layer, so that the extraction rate of the side wall light of the deep ultraviolet light emitting diode is improved, and the high light extraction rate is finally realized.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1a to 1i are sectional views illustrating stages of a method of manufacturing a deep ultraviolet light emitting diode according to a first embodiment of the present invention;
FIG. 1j shows a top view of FIG. 1c in a first embodiment of the invention;
fig. 2a to 2f are sectional views illustrating stages in a method of manufacturing a deep ultraviolet light emitting diode according to a second embodiment of the present invention;
FIG. 2g shows a top view of FIG. 2b in a second embodiment of the invention;
fig. 3a to 3l are sectional views illustrating stages of a method of manufacturing a deep ultraviolet light emitting diode according to a third embodiment of the present invention;
Figure 3m shows a top view of figure 3b in a third embodiment of the invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly above another layer, another area, the expression "directly above … …" or "above and adjacent to … …" will be used herein.
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.
Fig. 1a to 1i are sectional views illustrating stages of a method of manufacturing a deep ultraviolet light emitting diode according to a first embodiment of the present invention; FIG. 1j shows a top view of FIG. 1c in a first embodiment of the invention.
Referring to fig. 1a, an epitaxial layer 101 is formed on a surface of a first substrate 100.
In this step, an epitaxial growth process such as metal chemical vapor deposition, laser-assisted molecular beam epitaxy, laser sputtering, or hydride vapor phase epitaxy is used to form an epitaxial layer 101 on the surface of the first substrate 100. The epitaxial layer 101 includes, in order from bottom to top in a direction perpendicular to the surface of the first substrate 100, a buffer layer 11, an unintentional doping layer 12, a superlattice layer 13, a first semiconductor layer 14, a multiple quantum well layer 15, and a second semiconductor layer 16.
In this embodiment, the first substrate 100 is, for example, a sapphire substrate. Specifically, the sapphire substrate includes but is not limited to one of a mirror sapphire substrate or a micron/nanometer patterned sapphire substrate, and the preferred embodiment is a nanometer patterned sapphire substrate.
In this embodiment, the epitaxial layer 101 may be a polycrystalline or single crystal structure, and includes one or more of reciprocating continuous progressive LED epitaxial structures composed of AlGaN/AlInGaN and other material systems, and a preferred embodiment thereof is an AlGaN structure containing different Al compositions. In this embodiment, the material of the buffer layer 11 is, for example, AlN, the material of the unintentional doping layer 12 is, for example, AlN, the material of the superlattice layer 13 is, for example, AlN/AlGaN, the material of the first semiconductor layer 14 is, for example, heavily doped n-AlGaN, the material of the multiple quantum well layer 15 is, for example, AlGaN or AlGaInN, the corresponding wavelength range is 200nm to 320nm, the material of the second semiconductor layer 16 is, for example, p-AlGaN, and the total thickness of the epitaxial layer 101 is, for example, 5 to 10 um.
In other embodiments, the first substrate 100 may also be one of a homogeneous or heterogeneous substrate, including GaN, AlN, Ga 2 O 3 SiC, Si, sapphire, ZnO single crystal substrates, and high temperature resistant metal substrates with pre-deposited AlN films, wherein the wafer size is one of 1 inch to 8 inches, and the thickness of the substrates is 300um to 2 mm.
Further, a first step is formed on the epitaxial layer 101, as shown in fig. 1 b.
In this step, the multi quantum well layer 15 and the second semiconductor layer 16 are etched using a photolithography process and a dry etching process to form a first step.
In this embodiment, a part of the multiple quantum well layer 15 and the second semiconductor layer 16 is etched to expose the surface of the first semiconductor layer 14, and the remaining multiple quantum well layer 15 and the second semiconductor layer 16 are separated from each other to form a plurality of truncated pyramids in a regular hexagonal plan view pattern. The first step comprises an upper step surface, a lower step surface and a step side wall, wherein the upper step surface is the surface of the second semiconductor layer 16 in the frustum pyramid, the lower step surface is the surface of the first semiconductor layer 14, the step side wall is the side wall of the multiple quantum well layer 15 and the second semiconductor layer 16, and the step side wall has an inclination angle of 30-60 degrees, preferably 40 degrees.
In this embodiment, the first step is formed, for example, by a mesa composed of the multiple quantum well layer 15 and the second semiconductor layer 16, and the plurality of mesas are separated from each other. The shape of boss can be for example for any one in round platform, regular polygon terrace with edge or other polygon terrace with edge, 2 are no less than to the quantity of first step, and are array evenly distributed. The area of the multi-quantum well layer accounts for 50% -85% of the whole substrate area.
In other embodiments, the first step may also be a via hole penetrating the multiple quantum well layer and the second semiconductor layer, the plurality of via holes being separated from each other.
Further, a roughened surface is formed on the sidewall of the first step, and a portion of the epitaxial layer 101 is removed to form a second step, as shown in fig. 1 c.
In this step, the MESA lithography that patterns the first step is performed, and the uneven pattern lines are designed so as to form an uneven structure on the side wall of the first step, the uneven structure including a convex structure and a concave structure having an uneven surface, thereby increasing the side wall area of the first step, and the uneven structure forming a pattern in the vertical direction on the side wall of the first step. Further, deep trench etching is performed on the epitaxial layer 101 outside the first step by using a photolithography process and a dry etching process to form a second step, thereby exposing the surface of the first substrate 100.
The second step includes a buffer layer 11, an unintentionally doped layer 12, a superlattice layer 13 and a first semiconductor layer 14, and the first step is located on the second step. The upper step surface of the second step is, for example, the surface of the first semiconductor layer 14, the side surfaces of the second step are, for example, the buffer layer 11, the unintentional doping layer 12, the superlattice layer 13, and the sidewalls of the first semiconductor layer 14, and the lower step surface of the second step is the surface of the first substrate 100.
In this embodiment, FIG. 1j is a top view of FIG. 1c, and FIG. 1c is a cross-sectional view taken, for example, along the position indicated by dashed line AA in FIG. 1 j. In fig. 1j, reference numeral 132 denotes an edge of a lower step surface of the first step, a top view shape of the first step is, for example, a regular hexagon, a sidewall of the first step has a concave-convex structure (not shown), reference numeral 131 denotes an edge of the deep trench etching, and an outer side of the edge of the deep trench etching is the first substrate 100. Fig. 1j shows an embodiment having four first steps, the four first steps are located on one second step, in other embodiments, the number of the first steps may also be 2, 6, or 8, and the like, which is not limited in this embodiment, and the plurality of first steps are uniformly distributed in an array.
In this embodiment, the shape of the protrusions or depressions in the concavo-convex structure of the first step sidewall is one or more combinations of a triangle, a circle, a trapezoid, or a regularly designed figure having protrusion or depression features, and the size is between several micrometers and several hundreds of micrometers.
Further, a first ohmic contact layer 102 is formed on the surface of the first semiconductor layer 14, as shown in fig. 1 d.
In this step, a metal material is formed on the surface of the first semiconductor layer 14 outside the first step edge using a photolithography process and an electron beam evaporation process, and nitrogen (N) gas is used 2 ) And rapidly annealing under the conditions of atmosphere and 900 ℃ to form a good N-type ohmic contact. The material of the first ohmic contact layer 102 is, for example, one or more combinations of metal materials such as Cr, Al, Ni, or Au, and the thickness ranges from 100nm to 2 um.
In other embodiments, the material of the first ohmic contact layer 102 is one or more of V, Ti, Cr, Al, Ni, Au, and Pt, and the annealing temperature ranges from 800 to 1100 ℃ and the annealing time ranges from 30s to 2 min. The first ohmic contact layer 102 is, for example, an N-type ohmic contact layer, and the first semiconductor layer 14 is, for example, an N-type semiconductor layer.
Further, a second ohmic contact layer 103 is formed on the surface of the second semiconductor layer 16, as shown in fig. 1 e.
In this step, a second ohmic contact layer 103 is formed on the surface of the second semiconductor layer 16 of the first step using photolithography and electron beam evaporation processes, and O 2 And rapidly annealing under the conditions of atmosphere and 600 ℃ to form a good P-type ohmic contact. The material of the second ohmic contact layer 103 is, for example, NiAu, and the thickness ranges from 0.1nm to 100 nm. Meanwhile, the second ohmic contact layer 103 may reflect a portion of light, having a function of a mirror.
In other embodiments, the material of the second ohmic contact layer 103 may also be one or a combination of ITO, Ni, NiAu, Pd, Rh, and the annealing atmosphere is one of air or oxygen, the annealing temperature ranges from 350 to 700 ℃, and the annealing time ranges from 3 to 10 min. The second ohmic contact layer 103 is, for example, a P-type ohmic contact layer, and the second semiconductor layer 16 is, for example, a P-type semiconductor layer.
Further, a dielectric layer 105 is formed on the surface of the semiconductor structure, as shown in fig. 1 f.
In this step, a dielectric layer 105 is formed on the surface of the semiconductor structure using a Chemical Vapor Deposition (CVD) process. Dielectric layer 105 material such as SiN x 。
After the step of forming the dielectric layer 105, the method further includes removing a portion of the dielectric layer 105 on the surface of the second ohmic contact layer 103 and a portion of the first ohmic contact layer 102 by using photolithography and dry etching processes, so as to expose a portion of the surface of the second ohmic contact layer 103 and a portion of the surface of the first ohmic contact layer 102. At this time, the dielectric layer 105 covers the sidewalls of the first step, the sidewalls of the second step, the surfaces of the first semiconductor layer and the second semiconductor layer.
In other embodiments, the material of the dielectric layer 105 may also be SiO 2 、SiN x 、Al 2 O 3 、AlN、MgF 2 、HfO 2 One or more of the materials are combined, and the thickness range is 30 nm-5 um.
Preferably, the material of the dielectric layer 105 is a high thermal conductive dielectric material, and includes one or more combinations of BN, AlN, BeO or diamond thin film, the thickness of the dielectric layer is 100nm to 5um, and the preparation method thereof is one or more combinations of sputtering, RPD (reactive plasma deposition), and ALD (atomic layer deposition). In the embodiment, the high heat-conducting medium material is adopted, so that the heat dissipation performance of the deep ultraviolet light-emitting diode can be improved, and the reliability of the ultraviolet light-emitting diode is improved.
Further, a mirror layer 104 is formed on the surface of the semiconductor structure, as shown in FIG. 1 g.
In this step, a mirror layer 104 is formed on the dielectric layer 105, the second ohmic contact layer 103, and the surface of the first substrate 100 at the bottom of the second step using a sputtering process. The material of the mirror layer 104 is, for example, AlTiPt.
In this embodiment, a lift-off process is further used to remove the mirror layer 104 on the surface of the second ohmic contact layer 103, so that the surface of the second ohmic contact layer 103 is exposed, and insulation between the second ohmic contact layer 103 and the first ohmic contact layer 102 is ensured.
In other embodiments, the material of the mirror layer 104 may be one or more of Al, Rh, Pt, DBR, ODR, and have a thickness in the range of 100nm-3 um.
Further, a passivation layer 107 is formed on the surface of the semiconductor structure, and a via hole 121 exposing the first ohmic contact layer 102 and the mirror layer 104 is formed, as shown in fig. 1 h.
In this step, a passivation layer 107 is formed on the surface of the semiconductor structure using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. The passivation layer 107 serves to protect the semiconductor structure and is made of a material such as SiO 2 The thickness is, for example, 2000 nm.
A plurality of through holes 121 are formed in the passivation layer 107 using a photolithography process and a dry etching process, and the plurality of through holes 121 expose the surface of the second ohmic contact layer 103 and the surface of the mirror layer 104, respectively.
Further, a first electrode 108 and a second electrode 109 are formed on the passivation layer 107, as shown in fig. 1 i.
In this step, a conductive material is deposited in the plurality of through holes 121 and on the passivation layer 107 using an electron beam evaporation process, and a portion of the conductive material connected to the surface of the passivation layer 107 is stripped off by a stripping process, thereby forming the first electrode 108 and the second electrode 109 spaced apart from each other. In this embodiment, the material of the first electrode 108 and the second electrode 109 is, for example, AuSn. The first electrode 108 is, for example, an N electrode, and the second electrode 109 is, for example, a P electrode.
In this embodiment, the deep ultraviolet light emitting diode is a flip-chip deep ultraviolet light emitting diode, the first steps distributed in an array are formed, and the roughened surface is formed on the side wall of the first steps, so that the area of the side wall of the deep ultraviolet light emitting diode is increased on the premise of not losing the area of a light emitting area, the light extraction efficiency of the side wall of the deep ultraviolet light emitting diode with the horizontal direction as the main light emitting direction is improved, and the roughened surface of the side wall of the first step can also improve the current spreading effect.
Furthermore, the high-heat-conductivity medium material is adopted, so that the heat dissipation capability of the deep ultraviolet light-emitting diode can be effectively improved, and the reliability of the deep ultraviolet light-emitting diode is improved.
Furthermore, the technical scheme of forming the first steps in array distribution and forming the roughened surface on the side wall of the first steps can be used in all forward-mounted, inverted-mounted and vertical structure deep ultraviolet light emitting diode processes, not only can the process complexity be reduced, but also the process compatibility is good, and the problems of low light extraction efficiency and poor heat dissipation performance of the deep ultraviolet light emitting diode can be effectively improved.
Fig. 2a to 2f are sectional views illustrating stages in a method of manufacturing a deep ultraviolet light emitting diode according to a second embodiment of the present invention; fig. 2g shows a top view of fig. 2b in a second embodiment of the invention. In this embodiment, the deep ultraviolet light emitting diode is a flip-through-hole deep ultraviolet light emitting diode.
Referring to fig. 2a, an epitaxial layer 201 is formed on a surface of a first substrate 200.
In this step, an epitaxial layer 201 is formed on the surface of the first substrate 200 by using an epitaxial growth process such as metal chemical vapor deposition, laser-assisted molecular beam epitaxy, laser sputtering, or hydride vapor phase epitaxy. The epitaxial layer 201 includes, in order from bottom to top in a direction perpendicular to the surface of the first substrate 200, a buffer layer 21, an unintentional doping layer 22, a superlattice layer 23, a first semiconductor layer 24, a multiple quantum well layer 25, and a second semiconductor layer 26.
In this embodiment, the first substrate 200 is, for example, a sapphire substrate. Specifically, the sapphire substrate includes but is not limited to one of a mirror sapphire substrate or a micron/nanometer patterned sapphire substrate, and the preferred embodiment is a nanometer patterned sapphire substrate.
In this embodiment, the epitaxial layer 201 may be a polycrystalline or single crystal structure, and includes one or more of reciprocating continuous progressive LED epitaxial structures composed of AlGaN/AlInGaN and other material systems, and a preferred embodiment thereof is an AlGaN structure containing different Al compositions. In this embodiment, the material of the buffer layer 21 is, for example, AlN, the material of the unintentional doping layer 22 is, for example, AlN, the material of the superlattice layer 23 is, for example, AlN/AlGaN, the material of the first semiconductor layer 24 is, for example, heavily doped n-AlGaN, the material of the multiple quantum well layer 25 is, for example, AlGaN or AlGaInN, the corresponding wavelength range is 200nm to 320nm, the material of the second semiconductor layer 26 is, for example, p-AlGaN, and the total thickness of the epitaxial layer 201 is, for example, 5 to 10 um.
In other embodiments, the first substrate 200 may also be one of a homogeneous or heterogeneous substrate, including GaN, AlN, Ga 2 O 3 SiC, Si, sapphire, ZnO single crystal substrates, and high temperature resistant metal substrates with pre-deposited AlN films, wherein the wafer size is one of 1 inch to 8 inches, and the thickness of the substrates is 300um to 2 mm.
Further, a first step is formed in the epitaxial layer 201, and a roughened surface is formed on the sidewall of the first step, as shown in fig. 2 b.
In this step, a region other than the first step is defined by a photolithography process, and etching is performed in the region other than the first step by a dry etching process, i.e., the second semiconductor layer 26 and the multiple quantum well layer 25 are etched to form a plurality of through holes to expose the surface of the first semiconductor layer 24, and the remaining multiple quantum well layer 25 and the second semiconductor layer 26 are connected. The first step includes an upper step surface, a lower step surface and a step side wall, the upper step surface is a surface of the second semiconductor layer 26, the lower step surface is a surface of the first semiconductor layer 24 in the through hole, the step side wall is a side wall of the multiple quantum well layer 25 and the second semiconductor layer 26, and the step side wall has an inclination angle of 30 ° to 60 °, preferably 40 °.
In this embodiment, the first step is formed, for example, by a via hole penetrating the multiple quantum well layer 25 and the second semiconductor layer 26, and the plurality of via holes are separated from each other. The shape of through-hole can be in the round platform, regular polygon terrace with edge or any one in other polygon terrace with edge, and 2 are no less than to the quantity of first step, and are array evenly distributed. The area of the multi-quantum well layer accounts for 50% -85% of the area of the whole substrate.
In other embodiments, the first step is, for example, a mesa composed of the multiple quantum well layer and the second semiconductor layer, and the plurality of mesas are separated from each other.
Referring to fig. 2g, fig. 2b is, for example, a cross-sectional view taken along a position indicated by a broken line BB in fig. 2 g. In fig. 2g, reference numeral 232 denotes an edge of a lower step surface of the first step, a plan view shape of the first step is, for example, a regular hexagon, a sidewall of the first step has a concave-convex structure (not shown in the figure), an outer side of the sidewall edge of the first step is a surface of the second semiconductor layer 26, and peripheral edge portions of the mqw layer 25 and the second semiconductor layer 26 are etched to expose a surface of the first semiconductor layer 24. Fig. 2g shows an embodiment having eight first steps, where the eight first steps are uniformly distributed in an array and have the same size, and in other embodiments, the number of the first steps may also be 3, 5, and the like, which is not limited in this embodiment, and the plurality of first steps are uniformly distributed in an array.
In this embodiment, the first steps are uniformly distributed, and the sidewalls of the first steps are etched to form a concave-convex structure. The rugged structure includes a convex structure and a concave structure, and has a rugged surface, thereby increasing a side wall area of the first step.
In this embodiment, the shape of the protrusions or depressions in the concavo-convex structure of the first step sidewall is one or more combinations of a triangle, a circle, a trapezoid, or a regularly designed figure having protrusion or depression features, and the size is between several micrometers and several hundreds of micrometers.
Further, a first ohmic contact layer 202 is formed on the surface of the first semiconductor layer 24, as shown in fig. 2 c.
In this step, a metal material is deposited on the surface of the first semiconductor layer 24 using a photolithography and Physical Vapor Deposition (PVD) process, thereby forming the first ohmic contact layer 202. In this embodiment, N is also included 2 Annealing is carried out for 30 s-2 min under the condition of atmosphere and 800 ℃ so that the first ohmic contact layer 202 and the first semiconductor layer 24 form good ohmic contact.
In this embodiment, the material of the first ohmic contact layer 202 includes one or a combination of V, Al, Ti, or Au. The thickness of the first ohmic contact layer 202 was 500 nm. The first ohmic contact layer 202 is, for example, an N-type ohmic contact layer, and the first semiconductor layer 24 is, for example, an N-type semiconductor layer.
Further, a second ohmic contact layer 203 and a mirror layer 204 are sequentially formed on the surface of the second semiconductor layer 26, as shown in fig. 2 d.
In this step, a second ohmic contact layer 203 and a mirror layer 204 are formed on the surface of the second semiconductor layer 26 using photolithography, wet etching, and sputtering processes. In this embodiment, the material of the second ohmic contact layer 203 is NiAu with a thickness of 60nm, and the material of the mirror layer 204 is TiPtAu with a thickness of 600nm, for example. The second ohmic contact layer 203 is, for example, a P-type ohmic contact layer, and the second semiconductor layer 26 is, for example, a P-type semiconductor layer.
In this embodiment, the second ohmic contact layer 203 and the mirror layer 204 after formation are only on the surface of the second semiconductor layer 26, and the first ohmic contact layer 202 is exposed.
Further, a dielectric layer 205 is formed on the surface of the semiconductor structure, and a via hole exposing the first ohmic contact layer 202 is formed in the dielectric layer 205, as shown in fig. 2 e.
In this step, a dielectric layer 205 is formed on the surface of the semiconductor structure by a sputtering process, and then a plurality of through holes are formed in the dielectric layer 205 by a photolithography and dry etching process, wherein a portion of the through holes expose the first ohmic contact layer 202 and a portion of the through holes expose the mirror layer 204.
In this embodiment, the material of the dielectric layer 205 is, for example, highly thermally conductive BN with a thickness of 500 nm.
Further, a first electrode 208 and a second electrode 209 are formed on the dielectric layer 205, as shown in fig. 2 f.
In this step, an electrode layer is formed in the plurality of through holes and on the dielectric layer 205 by a sputtering process, and a material of the electrode layer is, for example, a conductive metal. In this embodiment, the electrode layer fills the via hole where the first ohmic contact layer 202 is located and the via hole exposing the mirror layer 204.
In this embodiment, the method further comprises removing a portion of the electrode layer on the dielectric layer 205 by photolithography and lift-off processes to separate the electrode layer into a first electrode 208 connected to the first ohmic contact layer 102 and a second electrode 209 connected to the mirror layer 204.
In this embodiment, the first electrode 208 is, for example, an N electrode, and the second electrode 209 is, for example, a P electrode.
In this embodiment, the deep ultraviolet light emitting diode is a flip-chip through hole deep ultraviolet light emitting diode, the first steps distributed in an array are formed, and the roughened surface is formed on the side wall of the first steps, so that the area of the side wall of the deep ultraviolet light emitting diode is increased on the premise of not losing the area of a light emitting area, the light extraction efficiency of the side wall of the deep ultraviolet light emitting diode with the horizontal direction as the main light emitting direction is improved, and the roughened surface of the side wall of the first step can also improve the current expansion effect.
Furthermore, the high-heat-conductivity medium material is adopted, so that the heat dissipation capability of the deep ultraviolet light-emitting diode can be effectively improved, and the reliability of the deep ultraviolet light-emitting diode is improved.
Furthermore, the technical scheme of forming the first steps in array distribution and forming the roughened surface on the side wall of the first steps can be used in all forward-mounted, inverted-mounted and vertical structure deep ultraviolet light emitting diode processes, not only can the process complexity be reduced, but also the process compatibility is good, and the problems of low light extraction efficiency and poor heat dissipation performance of the deep ultraviolet light emitting diode can be effectively improved.
Fig. 3a to 3l are sectional views illustrating stages of a method of manufacturing a deep ultraviolet light emitting diode according to a third embodiment of the present invention; figure 3m shows a top view of figure 3b in a third embodiment of the invention. In this embodiment, the deep ultraviolet light emitting diode is a vertical through hole deep ultraviolet light emitting diode.
Referring to fig. 3a, an epitaxial layer 301 is sequentially formed on a surface of a first substrate 300.
In this step, an epitaxial growth process such as metal chemical vapor deposition, laser-assisted molecular beam epitaxy, laser sputtering, or hydride vapor phase epitaxy is used to form an epitaxial layer 301 on the surface of the first substrate 300. The epitaxial layer 301 includes, in order from bottom to top in a direction perpendicular to the surface of the first substrate 300, a buffer layer 31, an unintentional doping layer 32, a superlattice layer 33, a first semiconductor layer 34, a multiple quantum well layer 35, and a second semiconductor layer 36.
In this embodiment, the first substrate 300 is, for example, a sapphire substrate. Specifically, the sapphire substrate includes but is not limited to one of a mirror sapphire substrate or a micro/nano patterned sapphire substrate, and the preferred embodiment is a mirror sapphire substrate.
In this embodiment, the epitaxial layer 301 may be a polycrystalline or single crystal structure, and includes one or more of reciprocating continuous progressive LED epitaxial structures composed of AlGaN/AlInGaN and other material systems, and a preferred embodiment thereof is an AlGaN structure containing different Al compositions. In this embodiment, the material of the buffer layer 31 is, for example, AlN, the material of the unintentional doping layer 32 is, for example, AlN, the material of the superlattice layer 33 is, for example, AlN/AlGaN, the material of the first semiconductor layer 34 is, for example, heavily doped n-AlGaN, the material of the multiple quantum well layer 35 is, for example, AlGaN or AlGaInN, the corresponding wavelength range is 200nm to 320nm, the material of the second semiconductor layer 36 is, for example, p-AlGaN, and the total thickness of the epitaxial layer 301 is, for example, 5 to 10 um.
Further, a first step is formed in the epitaxial layer 301, and a roughened surface is formed at the sidewall of the first step, as shown in fig. 3 b.
In this step, photolithography and dry etching processes are used to form first steps in the epitaxial layer 301 in a uniform array distribution. After etching the epitaxial layer 301 to form a plurality of through holes, the surface of the first semiconductor layer 34 is exposed. Specifically, the second semiconductor layer 36 and the multiple quantum well layer 35 are etched to form a plurality of through holes, and the remaining multiple quantum well layer 35 and the second semiconductor layer 36 communicate. In this embodiment, the first step includes an upper step surface which is an upper surface of the second semiconductor layer 36, a lower step surface which is a surface of the first semiconductor layer 34 in the through hole, and a step sidewall which is a sidewall of the multiple quantum well layer 35 and the second semiconductor layer 36, and has a tilt angle of 30 ° to 60 °, preferably 40 °.
In this embodiment, the first step is formed, for example, by a via hole penetrating the multiple quantum well layer 35 and the second semiconductor layer 36, and the plurality of via holes are separated from each other. The shape of through-hole can be in the round platform, regular polygon terrace with edge or any one in other polygon terrace with edge, and 2 are no less than to the quantity of first step, and are array evenly distributed. The area of the multi-quantum well layer accounts for 50% -85% of the whole substrate area.
In other embodiments, the first step is, for example, a mesa composed of the multiple quantum well layer and the second semiconductor layer, and the plurality of mesas are separated from each other.
Referring to fig. 3m, fig. 3b is a cross-sectional view taken, for example, along the position indicated by the dashed line CC in fig. 3 m. In fig. 3m, reference numeral 332 denotes an edge of a lower step surface of the first step, a top view shape of the first step is, for example, a regular hexagon, a sidewall of the first step has a concave-convex structure (not shown), and an outer side of the sidewall edge of the first step is the second semiconductor layer 36. Fig. 3m shows an embodiment having nine first steps, the nine first steps are uniformly distributed in an array, and have the same size, in other embodiments, the number of the first steps may also be 4, 6, and the like, which is not limited in this embodiment, and the plurality of first steps are uniformly distributed in an array.
In this embodiment, the first steps are uniformly distributed, and the sidewalls of the first steps are etched to form a concave-convex structure. The rugged structure includes a convex structure and a concave structure, and has a rugged surface, thereby increasing a side wall area of the first step.
In this embodiment, the shape of the protrusions or depressions in the concavo-convex structure of the first step sidewall is one or more combinations of a triangle, a circle, a trapezoid, or a regularly designed figure having protrusion or depression features, and the size is between several micrometers and several hundreds of micrometers.
Further, a first ohmic contact layer 302 is formed on the surface of the first semiconductor layer 34, as shown in fig. 3 c.
In this embodiment, the first ohmic contact layer 302 is formed on the surface of the first semiconductor layer 34 by, for example, photolithography and physical vapor deposition processes, and the first ohmic contact layer 302 is rapidly annealed for 30s to 2min under a nitrogen atmosphere and at 800 ℃ to form a good ohmic contact with the first semiconductor layer 34.
In this embodiment, the material of the first ohmic contact layer 302 includes one or a combination of V, Al, Ti, or Au. The thickness of the first ohmic contact layer 302 is 500 nm. The first ohmic contact layer 302 is, for example, an N-type ohmic contact layer, and the first semiconductor layer 34 is, for example, an N-type semiconductor layer.
Further, a second ohmic contact layer 303 and a mirror layer 304 are sequentially formed on the surface of the second semiconductor layer 36, as shown in fig. 3 d.
In this step, a second ohmic contact layer 303 and a mirror layer 304 are formed on the surface of the second semiconductor layer 36 using photolithography, wet etching, and sputtering processes. In this embodiment, the material of the second ohmic contact layer 303 is NiAl and has a thickness of 120nm, and the material of the mirror layer 304 is TiPtAu, for example, and has a thickness of 200 nm. The second ohmic contact layer 303 is, for example, a P-type ohmic contact layer, and the second semiconductor layer 36 is, for example, a P-type semiconductor layer.
In this embodiment, the second ohmic contact layer 303 and the mirror layer 304 after formation are only on the surface of the second semiconductor layer 36, and the first ohmic contact layer 302 is exposed.
Further, a dielectric layer 305 is formed on the surface of the semiconductor structure, and the dielectric layer 305 on the surface of the first ohmic contact layer 302 is removed, as shown in fig. 3 e.
In this step, a dielectric layer 305 is formed on the surface of the semiconductor structure using an ALD atomic layer deposition process, and the dielectric layer 305 on the surface of the first ohmic contact layer 302 is removed using a photolithography and dry etching process. In this embodiment, after removing the dielectric layer 305 on the surface of the first ohmic contact layer 302, the remaining dielectric layer 305 is located on the surface of the mirror layer 304, the sidewall of the first step, the mirror layer 304 and the sidewall of the second ohmic contact layer 303, and the dielectric layer 305 is used to isolate the first ohmic contact layer 302 from the mqw layer 35, the second semiconductor layer 36, the second ohmic contact layer 303 and the mirror layer 304.
In this embodiment, the dielectric layer 305 is made of a high thermal conductivity dielectric material, such as AlN, and has a thickness of, for example, 500 nm.
Further, a bonding layer 306 is formed on the surface of the semiconductor structure, resulting in a first semiconductor structure, as shown in fig. 3 f.
In this step, a sputtering process is used to form a bonding layer 306 on the surface of the semiconductor structure, where the bonding layer 306 is, for example, a Cu/Sn binary metal bonding layer, specifically, the bonding layer 306 is, for example, a bonding layer formed by a pair of Au and Sn binary metal layers, and the thickness of each metal layer in the bonding layer 306 is, for example, 1um for the Cu metal layer and 200nm for the Sn metal layer.
In this embodiment, before forming the bonding layer 306, an adhesion layer (not shown in the figure) may be further formed on the semiconductor surface, and the adhesion layer is located between the bonding layer 306 and the semiconductor structure for adhering the semiconductor structure and the bonding layer 306. The material of the adhesion layer is, for example, Ti and the thickness is, for example, 200 nm.
Further, an adhesion layer (not shown in the figure) and a bonding layer 306 are formed on the second substrate 310, resulting in a second semiconductor structure, and the first semiconductor structure is bonded to the second semiconductor structure, as shown in fig. 3 g.
In this embodiment, the material of the adhesion layer (not shown) formed on the second substrate 310 is, for example, Ti, and the thickness is, for example, 200 nm. The bonding layer 306 is, for example, a Cu/Sn binary metal bonding layer, specifically, the bonding layer 306 is, for example, a bonding layer formed by a pair of Cu and Sn binary metal layers, and the thickness of each metal layer in the bonding layer 306 is, for example, 1um of the Cu metal layer and 200nm of the Sn metal layer.
In this embodiment, the second substrate 310 is, for example, a CuW substrate, and the thickness of the second substrate 310 is, for example, 400 um. And the first semiconductor structure and the second semiconductor structure are bonded by adopting a CuSn liquid phase transient bonding process at the temperature of 260 ℃.
In this embodiment, the second substrate 310 is a first electrode, which is an N-electrode.
Further, the first substrate 300 and part of the epitaxial layer 301 are removed, as shown in fig. 3 h.
In this step, the separation of the first substrate 300, the buffer layer 31, the unintentional doping layer 32, and the superlattice layer 33 from other parts is achieved by, for example, peeling and decomposing the superlattice layer 33 using a small ultraviolet laser spot having a wavelength of 266nm and an area of 50 um.
In this embodiment, the surface of the first semiconductor layer 34 exposed after peeling off the superlattice layer 33 is treated with dilute hydrochloric acid.
Further, the surface of the first semiconductor layer 34 is roughened as shown in fig. 3 i.
In this step, for example, a KOH solution with a concentration of 6mol/L is used to process the surface of the first semiconductor layer 34 at 70 ℃ to form a roughened surface, so that the secondary micro-nano structure is used to increase the light emission of the deep ultraviolet light emitting diode.
Further, a third step is formed on the surface of the first semiconductor layer 34, and a roughened surface is formed on the sidewall of the third step, as shown in fig. 3 j.
In this step, portions of the first semiconductor layer 34, the multiple quantum well 35, the second semiconductor layer 36, and the second ohmic contact layer 303 at the edges of the semiconductor structure are removed using photolithography and dry etching processes, exposing the surface of the mirror layer 304, thereby forming a third step in the semiconductor structure. In this embodiment, the width of the lower step face region of the third step is, for example, 100 um.
In this embodiment, the third step includes the first semiconductor layer 34, the multiple quantum well layer 35, the second semiconductor layer 36, and the second ohmic contact layer 303. The upper step surface of the third step is the surface of the first semiconductor layer 34 subjected to the roughening treatment, the step side walls are the side walls of the first semiconductor layer 34, the multiple quantum well layer 35, the second semiconductor layer 36 and the second ohmic contact layer 303, and the lower step surface is the surface of the mirror layer 304.
In this embodiment, the method further includes forming a concave-convex structure on the sidewall of the third step by using an etching process, where the concave-convex structure includes a convex structure and a concave structure, and has a concave-convex surface, thereby increasing the sidewall area of the first step.
In this embodiment, the shape of the protrusions or depressions in the concavo-convex structure of the first step sidewall is one or more combinations of a triangle, a circle, a trapezoid, or a regularly designed figure having protrusion or depression features, and the size is between several micrometers and several hundreds of micrometers.
Further, a passivation layer 307 is formed on the surface of the semiconductor structure, as shown in fig. 3 k.
In this step, a passivation layer 307 is formed on the surface of the semiconductor structure using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, and the passivation layer 307 on the surface of the mirror layer 304 is removed using a photolithography and dry etching process, with the remaining passivation layer 307 being located on the sidewall of the third step and the surface of the first semiconductor layer 34.
In this embodiment, the material of the passivation layer 307 is SiO 2 And the thickness is 200 nm.
Further, a second electrode 309 is formed on the surface of the mirror layer 304 in the step region, as shown in fig. 3 l.
In this step, a second electrode 309 is formed on the surface of the mirror layer 304 using photolithography, wet etching, and electron beam evaporation techniques. The material of the second electrode 309 is, for example, CrPtAu. The second electrode 309 is, for example, a P electrode.
In this embodiment, the deep ultraviolet light emitting diode is a deep ultraviolet light emitting diode with a vertical through hole, the first steps distributed in an array are formed, and the roughened surfaces are formed on the side walls of the first steps and the third steps, so that the side wall area of the deep ultraviolet light emitting diode is increased on the premise of not losing the area of a light emitting area, the side wall light extraction efficiency of the deep ultraviolet light emitting diode with the horizontal direction as the main light emitting direction is improved, and the current spreading effect can be improved by the roughened surface of the side wall of the first step.
Furthermore, the high-heat-conductivity medium material is adopted, so that the heat dissipation capability of the deep ultraviolet light-emitting diode can be effectively improved, and the reliability of the deep ultraviolet light-emitting diode is improved.
Furthermore, the technical scheme of forming the first steps in array distribution and forming the roughened surface on the side wall of the first steps can be used in all forward-mounted, inverted-mounted and vertical structure deep ultraviolet light emitting diode processes, not only can the process complexity be reduced, but also the process compatibility is good, and the problems of low light extraction efficiency and poor heat dissipation performance of the deep ultraviolet light emitting diode can be effectively improved.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims (37)

1. A deep ultraviolet light emitting diode comprising:
the epitaxial layer comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer, wherein the epitaxial layer comprises a first step, one step surface of the first step is the surface of the second semiconductor layer, the side wall of the first step is the side walls of the multi-quantum well layer and the second semiconductor layer, and the other step surface of the first step is the surface of the first semiconductor layer;
a first ohmic contact layer contacting the first semiconductor layer;
a second ohmic contact layer in contact with the second semiconductor layer;
a mirror layer on the second ohmic contact layer;
a bonding layer in contact with the first ohmic contact layer;
the dielectric layer covers the side walls of the first step, the second ohmic contact layer and the reflector layer and separates the bonding layer from the epitaxial layer, the second ohmic contact layer and the reflector layer;
and the side wall of the third step comprises the side walls of the first semiconductor layer, the multiple quantum well layer, the second semiconductor layer and the second ohmic contact layer, the side wall of the third step is a light emergent surface, and the third step is used for increasing the light emergent efficiency.
2. The deep ultraviolet light emitting diode of claim 1, wherein the sidewalls of the first step are roughened surfaces.
3. The deep ultraviolet light emitting diode of claim 2, wherein the sidewall of the first step is formed with a relief structure.
4. The deep ultraviolet light emitting diode of claim 3, wherein the relief structure is a raised structure or a recessed structure.
5. The deep ultraviolet light emitting diode of claim 4, wherein the shape of the protruding structures or the recessed structures is any one or more of a triangle, a circle, a trapezoid, or a regular pattern with protruding or recessed features.
6. The deep ultraviolet light emitting diode of claim 1, wherein the first step comprises a plurality of first steps, and the plurality of first steps are uniformly distributed in an array manner.
7. The deep ultraviolet light emitting diode of claim 6, wherein the first step comprises a mesa of the MQW layer and the second semiconductor layer, the plurality of mesas being spaced apart from each other.
8. The deep ultraviolet light emitting diode of claim 6, wherein the first step comprises a via hole penetrating the MQW layer and the second semiconductor layer, the via holes being separated from each other.
9. The deep ultraviolet light emitting diode of claim 7, wherein the boss is in the shape of any one of a circular truncated cone, a regular polygonal frustum, or other polygonal frustum.
10. The deep ultraviolet light emitting diode of claim 8, wherein the through hole is in the shape of any one of a truncated cone, a regular polygonal frustum, or other polygonal frustum.
11. The deep ultraviolet light emitting diode of claim 1, wherein the sidewall inclination angle of the first step is 30 ° to 60 °.
12. The deep ultraviolet light emitting diode of claim 1, wherein the multiple quantum well layer comprises 50% to 85% of the area of the substrate.
13. The deep ultraviolet light emitting diode of claim 1, further comprising:
the second substrate is positioned on one side of the second semiconductor layer, and the second ohmic contact layer is positioned between the second semiconductor layer and the second substrate.
14. The deep ultraviolet light emitting diode of claim 13, wherein the second substrate is electrically connected to the first ohmic contact layer through the bonding layer, the second substrate is a first electrode, and the first electrode is an N-electrode.
15. The deep ultraviolet light emitting diode of claim 14, further comprising:
and the second electrode is positioned in a third step area, the third step penetrates through the first semiconductor layer, the multiple quantum well layer, the second semiconductor layer and the second ohmic contact layer and exposes the surface of the reflector layer, the second electrode is positioned on the surface of the reflector layer, and the second electrode is a P electrode.
16. The deep ultraviolet light emitting diode of claim 13, wherein a surface of the first semiconductor layer on a side away from the second substrate is roughened.
17. The deep ultraviolet light emitting diode of claim 15, further comprising:
a passivation layer covering a surface of the first semiconductor layer and a sidewall of the third step.
18. The deep ultraviolet light emitting diode of claim 1, wherein the dielectric layer is made of a high thermal conductivity material.
19. A method for manufacturing a deep ultraviolet light emitting diode comprises the following steps:
forming an epitaxial layer on a first substrate, wherein the epitaxial layer sequentially comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer from bottom to top;
etching to form a first step in the epitaxial layer, wherein an upper step surface of the first step is the second semiconductor layer, a side wall of the first step is a side wall of the MQW layer and the second semiconductor layer, and a lower step surface of the first step is the first semiconductor layer;
Forming a first ohmic contact layer on the surface of the first semiconductor layer; and
forming a second ohmic contact layer on the surface of the second semiconductor layer;
forming a mirror layer on the surface of the second ohmic contact layer;
forming dielectric layers on the surfaces of the first semiconductor layer and the reflector layer and on the side walls of the first step, the second ohmic contact layer and the reflector layer;
forming a through hole exposing the surface of the first ohmic contact layer in the dielectric layer;
forming a bonding layer on the surface of the dielectric layer and in the through hole to obtain a first semiconductor structure;
and forming a third step, wherein the third step penetrates through the first semiconductor layer, the multiple quantum well layer, the second semiconductor layer and the second ohmic contact layer and exposes the surface of the reflector layer, the side wall of the third step comprises the side walls of the first semiconductor layer, the multiple quantum well layer, the second semiconductor layer and the second ohmic contact layer, the side wall of the third step is a light emergent surface, and the third step is used for increasing the light emergent efficiency.
20. The method of manufacturing of claim 19, wherein, between the steps of etching a first step in the epitaxial layer and forming a first ohmic contact layer on the first semiconductor layer surface, further comprising:
And carrying out roughening treatment on the side wall of the first step.
21. The manufacturing method according to claim 20, wherein the side wall of the first step is roughened to form a textured structure.
22. The manufacturing method according to claim 21, wherein the concave-convex structure is a convex structure or a concave structure.
23. The manufacturing method according to claim 22, wherein the shape of the projections or depressions in the concavo-convex structure is any one or more of a triangle, a circle, a trapezoid, or a regular pattern having the features of projections or depressions.
24. The manufacturing method according to claim 19, wherein the first step includes a plurality of first steps, and the plurality of first steps are uniformly distributed in an array.
25. The manufacturing method according to claim 24, wherein the first step includes a mesa composed of the mqw layer and the second semiconductor layer, and a plurality of the mesas are separated from each other.
26. The manufacturing method according to claim 24, wherein the first step includes a via hole penetrating the mqw layer and the second semiconductor layer, the via holes being separated from each other.
27. The manufacturing method according to claim 25, wherein the shape of the boss is any one of a circular truncated cone, a regular polygonal frustum, or another polygonal frustum.
28. The manufacturing method according to claim 26, wherein the shape of the through-hole is any one of a circular truncated cone, a regular polygonal frustum, or another polygonal frustum.
29. The method of manufacturing of claim 19, wherein the sidewall slope angle of the first step is 30 ° to 60 °.
30. The manufacturing method according to claim 19, wherein an area of the mqw layer occupies 50 to 85% of an area of the substrate.
31. The method of manufacturing of claim 19, wherein after the step of forming a bonding layer on the surface of the dielectric layer and in the via resulting in the first semiconductor structure, further comprising:
forming a bonding layer on the surface of the second substrate to obtain a second semiconductor structure;
bonding the first semiconductor structure with the second semiconductor structure;
removing the first substrate to expose the surface of the first semiconductor layer,
the second substrate is a first electrode, and the first electrode is an N electrode.
32. The manufacturing method according to claim 31, further comprising, after the step of removing the first substrate:
and roughening the surface of the first semiconductor layer to form a roughened surface.
33. The manufacturing method according to claim 32, further comprising, after the step of roughening the surface of the first semiconductor layer:
and etching the edge area of the epitaxial layer to form a third step.
34. The manufacturing method according to claim 33, further comprising, after the step of forming the third step:
and roughening the surfaces of the first semiconductor layer, the multi-quantum well layer, the second semiconductor layer and the second ohmic contact layer on the side wall of the third step to form a roughened surface.
35. The manufacturing method according to claim 34, further comprising, after the step of forming a roughened surface:
and forming a passivation layer on the surface of the first semiconductor layer and the side wall of the third step.
36. The manufacturing method according to claim 35, further comprising, after the step of forming a passivation layer on the surface of the first semiconductor layer and the sidewall of the third step:
and forming a second electrode on the surface of the reflecting mirror layer, wherein the second electrode is a P electrode.
37. The manufacturing method of claim 19, wherein the material of the dielectric layer is a highly thermally conductive material.
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