CN113964249A - Light emitting diode and method for manufacturing the same - Google Patents
Light emitting diode and method for manufacturing the same Download PDFInfo
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- CN113964249A CN113964249A CN202111079333.4A CN202111079333A CN113964249A CN 113964249 A CN113964249 A CN 113964249A CN 202111079333 A CN202111079333 A CN 202111079333A CN 113964249 A CN113964249 A CN 113964249A
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- 229910002601 GaN Inorganic materials 0.000 description 32
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- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 20
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/24—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/16—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
- H01L33/18—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
Abstract
The application discloses a light emitting diode and a manufacturing method thereof, the light emitting diode includes: the epitaxial layer comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially positioned on the surface of the substrate; the patterned steps are located on the periphery of the epitaxial layer, the side walls of the patterned steps are roughened surfaces, and the crystal directions of at least one group of opposite sides in the side walls of the patterned steps are parallel to the [1010] crystal direction of the material of the epitaxial layer. The light-emitting diode provided by the application obtains a roughened surface by forming the patterned step in the preparation process and then roughening the side wall of the patterned step, wherein the set crystal orientation of the epitaxial layer material at the side wall of the patterned step is combined with a wet etching technology, so that the lateral light-emitting of the light-emitting diode can be improved to a greater extent, and further the internal quantum efficiency, the light extraction efficiency and the light-emitting morphology of the light-emitting diode are improved.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a light emitting diode and a manufacturing method thereof.
Background
With the continuous development of display technology, LED backlight technology is becoming the mainstream technology of backlight of liquid crystal display devices. With the pursuit of higher contrast and higher color gamut of display devices, the mini LED backlight technology is gaining favor in the industry. At present, a high-resolution display device usually adopts a complex light uniform diffusion technical means, and a mini LED chip used as a backlight source is required to have higher brightness so as to overcome the problem of brightness reduction caused by the complex light uniform technology.
For the mini LED, the proportion of the chip edge area to the total chip area is obviously increased compared with the common small-size LED chip, so that the light emission of the mini LED edge area also becomes an important component of the light emission intensity. Therefore, in addition to using a mirror to improve the light extraction efficiency of forward light emission, the light extraction efficiency of the chip edge region also needs to be emphasized. In a relatively large-sized mini LED chip product, edge graphical design and dry etching can be adopted to form an inclination angle so as to increase edge light extraction and improve the brightness of the chip, but for the relatively small-sized mini LED chip product, the photoelectric efficiency of the LED chip can be seriously influenced by the increase of the area of the edge area or the surface recombination effect generated by the damage of the dry etching.
Disclosure of Invention
The invention aims to provide a light-emitting diode and a manufacturing method thereof, which improve the light-emitting diode edge light-emitting and reduce the influence of surface recombination of an epitaxial layer material on the internal quantum efficiency of the light-emitting diode, thereby improving the internal quantum efficiency, the light extraction efficiency and the light-emitting appearance of the light-emitting diode.
According to an aspect of the present application, there is provided a light emitting diode including:
the epitaxial layer comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially positioned on the surface of the substrate;
a patterned step positioned around the epitaxial layer, the side wall of the patterned step being a roughened surface,
wherein at least one pair of opposite sides of the sidewall of the patterned step has a crystal orientation with respect to the epitaxial layer
The crystal directions are parallel.
Optionally, the sidewall with the roughened surface is randomly interspersed with a plurality of triangular prisms.
Optionally, the patterned step penetrates through the second semiconductor layer and the light emitting layer and exposes the surface of the first semiconductor layer.
Optionally, the top view pattern of the patterned step is a symmetrical pattern, and the symmetrical pattern includes one or more patterns of a rectangle, a square, a diamond, or a hexagon.
Optionally, the top view of the patterned step is diamond or hexagon, and the crystal orientation of the remaining edge in the sidewall of the step is same as that of the material of the epitaxial layer
The crystal orientation forms an included angle of 120 °.
Optionally, the top view of the patterned step is rectangular, and the crystal orientation of the long side of the sidewall of the step and the material of the epitaxial layer
The crystal directions are parallel, and the short edge in the side wall of the step is a broken line with an angle.
Optionally, the top view of the patterned step is square, and the remaining edges of the sidewall of the step are angular broken lines.
Optionally, the fold lines are mutually included at an angle of 120 degrees, and the fold lines and the material of the epitaxial layer
The crystal orientation forms an included angle of 120 °.
Optionally, the method further comprises:
the through hole sequentially penetrates through the second semiconductor layer and the light emitting layer and exposes out of the surface of the first semiconductor layer;
a first ohmic contact layer on the surface of the first semiconductor layer in the through hole;
the reflecting mirror layer is positioned on the surface of the second semiconductor layer, and the metal barrier layer is positioned on the surface of the reflecting mirror layer, and the reflecting mirror layer and the metal barrier layer expose the through hole and the step;
the dielectric layer is positioned on the surface of the metal barrier layer, in the patterned step and the through hole and provided with a first opening exposing the first ohmic contact layer and a second opening exposing part of the surface of the metal barrier layer; and
a first electrode in the first opening and a part of the surface of the dielectric layer, and a second electrode in the second opening and a part of the surface of the dielectric layer,
and the first electrode and the second electrode positioned on the surface of the dielectric layer are not contacted.
Optionally, the method further comprises:
the first ohmic contact layer is positioned on the surface of the first semiconductor layer at the bottom of the patterned step;
the reflecting mirror layer is positioned on the surface of the second semiconductor layer, and the metal barrier layer is positioned on the surface of the reflecting mirror layer, and the steps are exposed by the reflecting mirror layer and the metal barrier layer;
the dielectric layer is positioned on the surface of the metal barrier layer and in the patterned step and is provided with a first opening exposing the surface of part of the first ohmic contact layer and a second opening exposing the surface of part of the metal barrier layer; and
a first electrode in the first opening and a part of the surface of the dielectric layer, and a second electrode in the second opening and a part of the surface of the dielectric layer,
and the first electrode and the second electrode positioned on the surface of the dielectric layer are not contacted.
Optionally, the light emitting diode is a mini LED chip.
According to another aspect of the present application, there is provided a method of manufacturing a light emitting diode, including:
forming an epitaxial layer on a substrate, wherein the epitaxial layer comprises a first semiconductor layer, a light-emitting layer and a second semiconductor layer which are sequentially positioned on the surface of the substrate;
forming a patterned step by downward dry etching along the surface of the second semiconductor layer; and
roughening the side wall of the patterned step to form a roughened surface,
wherein at least one pair of opposite sides of the sidewall of the patterned step has a crystal orientation with respect to the epitaxial layer
The crystal directions are parallel.
Optionally, the sidewall with the roughened surface is randomly interspersed with a plurality of triangular prisms.
Optionally, the step of roughening the sidewall of the patterned step to form a roughened surface includes:
and chemically etching the side wall of the patterned step by adopting a first solution.
Optionally, the method further comprises:
and when the side wall of the patterned step is chemically etched by adopting a first solution, removing the oxide layer on the surface of the second semiconductor layer and the dry etching damage layer on the surface of the side wall of the patterned step by adopting the first solution for chemical etching.
Optionally, the first solution is an alkaline solution with a concentration of no more than 20%, and the first solution is one of potassium hydroxide, sodium hydroxide and tetramethylammonium hydroxide.
Optionally, in the process of chemically etching the sidewall of the patterned step with a first solution, the first solution is heated at a temperature of 30 ℃ to 150 ℃.
Optionally, the time for chemically etching the sidewall of the patterned step with the first solution is 5 to 60 minutes.
Optionally, the step of forming a patterned step by dry etching downward along the surface of the second semiconductor layer includes:
and photoetching and dry etching the second semiconductor layer and the light emitting layer to reach the surface of the first semiconductor layer to form a patterned step, wherein the patterned step is positioned on the periphery of the epitaxial layer.
Optionally, the step of forming a patterned step by dry etching downward along the surface of the second semiconductor layer further includes:
etching the crystal direction of the opposite side of the side wall of the step perpendicular to the reference crystal direction into the material of the epitaxial layer
The crystal directions are parallel.
Optionally, the top view pattern of the patterned step is a symmetrical pattern, and the symmetrical pattern includes one or more patterns of a rectangle, a square, a diamond, or a hexagon.
Optionally, the top view of the patterned step is diamond or hexagon, and the crystal orientation of the remaining edge in the sidewall of the step is etched to be equal to that of the material of the epitaxial layer
The crystal orientation forms an included angle of 120 °.
Optionally, the overlook pattern of the patterned step is a rectangle, and the crystal orientation of the long side of the sidewall of the step is etchedOf the material of the epitaxial layer
The crystal directions are parallel, and the short edge in the side wall of the step is etched into a fold line with an angle.
Optionally, the top view of the patterned step is square, and the remaining edge of the sidewall of the step is etched to form an angled fold line.
Optionally, the fold lines are mutually included at an angle of 120 degrees, and the fold lines and the material of the epitaxial layer
The crystal orientation forms an included angle of 120 °.
Optionally, the method further comprises:
forming at least one through hole, wherein the through hole sequentially penetrates through the second semiconductor layer and the light emitting layer and exposes the surface of the first semiconductor layer;
forming a first ohmic contact layer on a surface of the first semiconductor layer in the via hole;
sequentially forming a reflector layer and a metal barrier layer on the surface of the second semiconductor layer, wherein the reflector layer and the metal barrier layer expose the through hole and the step;
forming a dielectric layer material on the surface of the first ohmic contact layer, the surface of the metal barrier layer, the patterned step and the through hole;
etching the dielectric layer material to form a dielectric layer with a first opening exposing the first ohmic contact layer and a second opening exposing the surface of the partial metal barrier layer; and
forming a first electrode in the first opening and a part of the surface of the dielectric layer, forming a second electrode in the second opening and a part of the surface of the dielectric layer,
and the first electrode and the second electrode positioned on the surface of the dielectric layer are not contacted.
Optionally, the method further comprises:
forming a first ohmic contact layer on the surface of the first semiconductor layer at the bottom of the patterned step;
sequentially forming a reflector layer and a metal barrier layer on the surface of the second semiconductor layer, wherein the steps are exposed by the reflector layer and the metal barrier layer;
forming a dielectric layer material on the surface of the first ohmic contact layer, the surface of the metal barrier layer and the patterned step;
etching the dielectric layer material to form a dielectric layer with a first opening exposing a part of the surface of the first ohmic contact layer and a second opening exposing a part of the surface of the metal barrier layer; and
forming a first electrode in the first opening and a part of the surface of the dielectric layer, forming a second electrode in the second opening and a part of the surface of the dielectric layer,
and the first electrode and the second electrode positioned on the surface of the dielectric layer are not contacted.
Optionally, the light emitting diode is a mini LED chip.
According to the light emitting diode and the manufacturing method thereof, firstly, the patterned step is prepared, and then the side wall of the patterned step is roughened to obtain the roughened surface. The crystal orientation of the material of the epitaxial layer of each side wall of the patterned step is a set crystal orientation group, and the side wall of the step is coarsened by combining a wet etching technology, so that the area of the side wall can be increased to a greater extent, the lateral light-emitting of the light-emitting diode is improved, the internal quantum efficiency, the light extraction efficiency and the light-emitting morphology of the light-emitting diode are further improved, and the brightness and the light-emitting angle of the light-emitting diode are effectively improved.
Furthermore, when the side wall of the patterned step is etched by the wet method to form a roughened surface, the oxide layer on the surface of the second semiconductor layer can be removed, so that the ohmic contact performance of the second semiconductor layer is obviously improved; the dry etching damage layer on the side wall surface of the patterned steps can be removed, so that the influence of the surface recombination reaction of the epitaxial layer material on the quantum efficiency in the light-emitting diode is reduced, and the light emission of the light-emitting diode is improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1a to 1f show cross-sectional views of a light-emitting diode according to a first embodiment of the invention at different stages in the manufacturing process;
fig. 2a to 2f show cross-sectional views of a light-emitting diode according to a second embodiment of the invention at different stages in the manufacturing process;
FIG. 3a is a schematic top view of a patterned step in an LED according to the present invention; fig. 3b shows a schematic top view of another patterned step in a light emitting diode according to the present invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
The present invention may be embodied in various forms, some examples of which are described below.
A light emitting diode (mini LED chip) is a current hot display backlight source, and in order to overcome the problem of luminance reduction caused by a complex light uniformity technique adopted in the backlight source, the light emitting diode used as the backlight source needs to have high luminance and a large light emitting angle. The luminance and the luminous angle of the light emitting diode are improved by improving the light extraction efficiency of the edge area of the light emitting diode.
Fig. 1a to 1f show cross-sectional views of a light emitting diode according to a first embodiment of the present invention at different stages in the manufacturing process, the present embodiment providing a manufacturing method operating on a monolithic wafer, the figures only showing one of the chip units.
The present application provides a method for manufacturing a light emitting diode to obtain the light emitting diode in the first embodiment, the method comprising the steps of:
an epitaxial layer is formed on a substrate. Specifically, as shown in fig. 1a, an epitaxial layer 120 is prepared on a surface of a substrate 110 through an epitaxial growth process. The total thickness of the epitaxial layer 120 is 5 to 10 microns. Further, a first semiconductor layer 122, a light emitting layer 123, and a second semiconductor layer 125 are sequentially formed on the surface of the substrate 110 using a metal organic chemical vapor deposition process. In alternative embodiments, the epitaxial layer 120 may also be formed using laser assisted molecular beam epitaxy, laser sputtering, or hydride vapor phase epitaxy. In other embodiments, forming the epitaxial layer 120 further includes forming a buffer layer 121 between the first semiconductor layer 122 and the substrate 110 and forming an electron blocking layer 124 between the light emitting layer 123 and the second semiconductor layer 125. The first semiconductor layer 122 is a gallium nitride material layer of a first doping type (N-type), the light-emitting layer 123 is, for example, a Multiple Quantum Well (MQW) structure layer, the electron blocking layer 124 is an aluminum gallium nitride material layer of a second doping type (P-type), and the second semiconductor layer 125 is a gallium nitride material layer of a second doping type (P-type). The MQW multi-quantum well structure is composed of a gallium nitride material layer/indium gallium nitride/aluminum gallium nitride material, for example. The substrate 110 includes, but is not limited to, one of a mirror or micro/nano patterned sapphire substrate, and in a preferred embodiment, the substrate 110 is micro patterned sapphire. In other alternative embodiments, the material of the substrate may also be gallium oxide, lithium gallate, lithium aluminate, and the like. The thickness of the substrate 110 is 300 micrometers to 2 millimeters, and the diameter of the substrate 110 is 1 inch to 8 inches. Wherein the epitaxial layer 120 comprises one of reciprocating continuous progressive epitaxial layers composed of GaN/InGaN material system, the preferred embodiment of which is an InGaN structure with different In composition.
Next, at least one via 171 and patterned step 172 are formed in an array on epitaxial layer 120, for example, using photolithography and dry etching processes. Further, photoresist is applied, exposed, and developed on the surface of the second semiconductor layer 125, and a corresponding pattern is formed on the surface of the second semiconductor layer 125 by using a photolithography process. Then, a dry etching process is used to form a via hole 171 sequentially penetrating through the second semiconductor layer 125, the electron blocking layer 124, the light emitting layer 123 and reaching the surface of the first semiconductor layer 122, andpatterned step 172. Wherein the patterned step 172 is located around the epitaxial layer 120 to separate the adjacent leds. The resulting epitaxial layer material at the sidewalls of patterned step 172 has a crystal orientation of
A family of crystal orientations. Further, the crystal direction of the opposite side of the sidewall of the step perpendicular to the reference crystal direction is etched to be of the material of the epitaxial layer 120
The crystal orientation being parallel, the reference crystal orientation being selected, for example, as
And (4) crystal orientation. The epitaxial layer 120 is a gallium nitride material layer in which hexagonal gallium nitride is present
The crystal orientation has a higher wet etching rate. Next, for example, the sidewalls of the plurality of patterned steps 172 are chemically etched using a heated first solution, so that the sidewalls of the plurality of patterned steps 172 form a roughened surface, and the sidewalls having the roughened surface are randomly distributed with a plurality of triangular prisms (triangular prisms) having a micro-nano size, for example. The first solution is an alkaline solution having a concentration of not more than 20%, and the first solution is, for example, one of potassium hydroxide, sodium hydroxide, and tetramethylammonium hydroxide. The time for chemically etching the sidewalls of the plurality of patterned steps 172 using the first solution is 5 to 60 minutes. In the process of chemically etching the sidewalls of the plurality of patterned steps 172 with the first solution, the first solution is heated at a temperature of 30 to 150 ℃. Furthermore, when the sidewalls of the patterned steps 172 are chemically etched, the oxide layer on the surface of the second semiconductor layer 125 can be removed by using the first solution chemical etching, so that the ohmic contact performance of the second semiconductor layer 125 is significantly improved; and an etching damage layer formed on the side wall surfaces of the plurality of patterned steps 172 in the dry etching process can be removed, so that the problem of quantum efficiency reduction caused by surface recombination is solvedLow problem.
The top view of the patterned step 172 is a symmetrical pattern, and the symmetrical pattern includes one or a combination of rectangles, squares, diamonds, or hexagons. At least one set of opposite sides of the symmetrical pattern is perpendicular to the reference crystal direction and is etched into the material of the epitaxial layer 120
The crystal directions are parallel. Further, referring to fig. 3a, a schematic top view of a patterned step in the led is shown, the patterned step 1721 is a diamond shape, wherein the crystal orientation of one set of sides of the diamond shape is
Crystal orientation, crystal orientation of the other set of edges and crystal orientation
And forms an included angle of 120 degrees. In an alternative embodiment, referring to fig. 3b, a schematic top view of a patterned step in a led is shown, the patterned step 1722 is rectangular in top view, and the crystal orientation of the long side of the rectangle is
Crystal orientation, and the short sides of the rectangle are composed of lines forming an angle of 120 DEG with the material of the epitaxial layer 120
The crystal orientation forms an included angle of 120 °. Wherein the rectangular gap as shown in fig. 3b is the area where the first electrode is formed later. In other embodiments, the top view of the patterned step is a square, and the crystal orientation of one set of opposite sides of the square is
The other pair of opposite sides of the crystal orientation, square, being composed of a fold line at an angle of 120 DEG to the material of the epitaxial layer 120
The crystal orientation forms an included angle of 120 °. In other embodiments, the top view pattern of the patterned steps is a hexagon, wherein the crystal orientation of one set of edges of the hexagon is
Crystal orientation, crystal orientation of the remaining edge and crystal orientation
And forms an included angle of 120 degrees.
Next, a first ohmic contact layer is formed in the via hole. Specifically, as shown in fig. 1b, the first ohmic contact layer 133 is formed in the via hole 171. Further, the first ohmic contact layer 133 of the first doping type, for example, having a total thickness of 500nm, is formed in the via hole 171 using, for example, photolithography and physical vapor deposition techniques. Specifically, the semiconductor structure shown in fig. 1b is annealed under a nitrogen atmosphere at a temperature of, for example, 800 ℃, for one minute, so that the first ohmic contact layer 133 on the surface of the first semiconductor layer 122 in the via hole 171 forms a good ohmic contact with the first semiconductor layer 122. In alternative embodiments, the first ohmic contact layer 133 may not be thermally annealed. Wherein a gap exists between the first ohmic contact layer 133 and the sidewall of the via hole 171. The first ohmic contact layer 133 includes at least one material of chromium, aluminum, titanium, and gold, for example.
And then, sequentially forming a reflecting mirror layer and a metal barrier layer on the surface of the second semiconductor layer. Specifically, as shown in fig. 1c, a mirror layer 131 and a metal barrier layer 132 are sequentially formed on the surface of the second semiconductor layer 125. Further, a mirror layer 131 is formed on the surface of the second semiconductor layer 125 and a metal barrier layer 132 is formed on the surface of the mirror layer 131, for example, by photolithography and physical vapor deposition processes, and the via 171 and the step 172 are exposed. The mirror layer 131 is, for example, a silver-nickel layer with a thickness of 200nm, and the metal barrier layer 132 is, for example, a titanium-tungsten stack with a thickness of 500 nm.
And then, forming dielectric layer materials on the surface of the metal barrier layer, the surface of the step, the surface of the first ohmic contact layer and the through hole. Specifically, as shown in fig. 1d, a dielectric layer material 141 is formed on the surface of the semiconductor structure shown in fig. 1 c. Further, a dielectric layer material 141 is deposited with a thickness of, for example, 1000 nm, for example, by a CVD (Chemical Vapor Deposition) process. The dielectric layer material 141 is disposed on the surfaces of the first semiconductor layer 122, the first ohmic contact layer 133 and the metal barrier layer 132. In other words, the dielectric material 141 covers the sidewalls and bottom wall of the step 172, fills the inside of the via hole 171, and covers the surfaces and sidewalls of the first ohmic contact layer 133 and the metal barrier layer 132. Dielectric layer material 141 includes, but is not limited to, insulating dielectrics such as silicon nitride, silicon oxide, silicon oxynitride, and the like.
And then, forming a dielectric layer with a first opening exposing the first ohmic contact layer and a second opening exposing a part of the surface of the metal barrier layer. Specifically, as shown in fig. 1e, a first opening 181 exposing the first ohmic contact layer 133 and a second opening 182 exposing a portion of the surface of the metal barrier layer 132 are formed in the dielectric layer material 141. Further, a first opening 181 communicating with the first ohmic contact layer 133 and a second opening 182 communicating with a portion of the metal barrier layer 132 are formed in the dielectric layer material 141 by, for example, photolithography and dry etching processes to form the dielectric layer 140.
Next, a first electrode and a second electrode are formed. Specifically, as shown in fig. 1f, a first electrode 151 and a second electrode 152 are formed. Further, a pattern of the electrode is defined, for example, by a photolithography process, and an adhesion layer (not shown) and a metal layer are formed in the pattern. The metal layer filling the first opening 181 and contacting the first ohmic contact layer 133 serves as the first electrode 151, the metal layer filling the second opening 182 and contacting the metal barrier layer 132 serves as the second electrode 152, and the first electrode 151 and the second electrode 152 on the surface of the dielectric layer 140 do not contact each other. The first electrode 151 is, for example, an N electrode, and the second electrode 152 is, for example, a P electrode. The adhesion layer is, for example, a titanium metal layer with a thickness of 200nm, and the metal layer is, for example, a gold-tin alloy layer with a thickness of 2 μm. In this step, the light emitting diode with the flip-chip through hole structure is obtained.
As shown in fig. 1f, a schematic structural diagram of a light emitting diode provided in a first embodiment is shown. The led 100 is illustrated as a flip-chip via led, but the invention is not limited thereto. The light emitting diode 100 includes a substrate 110, the substrate 110 including but not limited to one of a mirror or a micro/nano patterned sapphire substrate, in a preferred embodiment, the substrate 110 is a micro patterned sapphire substrate. In other alternative embodiments, the substrate material may also be gallium oxide, lithium gallate, lithium aluminate, and the like.
The light emitting diode 100 further includes an epitaxial layer 120 disposed on the surface of the substrate 110, and the epitaxial layer 120 includes a first semiconductor layer 122, a light emitting layer 123, an electron blocking layer 124, and a second semiconductor layer 125 sequentially stacked on the surface of the substrate 110. The epitaxial layer 120 comprises one of reciprocating continuous progressive epitaxial layers consisting of GaN/InGaN material system, the preferred embodiment of which is an InGaN structure with different In composition. In other embodiments, the epitaxial layer 120 further includes a buffer layer 121 between the substrate 110 and the first semiconductor layer 122, and an electron blocking layer 124 between the light emitting layer 123 and the second semiconductor layer 125. The first semiconductor layer 122 is a gallium nitride material layer of a first doping type (N-type), the light-emitting layer 123 is, for example, a Multiple Quantum Well (MQW) structure layer, the electron blocking layer 124 is an aluminum gallium nitride material layer of a second doping type (P-type), and the second semiconductor layer 125 is a gallium nitride material layer of a second doping type (P-type). The MQW multi-quantum well structure is composed of a gallium nitride material layer/indium gallium nitride/aluminum gallium nitride material, for example.
The epitaxial layer 120 also includes a patterned step and at least one via therein. At least one through hole sequentially penetrates through the second semiconductor layer 125, the electron blocking layer 124 and the light emitting layer 123 of the epitaxial layer 120 and exposes the surface of the first semiconductor layer 122; the step is located at the edge region of the epitaxial layer 120, sequentially penetrates through the second semiconductor layer 125, the electron blocking layer 124 and the light emitting layer 123 of the epitaxial layer 120, and exposes the surface of the first semiconductor layer 122 to separate adjacent light emitting diode dies. Surface arrangement of the first semiconductor layer 122 in the viaThere is a first ohmic contact layer 133 in ohmic contact therewith, the first ohmic contact layer 133 has a first doping type, and a gap exists between the first ohmic contact layer 133 and a sidewall of the via hole. The first ohmic contact layer 133 includes, for example, at least one material of chromium, aluminum, titanium, hafnium, and vanadium. The sidewalls of the plurality of patterned steps in the epitaxial layer 120 have a roughened surface, and the sidewalls having the roughened surface are randomly distributed with a plurality of triangular prisms (triangular prisms). The roughened surface is formed by roughening the side wall of the patterned step, wherein the crystal orientation of at least one group of opposite sides in the side wall of the patterned step is
And (4) crystal orientation.
A mirror layer 131 and a metal barrier layer 132 are further sequentially disposed on the surface of the second semiconductor layer 125. The mirror layer 131 is, for example, a nickel silver layer, and has a thickness of, for example, 200 nm. The metal barrier layer 132 is, for example, a titanium tungsten stack, and has a thickness of, for example, 500 nm.
The light emitting diode 100 further includes a dielectric layer 140 on the surface of the metal barrier layer 132 and in the patterned step and via, and having a first opening exposing the first ohmic contact layer 133 and a second opening exposing a portion of the surface of the metal barrier layer 132. The light emitting diode 100 further includes a first electrode 151 and a second electrode 152. The first electrode 151 is located on the surface of the dielectric layer 140, fills the first opening and contacts the first ohmic contact layer 133, the second electrode 152 is located on the surface of the dielectric layer 140, fills the second opening and contacts the metal barrier layer 132, and the first electrode 151 and the second electrode 152 located on the surface of the dielectric layer 140 are separated from each other.
Fig. 2a to 2f show cross-sectional views of a light emitting diode according to a second embodiment of the present invention at different stages in the manufacturing process, the present embodiment providing a manufacturing method operating on a monolithic wafer, the figures only showing one of the chip units.
The present application provides a method for manufacturing a light emitting diode to obtain a light emitting diode in a second embodiment, the method comprising the steps of:
an epitaxial layer is formed on a substrate. Specifically, as shown in fig. 2a, an epitaxial layer 220 is prepared on a surface of a substrate 210 through an epitaxial growth process. The total thickness of the epitaxial layer 220 is 5 to 10 microns. Further, a first semiconductor layer 222, a light emitting layer 223, and a second semiconductor layer 225 are sequentially formed on the surface of the substrate 210 using a metal organic chemical vapor deposition process. In alternative embodiments, the epitaxial layer 220 may also be formed using laser assisted molecular beam epitaxy, laser sputtering, or hydride vapor phase epitaxy. In other embodiments, forming the epitaxial layer 220 further includes forming a buffer layer 221 between the first semiconductor layer 222 and the substrate 210 and forming an electron blocking layer 224 between the light emitting layer 223 and the second semiconductor layer 225. The first semiconductor layer 222 is a gallium nitride material layer of a first doping type (N-type), the light-emitting layer 223 is, for example, a Multiple Quantum Well (MQW) structure layer, the electron blocking layer 224 is an aluminum gallium nitride material layer of a second doping type (P-type), and the second semiconductor layer 225 is a gallium nitride material layer of a second doping type (P-type). The MQW multi-quantum well structure is composed of a gallium nitride material layer/indium gallium nitride/aluminum gallium nitride material, for example. Substrate 210 includes, but is not limited to, one of a mirror or micro/nano patterned sapphire substrate, and in a preferred embodiment, substrate 210 is a mirror sapphire substrate. Wherein the epitaxial layer 220 comprises one of reciprocating continuous progressive epitaxial layers composed of GaN/InGaN material system, the preferred embodiment of which is an InGaN structure with different In compositions.
Next, a patterned step 271 is formed on the epitaxial layer 220, for example, using photolithography and dry etching processes. Further, photoresist is applied, exposed, and developed on the surface of the second semiconductor layer 225, and a corresponding pattern is formed on the surface of the second semiconductor layer 225 by using a photolithography process. Then, a dry etching process is used to form a patterned step 271 which sequentially penetrates through the second semiconductor layer 225, the electron blocking layer 224, and the light emitting layer 223 to reach the surface of the first semiconductor layer 222. Wherein the patterned step 271 is located around the epitaxial layer 220 to separate the adjacent led dies. Further, in the process of forming the patterned step 271, a photolithography process is first used to form a layer penetrating the second semiconductor layer 225 and then sequentially penetrating the second semiconductor layer 225 along the surface of the second semiconductor layer 225The sub-barrier layer 224, the light emitting layer 223, and a step reaching the surface of the first semiconductor layer 222. Then, for example, a dry etching process is used to pattern at least a portion of the sidewall of the step, and the crystal orientation of the epitaxial layer material at the sidewall of the patterned step 271 is obtained
A family of crystal orientations. Further, the opposite side of the sidewall of the step 271 perpendicular to the reference crystal direction is etched to be of the material of the epitaxial layer 220
The crystal directions are parallel. The reference crystal orientation is selected, for example, as
And (4) crystal orientation. The epitaxial layer 220 is a gallium nitride material layer in which hexagonal gallium nitride is present
The crystal orientation has a higher wet etching rate. Next, for example, the sidewalls of the plurality of patterned steps 271 are chemically etched using a heated first solution, so that the sidewalls of the plurality of patterned steps 271 form a roughened surface, and the sidewalls having the roughened surface are randomly distributed with a plurality of triangular prisms (triangular prisms) having a micro-nano size, for example. The first solution is an alkaline solution having a concentration of not more than 20%, and the first solution is, for example, one of potassium hydroxide, sodium hydroxide, and tetramethylammonium hydroxide. The time for chemically etching the sidewalls of the plurality of patterned steps 271 with the first solution is 5 to 60 minutes. In the process of chemically etching the side walls of the plurality of patterned steps 271 with the first solution, the first solution is heated at 30 to 150 ℃. Furthermore, when the sidewalls of the patterned steps 271 are chemically etched, the oxide layer on the surface of the second semiconductor layer 225 can be removed by using the first solution chemical etching, so that the ohmic contact performance of the second semiconductor layer 225 is significantly improved; the etching damage layer formed on the sidewall surface of the patterned steps 271 in the etching process can be removed, so that the problem of surface damage is solvedThe quantum efficiency is reduced due to recombination.
The top view of the patterned step 271 is a symmetrical pattern, and the symmetrical pattern includes one or a combination of rectangles, squares, diamonds, or hexagons. At least one set of opposite sides of the symmetrical pattern is perpendicular to the reference crystal direction and is etched into the material of epitaxial layer 220
The crystal directions are parallel. Further, referring to fig. 3a, a schematic top view of a patterned step in the led is shown, the patterned step 1721 is a diamond shape, wherein the crystal orientation of one set of sides of the diamond shape is
Crystal orientation, crystal orientation of the other set of edges and crystal orientation
And forms an included angle of 120 degrees. In an alternative embodiment, referring to fig. 3b, a schematic top view of a patterned step in a led is shown, the patterned step 1722 is rectangular in top view, and the crystal orientation of the long side of the rectangle is
Crystal orientation, and the short sides of the rectangle are composed of lines angled at 120 DEG to the material of epitaxial layer 220
The crystal orientation forms an included angle of 120 °. Wherein the rectangular gap as shown in fig. 3b is the area where the first electrode is formed later. In other embodiments, the top view of the patterned step is a square, and the crystal orientation of one set of opposite sides of the square is
The other pair of opposite sides of the crystal orientation, square, is composed of a fold line at an angle of 120 DEG and the fold line is in contact with the material of the epitaxial layer 220
The crystal orientation forms an included angle of 120 °. In other embodiments, the top view pattern of the patterned steps is a hexagon, wherein the crystal orientation of one set of edges of the hexagon is
Crystal orientation, crystal orientation of the remaining edge and crystal orientation
And forms an included angle of 120 degrees.
Next, a first ohmic contact layer is formed on the first semiconductor layer. Specifically, as shown in fig. 2b, the first ohmic contact layer 233 is formed on the surface of the first semiconductor layer 222 (the lower step surface of the step 271). Further, the first ohmic contact layer 233 of the first doping type is formed on the surface of the first semiconductor layer 222 (the lower step surface of the step 271) to have a total thickness of 800 nm, for example, using photolithography and physical vapor deposition techniques. Specifically, the semiconductor structure shown in fig. 2a is annealed under a nitrogen atmosphere at a temperature of, for example, 400 to 700 ℃ for one minute, so that the first ohmic contact layer 233 on the surface of the first semiconductor layer 222 and the first semiconductor layer 222 form a good ohmic contact. In an alternative embodiment, the first ohmic contact layer 233 may not employ the thermal annealing process. Wherein a gap exists between the first ohmic contact layer 233 and the sidewall of the step 271. The first ohmic contact layer 233 includes, for example, at least one material of chromium, aluminum, titanium, hafnium, and vanadium.
And then, sequentially forming a reflecting mirror layer and a metal barrier layer on the surface of the second semiconductor layer. Specifically, as shown in fig. 2c, a mirror layer 231 and a metal barrier layer 232 are sequentially formed on the surface of the second semiconductor layer 225. Further, a mirror layer 231 of the second doping type is formed on the surface of the second semiconductor layer 225 in the semiconductor structure shown in fig. 2b by using photolithography and physical vapor deposition processes, and a metal barrier layer 232 is formed on the surface of the mirror layer 231, and the step 271 is exposed. The mirror layer 231 is, for example, a 200nm thick silver-coated indium tin oxide layer, and the metal barrier layer 232 is, for example, a 600nm thick titanium-platinum stack.
And then, forming a dielectric layer material on the surface of the metal barrier layer, in the step and on the surface of the first ohmic contact layer. As shown in fig. 2d, a dielectric layer material 241 is formed on the surface of the semiconductor structure shown in fig. 2 c. Further, a dielectric layer 241 having a thickness of, for example, 1000 nm is deposited by, for example, a CVD (Chemical Vapor Deposition) process. The dielectric layer material 241 is disposed on the surfaces of the first semiconductor layer 222, the first ohmic contact layer 233 and the metal barrier layer 232. In other words, the dielectric material 241 covers the sidewalls and the bottom wall of the step 271, and the surfaces of the first ohmic contact layer 233 and the metal barrier layer 232. Dielectric layer material 241 includes, but is not limited to, insulating dielectrics such as silicon nitride, silicon oxide, silicon oxynitride, etc.
Then, a dielectric layer with a first opening exposing a part of the surface of the first ohmic contact layer and a second opening exposing a part of the surface of the metal barrier layer is formed. Specifically, as shown in fig. 2e, a first opening 282 reaching a portion of the surface of the first ohmic contact layer 233 and a second opening 281 reaching a portion of the surface of the metal barrier layer 232 are formed in the dielectric layer material 241. Further, a first opening 282 in communication with a portion of the first ohmic contact layer 233 and a second opening 281 in communication with a portion of the metal barrier layer 232 are formed in the dielectric layer material 241, for example, by photolithography and dry etching processes, thereby forming the dielectric layer 240.
Next, a first electrode and a second electrode are formed. Specifically, as shown in fig. 2f, a first electrode 251 and a second electrode 252 are formed. Further, a pattern of the electrode is defined, for example, by a photolithography process, and an adhesion layer (not shown) and a metal layer are formed in the pattern. The metal layer filling the first opening 282 and connected to the first ohmic contact layer 233 serves as the first electrode 251, the metal layer filling the second opening 281 and connected to the metal barrier layer 232 serves as the second electrode 252, and the first electrode 251 and the second electrode 252 on the surface of the dielectric layer 240 are not in contact with each other. The first electrode 151 is, for example, an N electrode, and the second electrode 152 is, for example, a P electrode. The adhesion layer is, for example, a titanium metal layer with a thickness of 200nm, and the metal layer is, for example, a gold layer with a thickness of 600nm and a gold-tin stack with a thickness of 200 nm. In this step, the light emitting diode with the flip-chip through hole structure is obtained.
As shown in fig. 2f, a schematic structural diagram of a light emitting diode provided by a second embodiment is shown. The led 200 is illustrated by using an led with a flip-chip via structure as an example, but the invention is not limited thereto. The light emitting diode 200 includes a substrate 210, the substrate 210 including but not limited to one of a mirror or micro/nano patterned silicon substrate, in the preferred embodiment, the substrate 210 is a mirror silicon substrate.
The light emitting diode 200 further includes an epitaxial layer 220 disposed on the surface of the substrate 210, and the epitaxial layer 220 includes a buffer layer 221, a first semiconductor layer 222, a light emitting layer 223, an electron blocking layer 224, and a second semiconductor layer 225 sequentially stacked on the surface of the substrate 210. The epitaxial layer 220 comprises one of reciprocating continuous progressive epitaxial layers consisting of GaN/InGaN material system, the preferred embodiment of which is an InGaN structure with different In composition. The first semiconductor layer 222 is a gallium nitride material layer of a first doping type (N-type), the light-emitting layer 223 is, for example, a Multiple Quantum Well (MQW) structure layer, the electron blocking layer 224 is an aluminum gallium nitride material layer of a second doping type (P-type), and the second semiconductor layer 225 is a gallium nitride material layer of a second doping type (P-type). The MQW multi-quantum well structure is composed of a gallium nitride material layer/indium gallium nitride/aluminum gallium nitride material, for example.
A patterned step is also included in epitaxial layer 220. The step is located at the edge region of the epitaxial layer 220, sequentially penetrates through the second semiconductor layer 225, the electron blocking layer 224 and the light emitting layer 223 of the epitaxial layer 220, and exposes the surface of the first semiconductor layer 222 to separate adjacent light emitting diode dies. The sidewalls of the plurality of patterned steps in the epitaxial layer 220 have a roughened surface, and a plurality of triangular prisms (triangular prisms) having a micro-nano size, for example, are randomly distributed on the sidewalls having the roughened surface. The roughened surface is formed by roughening the side wall of the patterned step, wherein the crystal orientation of at least one group of opposite sides in the side wall of the patterned step is
And (4) crystal orientation. The surface of the first semiconductor layer 222 in the patterned step is further provided with a first ohmic contact layer 233 in ohmic contact therewith, the first ohmic contact layer 233 has a first doping type, and a gap exists between the first ohmic contact layer 133 and the sidewall of the via hole. The first ohmic contact layer 133 includes, for example, at least one material of chromium, aluminum, titanium, hafnium, and vanadium.
A mirror layer 231 and a metal barrier layer 232 are sequentially disposed on the surface of the second semiconductor layer 225. The mirror layer 231 is, for example, a silver-coated indium tin oxide layer, and has a thickness of, for example, 200 nm. The metal barrier layer 232 is, for example, a titanium platinum stack, and has a thickness of, for example, 600 nm.
The light emitting diode 200 further includes a dielectric layer 240 on the surface of the metal barrier layer 232, a portion of the surface of the first ohmic contact layer 233, and in the patterned step, and having a first opening exposing a portion of the surface of the first ohmic contact layer 233 and a second opening exposing a portion of the surface of the metal barrier layer 232. The light emitting diode 200 further includes a first electrode 251 and a second electrode 252. The first electrode 251 is located on the surface of the dielectric layer 240, fills the first opening and contacts the first ohmic contact layer 233, the second electrode 252 is located on the surface of the dielectric layer 240, fills the second opening and contacts the metal barrier layer 232, and the first electrode 251 and the second electrode 252 are separated from each other.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The scope of the invention should be determined from the following claims.
Claims (28)
1. A light emitting diode, comprising:
the epitaxial layer comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially positioned on the surface of the substrate;
a patterned step positioned around the epitaxial layer, the side wall of the patterned step being a roughened surface,
wherein at least one pair of opposite sides of the sidewall of the patterned step has a crystal orientation with respect to the epitaxial layer
The crystal directions are parallel.
2. The light emitting diode of claim 1, wherein the sidewall having the roughened surface is randomly interspersed with a plurality of triangular prisms.
3. The light emitting diode of claim 1, wherein the patterned step extends through the second semiconductor layer, the light emitting layer and exposes a surface of the first semiconductor layer.
4. The light emitting diode of claim 1, wherein the top view pattern of the patterned steps is a symmetrical pattern comprising a combination of one or more patterns of rectangles, squares, diamonds, or hexagons.
5. The LED of claim 4, wherein the patterned step has a diamond or hexagonal top view, and the remaining sides of the sidewall of the step have a crystallographic orientation that is different from the material of the epitaxial layer
The crystal orientation forms an included angle of 120 °.
6. The LED of claim 4, wherein the patterned step has a rectangular top view, and the crystal orientation of the longer side of the sidewall of the step is in accordance with the material of the epitaxial layer
The crystal directions are parallel, and the short edge in the side wall of the step is a broken line with an angle.
7. The LED of claim 4, wherein the top view of the patterned step is square and the remaining sides of the sidewalls of the step are angled polylines.
8. A light emitting diode according to claim 6 or 7 wherein the fold lines are at an angle of 120 ° to each other and to the material of the epitaxial layers
The crystal orientation forms an included angle of 120 °.
9. The light emitting diode of claim 1, further comprising:
the through hole sequentially penetrates through the second semiconductor layer and the light emitting layer and exposes out of the surface of the first semiconductor layer;
a first ohmic contact layer on the surface of the first semiconductor layer in the through hole;
the reflecting mirror layer is positioned on the surface of the second semiconductor layer, and the metal barrier layer is positioned on the surface of the reflecting mirror layer, and the reflecting mirror layer and the metal barrier layer expose the through hole and the step;
the dielectric layer is positioned on the surface of the metal barrier layer, in the patterned step and the through hole and provided with a first opening exposing the first ohmic contact layer and a second opening exposing part of the surface of the metal barrier layer; and
a first electrode in the first opening and a part of the surface of the dielectric layer, and a second electrode in the second opening and a part of the surface of the dielectric layer,
and the first electrode and the second electrode positioned on the surface of the dielectric layer are not contacted.
10. The light emitting diode of claim 1, further comprising:
the first ohmic contact layer is positioned on the surface of the first semiconductor layer at the bottom of the patterned step;
the reflecting mirror layer is positioned on the surface of the second semiconductor layer, and the metal barrier layer is positioned on the surface of the reflecting mirror layer, and the steps are exposed by the reflecting mirror layer and the metal barrier layer;
the dielectric layer is positioned on the surface of the metal barrier layer and in the patterned step and is provided with a first opening exposing the surface of part of the first ohmic contact layer and a second opening exposing the surface of part of the metal barrier layer; and
a first electrode in the first opening and a part of the surface of the dielectric layer, and a second electrode in the second opening and a part of the surface of the dielectric layer,
and the first electrode and the second electrode positioned on the surface of the dielectric layer are not contacted.
11. The light emitting diode of claim 1, wherein the light emitting diode is a mini LED chip.
12. A method of manufacturing a light emitting diode, comprising:
forming an epitaxial layer on a substrate, wherein the epitaxial layer comprises a first semiconductor layer, a light-emitting layer and a second semiconductor layer which are sequentially positioned on the surface of the substrate;
carrying out dry etching on the first semiconductor layer along the surface of the second semiconductor layer to form a patterned step; and
roughening the side wall of the patterned step to form a roughened surface,
wherein at least one pair of opposite sides of the sidewall of the patterned step has a crystal orientation with respect to the epitaxial layer
The crystal directions are parallel.
13. The method of manufacturing of claim 12, wherein the sidewall having the roughened surface is randomly interspersed with a plurality of triangular prisms.
14. The method of manufacturing of claim 12, wherein roughening the sidewalls of the patterned step to form a roughened surface comprises:
and chemically etching the side wall of the patterned step by adopting a first solution.
15. The manufacturing method according to claim 14, further comprising:
and when the side wall of the patterned step is chemically etched by adopting a first solution, removing the oxide layer on the surface of the second semiconductor layer and the dry etching damage layer on the surface of the side wall of the patterned step by adopting the first solution for chemical etching.
16. The production method according to claim 14, wherein the first solution is an alkaline solution having a concentration of not more than 20%, and the first solution is one of potassium hydroxide, sodium hydroxide, and tetramethylammonium hydroxide.
17. The manufacturing method according to claim 14, wherein the first solution is heat-treated at a temperature of 30 ℃ to 150 ℃ in the chemical etching of the sidewall of the patterned step with the first solution.
18. The manufacturing method according to claim 14, wherein the time for chemically etching the sidewall of the patterned step with the first solution is 5 to 60 minutes.
19. The manufacturing method according to claim 12, wherein the step of performing dry etching to the first semiconductor layer along the surface of the second semiconductor layer to form a patterned step comprises:
and photoetching and dry etching the second semiconductor layer and the light emitting layer to reach the surface of the first semiconductor layer to form a patterned step, wherein the patterned step is positioned on the periphery of the epitaxial layer.
20. The manufacturing method according to claim 19, wherein the step of performing dry etching to the first semiconductor layer along the surface of the second semiconductor layer to form a patterned step further comprises:
etching the crystal direction of the opposite side of the side wall of the step perpendicular to the reference crystal direction into the material of the epitaxial layer
The crystal directions are parallel.
21. The method of manufacturing of claim 12, wherein the top view pattern of the patterned steps is a symmetrical pattern comprising a combination of one or more patterns of rectangles, squares, diamonds, or hexagons.
22. The method of manufacturing of claim 21, wherein the top view pattern of the patterned step is a diamond or hexagon, and the crystal orientation of the remaining edge in the sidewall of the step is etched to be the same as the material of the epitaxial layer
The crystal orientation forms an angle of 120 deg..
23. The manufacturing method according to claim 21, wherein the patterned step has a rectangular top view pattern, and the crystal orientation of the longer side of the sidewall of the step is etched to be in contact with the material of the epitaxial layer
The crystal directions are parallel, and the short edge in the side wall of the step is etched into a fold line with an angle.
24. The method of manufacturing of claim 21, wherein the top view of the patterned step is square and the remaining sides of the sidewalls of the step are etched to form angled fold lines.
25. Method of manufacturing according to claim 23 or 24, wherein the fold lines are mutually angled at 120 ° and are in contact with the material of the epitaxial layer
The crystal orientation forms an included angle of 120 °.
26. The manufacturing method according to claim 12, further comprising:
forming at least one through hole, wherein the through hole sequentially penetrates through the second semiconductor layer and the light emitting layer and exposes the surface of the first semiconductor layer;
forming a first ohmic contact layer on a surface of the first semiconductor layer in the via hole;
sequentially forming a reflector layer and a metal barrier layer on the surface of the second semiconductor layer, wherein the reflector layer and the metal barrier layer expose the through hole and the step;
forming a dielectric layer material on the surface of the first ohmic contact layer, the surface of the metal barrier layer, the patterned step and the through hole;
etching the dielectric layer material to form a dielectric layer with a first opening exposing the first ohmic contact layer and a second opening exposing the surface of the partial metal barrier layer; and
forming a first electrode in the first opening and a part of the surface of the dielectric layer, forming a second electrode in the second opening and a part of the surface of the dielectric layer,
and the first electrode and the second electrode positioned on the surface of the dielectric layer are not contacted.
27. The manufacturing method according to claim 12, further comprising:
forming a first ohmic contact layer on the surface of the first semiconductor layer at the bottom of the patterned step;
sequentially forming a reflector layer and a metal barrier layer on the surface of the second semiconductor layer, wherein the steps are exposed by the reflector layer and the metal barrier layer;
forming a dielectric layer material on the surface of the first ohmic contact layer, the surface of the metal barrier layer and the patterned step;
etching the dielectric layer material to form a dielectric layer with a first opening exposing a part of the surface of the first ohmic contact layer and a second opening exposing a part of the surface of the metal barrier layer; and
forming a first electrode in the first opening and a part of the surface of the dielectric layer, forming a second electrode in the second opening and a part of the surface of the dielectric layer,
and the first electrode and the second electrode positioned on the surface of the dielectric layer are not contacted.
28. The manufacturing method according to claim 12, wherein the light emitting diode is a mini LED chip.
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1357928A (en) * | 2000-12-04 | 2002-07-10 | 光磊科技股份有限公司 | Semiconductor photoelectronic device with non-rectangular substrate and its manufacture |
| CN101350389A (en) * | 2007-07-19 | 2009-01-21 | 富士迈半导体精密工业（上海）有限公司 | Nitrifier semiconductor light emitting element and method for fabricating the same |
| US20110220866A1 (en) * | 2010-03-09 | 2011-09-15 | Micron Technology, Inc. | Solid state lighting devices grown on semi-polar facets and associated methods of manufacturing |
| KR20110116453A (en) * | 2010-04-19 | 2011-10-26 | 삼성엘이디 주식회사 | Semiconductor light emitting device and light emitting devide package |
| CN103403842A (en) * | 2011-08-09 | 2013-11-20 | 松下电器产业株式会社 | Structure for growth of nitride semiconductor layer, stacked structure, nitride-based semiconductor element, light source, and manufacturing method for same |
| CN103828073A (en) * | 2011-09-16 | 2014-05-28 | 首尔伟傲世有限公司 | Light emitting diode and method of manufacturing same |
| US20150170901A1 (en) * | 2013-12-13 | 2015-06-18 | University Of Maryland, College Park | Methods of Fabricating Micro- and Nanostructure Arrays and Structures Formed Therefrom |
| CN109192832A (en) * | 2018-09-30 | 2019-01-11 | 武汉大学 | A kind of side wall has the gallium nitride LED chip and preparation method thereof of nanoprism structures |
| CN111146314A (en) * | 2018-11-06 | 2020-05-12 | 中国科学院苏州纳米技术与纳米仿生研究所 | Method for improving light extraction efficiency of nitride semiconductor ultraviolet light-emitting diode and application |
| CN112510126A (en) * | 2020-11-17 | 2021-03-16 | 杭州士兰明芯科技有限公司 | Deep ultraviolet light emitting diode and manufacturing method thereof |
-
2021
- 2021-09-15 CN CN202111079333.4A patent/CN113964249A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1357928A (en) * | 2000-12-04 | 2002-07-10 | 光磊科技股份有限公司 | Semiconductor photoelectronic device with non-rectangular substrate and its manufacture |
| CN101350389A (en) * | 2007-07-19 | 2009-01-21 | 富士迈半导体精密工业（上海）有限公司 | Nitrifier semiconductor light emitting element and method for fabricating the same |
| US20110220866A1 (en) * | 2010-03-09 | 2011-09-15 | Micron Technology, Inc. | Solid state lighting devices grown on semi-polar facets and associated methods of manufacturing |
| KR20110116453A (en) * | 2010-04-19 | 2011-10-26 | 삼성엘이디 주식회사 | Semiconductor light emitting device and light emitting devide package |
| CN103403842A (en) * | 2011-08-09 | 2013-11-20 | 松下电器产业株式会社 | Structure for growth of nitride semiconductor layer, stacked structure, nitride-based semiconductor element, light source, and manufacturing method for same |
| CN103828073A (en) * | 2011-09-16 | 2014-05-28 | 首尔伟傲世有限公司 | Light emitting diode and method of manufacturing same |
| US20150170901A1 (en) * | 2013-12-13 | 2015-06-18 | University Of Maryland, College Park | Methods of Fabricating Micro- and Nanostructure Arrays and Structures Formed Therefrom |
| CN109192832A (en) * | 2018-09-30 | 2019-01-11 | 武汉大学 | A kind of side wall has the gallium nitride LED chip and preparation method thereof of nanoprism structures |
| CN111146314A (en) * | 2018-11-06 | 2020-05-12 | 中国科学院苏州纳米技术与纳米仿生研究所 | Method for improving light extraction efficiency of nitride semiconductor ultraviolet light-emitting diode and application |
| CN112510126A (en) * | 2020-11-17 | 2021-03-16 | 杭州士兰明芯科技有限公司 | Deep ultraviolet light emitting diode and manufacturing method thereof |
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