CN113363311A - Double-groove SiC power MOS device - Google Patents
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Abstract
A double-groove SiC power MOS device comprises a source electrode, a drain electrode, a grid electrode, an N + substrate layer and an N-drift region, wherein the drain electrode and the N-drift region are respectively arranged on the bottom surface and the upper surface of the N + substrate layer; p well regions are respectively arranged on two sides of the upper surface of the N-drift region, and a P + region is arranged on the outer end of the transverse section of the P well region; a P shielding layer is arranged in the middle of the P well regions on the two sides, and a super junction is arranged below the P shielding layer; a grid electrode groove and a grid electrode are arranged on the P shielding layer; a P-body region is arranged between the grid groove and the P well regions on the two sides, and an N + region is arranged on the P-body region; a source electrode is arranged on the P well region, the P + region and the N + region; an interconnection electrode is provided between the source and the gate. The invention has the advantages that: through improving the traditional vertical power SiC MOS structure of the groove gate, the breakdown voltage of the device is improved, the on-resistance is reduced, and the advanced breakdown of the gate oxide layer is effectively prevented.
Description
Technical Field
The invention belongs to the technical field of microelectronics, relates to the design of a semiconductor device, and particularly relates to a SiC UMOSFET device capable of improving the reliability of a gate dielectric.
Background
The third generation semiconductor SiC has the characteristics of wide forbidden band width, high critical breakdown electric field, high saturation drift rate and the like, and is very suitable for extreme severe application environments such as high temperature, large voltage, high frequency, radiation resistance and the like. The development of the SiC-based semiconductor is beneficial to realizing high-efficiency, high-mobility, miniaturization and all-weather application of modern military electronic systems; meanwhile, the solar energy power generation device can be widely applied to civil power electronic equipment and plays an important role in the fields of rail transit, solar power generation, aerospace and the like. The SiC UMOSFET has the characteristics of low gate current, low on-resistance, stable resistance positive temperature coefficient, high heat dissipation efficiency and the like, and is the first choice in various SiC devices. However, the conventional SiC UMOSFET structure has a serious disadvantage that when the device is in a blocking operation state, the electric field concentration effect of the oxide layer at the bottom of the gate trench is very significant, which leads to early breakdown of the gate oxide layer and reduces the breakdown voltage of the device. The design provides a SiC UMOSFET with a double-groove structure, and grooves are also dug under a source electrode on the basis of the traditional UMOSFET. The dual-trench UMOSFET with the groove dug at the source can transfer the peak electric field originally under the gate electrode to the position under the source groove, and effectively relieves the electric field concentration phenomenon of the gate electrode. Meanwhile, a P shielding layer and a super junction (junction) structure are added below the gate. Due to the introduction of the P-shielding structure, the gate oxide layer is shielded from being influenced by a high electric field from the drift region, and the reliability of the device is improved. The super junction enhances the blocking capability, the local super junction is placed below the P shielding layer region, the problem of narrowing of a current path caused by widening of a depletion region between the P shielding layer region and the Ndrift region is solved, and the conduction mode characteristic is improved, so that the super junction has lower conduction resistance on the premise of keeping breakdown voltage.
Disclosure of Invention
The invention aims to provide a double-groove SiC power MOS device aiming at the defects of the prior art, so as to have lower on-resistance on the premise of improving the breakdown voltage of the device.
In order to achieve the purpose, the invention adopts the technical scheme that: a double-groove SiC power MOS device is characterized by comprising a source electrode, a drain electrode, a grid electrode, an N + substrate layer and an N-drift region, wherein the drain electrode and the N-drift region are respectively arranged on the bottom surface and the upper surface of the N + substrate layer; two sides of the upper surface of the N-drift region are respectively provided with L-shaped P well regions which are symmetrically arranged, and a P + region is arranged on the outer end of the transverse section of the P well region; a P shielding layer is arranged in the middle of the P well regions on the two sides, and a super junction is arranged below the P shielding layer; a grid electrode groove is arranged on the P shielding layer, and a grid electrode is arranged in the grid electrode groove; a P-body region is arranged between the grid groove and the P well regions on the two sides, and an N + region is arranged on the P-body region; a source electrode is arranged on the P well region, the P + region and the N + region; and an interconnection electrode is arranged between the source electrode and the grid electrode on the two sides.
Compared with the prior art, the invention has the following advantages: according to the invention, through improving the traditional vertical power SiC MOS structure of the trench gate, the breakdown voltage of the device is improved, the on-resistance is reduced, and the advanced breakdown of the gate oxide layer is effectively prevented.
Drawings
Fig. 1 is a schematic diagram of the structure of the device of the present invention.
Fig. 2 is a flow chart and a structural diagram of a manufacturing process of the device of the present invention.
Description of reference numerals: 1. source, 2, N + region, 3, grid, 4, P-body region, 5, P shielding layer, 6, drain, 7, N + substrate layer, 8, N-drift region, 9, super junction, 10, P well region, 11, P + region, 12 and interconnection electrode.
Detailed Description
Referring to fig. 1, the double-trench SiC power MOS device of the present invention is characterized by including a source 1, a drain 6, a gate 3, an N + substrate layer 7, and an N-drift region 8, where the drain 6 and the N-drift region 8 are respectively disposed on the bottom surface and the top surface of the N + substrate layer 7; two sides of the upper surface of the N-drift region 8 are respectively provided with L-shaped P well regions 10 which are symmetrically arranged, and the upper surface of the outer end of the transverse section of the P well region 10 is provided with a P + region 11; a P shielding layer 5 is arranged in the middle of the P well region 10 on the two sides, and a super junction 9 is arranged below the P shielding layer 5; a grid electrode groove is arranged on the P shielding layer 5, and a grid electrode 3 is arranged in the grid electrode groove; a P-body region 4 is arranged between the grid electrode groove and the P well regions 10 at two sides, and an N + region 2 is arranged above the P-body region 4; a source electrode 1 is arranged above the P well region 10, the P + region 11 and the N + region 2; an interconnection electrode 12 is provided between the source electrode 1 and the gate electrode 3 on both sides. Where N-drift region 8 consists of an upper portion of N-drift region 8 and a lower portion of N-drift region 8 (seen as one region in fig. 1), located above and below superjunction 9, respectively. During manufacturing, the lower part of the N-drift region 8 and the upper part of the N-drift region 8 are formed by epitaxy twice.
Referring to fig. 2, the process flow of the method for manufacturing the device of the present invention is as follows (the specific operations of the following steps of the process all belong to the conventional technology):
(1) coating photoresist on the surface of the N-drift region (8) of the cleaned epitaxial wafer, etching a high-temperature ion implantation region of an N-type region in the super junction (9), and then performing high-temperature nitrogen ion implantation to form an N region of the super junction (9), wherein the thickness of the N region is 0.2 mu m, and the concentration of the N region is 3e +17cm-3。
(2) Coating photoresist on the surface of the epitaxial wafer on which the super junction (9) N region is formed, etching a P-type high-temperature ion implantation region in the super junction 9, and then performing high-temperature Al ion implantation to form a film with the thickness of 0.2 mu m and the concentration of 3e +17cm-3The P-type region of superjunction 9.
And step 5, forming a P well region (10): the source trench is coated with photoresist, and a P well region (10) is etched to form a P well region with a concentration of 5e +17cm-3The depth was 0.3. mu.m. Formation of P shield layer (5): coating photoresist on the grid groove, etching a P shielding layer (5) injection region, and performing P-type ion injection to form a P shielding layer (5) with the concentration of 5e +18cm-3. See e diagram in fig. 2.
And 6, forming a P-body region (4): coating photoresist on the chip finished in the previous step, etching P-body (4) ion implantation regions at two sides of the gate trench, and performing P-type ion implantation to form P-body (4) regions with concentration of 1e +17cm-30.5 μm in depth; see diagram f in fig. 2.
And 7, forming an N + region (2): coating photoresist on the upper surfaces of the P-body region (4) and the P-well region (10), etching an implantation region of the N + region (2), and performing N-type ion implantation to form an N + (2) region with the concentration of 1e +20cm-3Depth of 0.2 μm; see graph g in fig. 2.
And 8, forming a carbon protective film on the surface of the N-drift region (8): after the P-type ion implantation of the step 5 is carried out, a carbon protective film is formed on the surface of the N-drift region (8);
The device of the invention can improve the breakdown voltage of the device, reduce the on-resistance and effectively prevent the advanced breakdown of the gate oxide, and the principle of the device is described as follows:
the existing single-groove UMOSFET has the advantages that the electric field of the device is mainly concentrated below the gate oxide layer, so that the reliability of the oxide is seriously tested and the oxide is easy to break down in advance, and after the double-groove design of source grooving is introduced, the electric field concentration effect at the bottom of the gate oxide layer can be relieved by the groove at the source position, so that the device is prevented from breaking down in advance, and the breakdown voltage of the device is improved. The doping concentration of the introduced P shielding layer is larger than that of Pbase, when the device works in a reverse state, the drain electrode is applied with high voltage, and the electric field of the device is dispersed to the P shielding layer and the N-drift region, so that the electric field concentration effect at the bottom of the gate oxide is relieved, and the advanced breakdown of the gate oxide is avoided. The voltage increases, the depletion region increases, and the electric field decreases. Therefore, the higher the source-drain voltage is, the higher the resistance of the drift layer is, and the higher the on-resistance thereof becomes; the super junction structure is characterized in that an N layer and a P layer in a drift layer are arranged in a longitudinal groove structure, after voltage is applied, depletion layers are connected in a transverse extending mode, finally the depletion layers under the gates are expanded, and the super junction structure breaks through the dependence of the doping concentration of a device and VB, so that on the basis of keeping high breakdown voltage, higher doping concentration can be kept, and the on-resistance of the super junction structure can be reduced.
Claims (2)
1. A double-groove SiC power MOS device is characterized by comprising a source electrode (1), a drain electrode (6), a grid electrode (3), an N + substrate layer (7) and an N-drift region (8), wherein the drain electrode (6) and the N-drift region (8) are respectively arranged on the bottom surface and the upper surface of the N + substrate layer (7); two sides of the upper surface of the N-drift region (8) are respectively provided with L-shaped P well regions (10) which are symmetrically arranged, and the upper surface of the outer end of the transverse section of the P well region (10) is provided with a P + region (11); a P shielding layer (5) is arranged in the middle of the P well regions (10) on the two sides, and a super junction (9) is arranged below the P shielding layer (5); a grid electrode groove is arranged on the P shielding layer (5), and a grid electrode (3) is arranged in the grid electrode groove; a P-body region (4) is arranged between the grid groove and the P well regions (10) at two sides, and an N + region (2) is arranged on the P-body region (4); a source (1) is arranged on the P well region (10), the P + region (11) and the N + region (2); an interconnection electrode (12) is provided between the source electrode (1) and the gate electrode (3) on both sides.
2. The double-trench SiC power MOS device of claim 1, wherein the process for manufacturing the double-trench SiC power MOS device comprises the steps of:
step 1, forming the lower part of an N-drift region (8): epitaxially forming the lower part of an N-drift region (8) on one side of the N + substrate layer (7), and carrying out standard wet process cleaning on the surface;
step 2, forming a super junction (9):
(1) coating photoresist on the surface of the N-drift region (8) of the cleaned epitaxial wafer, etching a high-temperature ion implantation region of an N-type region in the super junction (9), and then performing high-temperature nitrogen ion implantation to form an N region of the super junction (9), wherein the thickness of the N region is 0.2 mu m, and the concentration of the N region is 3e +17cm-3；
(2) On the surface of the epitaxial wafer where the super junction (9) N region is formedCoating photoresist, etching a P-type high-temperature ion implantation region in the super junction (9), and then performing high-temperature Al ion implantation to form a film with the thickness of 0.2 mu m and the concentration of 3e +17cm-3The super junction (9) of (a).
Step 3, forming the upper part of the N-drift region (8): epitaxially growing on the super junction (9) to obtain an N-type drift region (8) with a thickness of 11 μm and a concentration of 7.5e +15cm-3；
And 4, forming a source electrode groove and a grid electrode groove: etching two ends of the upper part of the N-type drift region (8) to form a source electrode groove; etching the middle of the upper part of the N-type drift region (8) to form a gate groove;
and step 5, forming a P well region (10): etching an injection region of a P well region (10) on the source electrode groove and the coated photoresist; forming a P well region with a concentration of 5e +17cm-3Depth of 0.3 μm;
step 6, forming a P shielding layer (5): coating photoresist on the grid groove, etching a P shielding layer (5) injection region, and performing P-type ion injection to form a P shielding layer (5) with the concentration of 5e +18cm-3；
And 7, forming a P-body region (4): coating photoresist on the chip finished in the previous step, etching P-body (4) ion implantation regions at two sides of the gate trench, and performing P-type ion implantation to form P-body (4) regions with concentration of 1e +17cm-30.5 μm in depth;
step 8, forming an N + region (2): coating photoresist on the upper surfaces of the P-body region (4) and the P well region (10), etching an implantation region of the N + region (2), and performing N-type ion implantation to form an N + (2) region with the concentration of 1e +20cm-3Depth of 0.2 μm;
and 9, forming a carbon protective film on the surface of the N-drift region (8): after the P-type ion implantation of the step 5 is carried out, a carbon protective film is formed on the surface of the N-drift region (8);
step 10, high-temperature ion implantation activation: and (3) carrying out 1600 ℃ high-temperature ion implantation annealing on the chip completed in the step (9):
step 11, removing the carbon protective film: removing the carbon protective film on the surface of the chip:
step 12, preparing a grid oxide layer: will remove carbonCleaning the chip surface of the protective film with HF acid, and then performing SiO2Growing a gate dielectric layer with the thickness of 50 nm;
step 13, forming a drain electrode (6): after the gate oxide layer is formed, performing drain region metal deposition, and then stripping two metals of Ni/Au of 20nm/240nm to form a drain region ohmic contact pattern;
step 14, formation of a source (1): and coating photoresist, etching a source region ohmic contact pattern, performing source region metal deposition, sequentially depositing 20nm/240nm Ni/Au metals, then performing ohmic contact annealing, and stripping to form a source electrode (1).
Step 15, forming a gate electrode: forming a gate electrode on the SiC sample subjected to the ohmic contact electrode annealing: Ni/Au of 20nm/240 nm;
step 16, formation of the interconnection electrode (12): coating a stripping glue and a photoresist on the surface of a chip on which a grid (6) is formed, etching contact holes of the grid (6), a source electrode (1) and an N + region (2), then depositing a metal layer, and stripping to form a pattern of an interconnection electrode (12) among the grid (6), the source electrode (1) and the N + region (2), wherein the interconnection electrode (12) is made of Ti/Au two-layer metal and has the thickness of 50nm/200nm respectively.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116130513A (en) * | 2023-04-17 | 2023-05-16 | 南京第三代半导体技术创新中心有限公司 | Silicon carbide trench gate MOSFET based on heterojunction and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130306983A1 (en) * | 2011-02-02 | 2013-11-21 | Rohm Co., Ltd. | Semiconductor device and method for producing same |
| CN107424928A (en) * | 2016-05-23 | 2017-12-01 | 英飞凌科技股份有限公司 | Power semiconductor with charging balanced design |
| KR20210009006A (en) * | 2019-07-16 | 2021-01-26 | 현대자동차주식회사 | Semiconductor device and method manufacturing the same |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130306983A1 (en) * | 2011-02-02 | 2013-11-21 | Rohm Co., Ltd. | Semiconductor device and method for producing same |
| CN107424928A (en) * | 2016-05-23 | 2017-12-01 | 英飞凌科技股份有限公司 | Power semiconductor with charging balanced design |
| KR20210009006A (en) * | 2019-07-16 | 2021-01-26 | 현대자동차주식회사 | Semiconductor device and method manufacturing the same |
Non-Patent Citations (1)
| Title |
|---|
| S. HARADA 等: "First Demonstration of Dynamic Characteristics for SiC Superjunction MOSFET Realized using Multi-epitaxial Growth Method", pages 181 - 184 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116130513A (en) * | 2023-04-17 | 2023-05-16 | 南京第三代半导体技术创新中心有限公司 | Silicon carbide trench gate MOSFET based on heterojunction and manufacturing method thereof |
| CN116130513B (en) * | 2023-04-17 | 2023-06-13 | 南京第三代半导体技术创新中心有限公司 | Silicon carbide trench gate MOSFET based on heterojunction and manufacturing method thereof |
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