CN113363157B - 半导体装置的制造方法 - Google Patents
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Abstract
本发明提供一种半导体装置的制造方法，包括：在第一介电层上形成导体层；在所述导体层中形成凹槽；进行第一蚀刻工艺，使所述凹槽的顶角圆角化；进行第二刻蚀工艺，移除所述凹槽的底面所裸露的所述导体层，以在所述导体层中形成具有圆顶角的开口；以及在所述开口中形成第二介电层。本公开实施例的半导体装置的制造方法可以避免金属线之间的微桥接，提升集成电路的信赖度。
Description
技术领域
本发明是涉及一种集成电路装置的制造方法，尤其涉及一种半导体装置的制造方法。
背景技术
随着半导体装置尺寸不断地缩小，金属线之间的距离愈来愈小，金属线之间常因为工艺的因素造成金属残留而发生微桥接(micro bridge)，因而导致集成电路信赖度的问题。
发明内容
本发明提供一种半导体装置的制造方法，可以避免金属线之间的微桥接，提升集成电路的信赖度。
本发明实施例提出一种半导体装置的制造方法，包括：在第一介电层上形成导体层、缓冲层与硬掩模层；在所述硬掩模层上形成图案化的掩模层；以图案化的掩模层为掩模，进行第一刻蚀工艺，以图案化所述硬掩模层与所述缓冲层，并在所述导体层中形成凹槽；移除所述图案化的掩模层；选择性移除部分所述缓冲层，使所述凹槽的顶角裸露出来；进行第二刻蚀工艺，以圆角化所述凹槽的所述顶角；进行第三刻蚀工艺，移除所述凹槽的底面所裸露的所述导体层，以形成具有圆顶角的多条导线；移除所述硬掩模层与所述缓冲层；以及在所述多条导线上与其彼此之间形成第二介电层。
本发明实施例还提出一种半导体装置的制造方法，包括：在第一介电层上形成导体层；在所述导体层中形成凹槽；进行第一刻蚀工艺，使所述凹槽的顶角圆角化；进行第二刻蚀工艺，移除所述凹槽的底面所裸露的所述导体层，以在所述导体层中形成具有圆顶角的开口；以及在所述开口中形成第二介电层。
本发明实施例的半导体装置的制造方法，在进行第二介电层的沉积工艺之前，已经先将导线的顶角圆化，不仅有助于提升第二介电层的阶梯覆盖性，且第二介电层可以采用无再溅射的沉积工艺，以避免金属线之间的微桥接，提升集成电路的信赖度。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1A至图1F是依照本发明的实施例示出的一种半导体装置的制造流程的剖面示意图。
具体实施方式
图1A至图1F是依照本发明的实施例示出的一种半导体装置的制造流程的剖面示意图。
参照图1A，在衬底10上形成第一介电层12。衬底10可以是半导体衬底，例如是硅衬底。第一介电层12例如是内层介电层(ILD)或是金属层间介电层(IMD)。第一介电层12例如是以化学气相沉积法形成的氧化硅。
接着，在第一介电层12上形成导体层14。导体层14可以是金属层18。导体层14可以还包括阻障层16，位于金属层18与第一介电层12之间。阻障层16例如是钛、氮化钛或其组合。金属层18例如是钨。
之后，在导体层14上形成缓冲层20与硬掩模层22。缓冲层20的材料可以包括氧化硅、氮化硅、氮氧化硅、氮碳化硅、氮碳氧化硅、碳、旋涂碳(SoC)、磷硅玻璃(PSG)、硼硅玻璃(BSG)、硼磷硅玻璃(BPSG)或其组合。
其后，在硬掩模层22上形成图案化的掩模层24。图案化的掩模层24例如是光刻胶图案。
参照图1B，以图案化的掩模层24为掩模，进行刻蚀工艺(例如是各向异性刻蚀工艺)，以形成具有开口26的图案化硬掩模层22a与缓冲层20a，并在导体层14中形成凹槽28。之后移除图案化的掩模层24。
参照图1C，对缓冲层20a进行拉回(pull back)工艺，以选择性移除开口26侧壁所裸露的部分的缓冲层20a，以形成具有凹陷30的缓冲层20b。凹陷30裸露出凹槽28的顶角α。拉回工艺例如是各向同性刻蚀工艺。各向同性刻蚀工艺可以是湿式刻蚀工艺或是干式刻蚀工艺。缓冲层20a与金属层18之间的刻蚀选择比例如是30:1至50：1。湿式刻蚀工艺可以采用氢氟酸溶液或是缓冲氧化刻蚀液(BOE)作为刻蚀剂。干式刻蚀工艺可以是在图案化硬掩模层22a与缓冲层20a之后，不破真空，以原位(in-situ)采用CF4作为刻蚀气体来进行的。
参照图1D，对凹陷30裸露出凹槽28的顶角α处的金属层18进行刻蚀工艺，以形成具有圆顶角β的凹槽28a。干式刻蚀工艺可以是在进行上述拉回工艺之后，不破真空，以原位采用CF4作为刻蚀气体来进行的。
参照图1E，进行各向异性蚀刻工艺(例如是干式刻蚀工艺)，移除凹槽28a的底面所裸露的导体层14，以形成具有圆顶角β的多条导线14a以及具有圆顶角β的开口32。每一条导线14a包括阻障层16a以及金属层18a。开口32例如是长型沟渠，将多条导线14a彼此分离。在一些实施例中，刻蚀工艺还过度刻蚀部分的第一介电层12，以确保多条导线14a可以彼此分离。由于开口30具有圆顶角β，因此，有利于后续形成的第二介电层34的阶梯覆盖性。干式刻蚀工艺可以是在刻蚀顶角α之后，不破真空，以原位采用CF4作为刻蚀气体来进行的。
其后，可以进行刻蚀工艺(例如是各向同性或各向异性刻蚀工艺)，移除硬掩模层22a与缓冲层20b。
参照图1F，在多条导线14a上以及开口32之中形成第二介电层34。第二介电层34例如是以高密度等离子体沉积法所形成的氧化硅层。由于凹槽28a的顶角β已先进行圆角化，因此，在进行高密度等离子体沉积时轰击的等离子体几乎不会再削顶角β，故可以避免削角造成金属残留所衍生的微桥接问题。
综上所述，本公开实施例先形成具有圆顶角的导线，再形成第二介电层，因此，可以避免沉积第二介电层因为削角所衍生的微桥接问题。
Claims (9)
1.一种半导体装置的制造方法，包括：
在第一介电层上形成导体层、缓冲层与硬掩模层；
在所述硬掩模层上形成图案化的掩模层；
以图案化的掩模层为掩模，进行第一刻蚀工艺，以图案化所述硬掩模层与所述缓冲层，并在所述导体层中形成凹槽；
移除所述图案化的掩模层；
选择性移除部分的所述缓冲层，使所述凹槽的顶角裸露出来；
进行第二刻蚀工艺，以圆角化所述凹槽的所述顶角；
进行第三刻蚀工艺，移除所述凹槽的底面所裸露的所述导体层，以形成具有圆顶角的多条导线；
移除所述硬掩模层与所述缓冲层；以及
在所述多条导线上与其彼此之间形成第二介电层。
2.根据权利要求1所述的半导体装置的制造方法，其中所述缓冲层包括氧化硅、氮化硅、氮氧化硅、氮碳化硅、氮碳氧化硅、碳、磷硅玻璃、硼硅玻璃、硼磷硅玻璃或其组合。
3.根据权利要求1所述的半导体装置的制造方法，其中所述选择性移除部分所述缓冲层包括各向同性刻蚀工艺。
4.根据权利要求1所述的半导体装置的制造方法，其中在形成所述第二介电层是以高密度等离子体沉积法，且在进行高密度等离子体沉积法时未对所述导体层进行削顶角。
5.根据权利要求1所述的半导体装置的制造方法，其中所述移除所述图案化的掩模层、所述选择性移除所述部分的所述缓冲层、所述第二刻蚀工艺以及所述第三刻蚀工艺的步骤包括不破真空，以原位进行的干式刻蚀工艺。
6.一种半导体装置的制造方法，包括：
在第一介电层上形成导体层；
在所述导体层中形成凹槽；
进行第一刻蚀工艺，使所述凹槽的顶角圆角化；
进行第二刻蚀工艺，移除所述凹槽的底面所裸露的所述导体层，以在所述导体层中形成具有圆顶角的开口；以及
在具有所述圆顶角的所述开口中形成第二介电层，
其中在所述导体层中形成所述凹槽的步骤包括：
在所述导体层上形成缓冲层、硬掩模层以及图案化的掩模层；以及
图案化所述硬掩模层与所述缓冲层，并在所述导体层中形成所述凹槽；
其中进行所述第一刻蚀工艺之前，包括：
选择性移除部分的所述缓冲层，使所述凹槽的顶角裸露出来。
7.根据权利要求6所述的半导体装置的制造方法，其中所述第一刻蚀工艺步骤包括不破真空，以原位进行的干式刻蚀工艺。
8.根据权利要求6所述的半导体装置的制造方法，其中在形成所述第二介电层是以高密度等离子体沉积法，且在进行高密度等离子体沉积法时未对所述导体层进行削顶角。
9.根据权利要求6所述的半导体装置的制造方法，其中所述开口包括长型沟渠。
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| CN115831866B (zh) * | 2023-02-24 | 2024-02-13 | 广州粤芯半导体技术有限公司 | 一种高深宽比接触孔的制作方法 |
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