CN113299756B - MOSFET with high-resistance layer, preparation method of MOSFET and power transistor module - Google Patents
MOSFET with high-resistance layer, preparation method of MOSFET and power transistor module Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 4
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 229910052742 iron Inorganic materials 0.000 claims description 3
- 229910052749 magnesium Inorganic materials 0.000 claims description 3
- 239000011777 magnesium Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
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Abstract
The invention discloses a MOSFET with a high-resistance layer, a preparation method thereof and a power transistor module, wherein the MOSFET with the high-resistance layer comprises the following components: a semi-insulating substrate layer, a buffer layer, an epitaxial layer and a high-resistance layer; a source electrode, a drain electrode, and a gate electrode; the semi-insulating substrate layer, the buffer layer and the epitaxial layer are sequentially arranged from bottom to top; the source electrode and the drain electrode are arranged on the upper surface of the epitaxial layer, and ohmic contact is formed between the source electrode and the epitaxial layer and between the source electrode and the drain electrode and between the source electrode and the epitaxial layer; a gate dielectric is arranged on the upper surface of the non-ohmic contact area of the epitaxial layer; the gate electrode is arranged on the upper surface of the gate dielectric; a high-resistance layer is arranged in a non-ohmic contact area between the gate electrode and the drain electrode in the epitaxial layer; the high-resistance layer comprises N-type gallium oxide, and the carrier concentration comprises 0-1 multiplied by 10 16 cm ‑3 。
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a MOSFET with a high-resistance layer, a preparation method of the MOSFET and a power transistor module.
Background
A MOSFET (metal oxide semiconductor type field effect transistor) is a switching device that can control the magnitude of current between a drain and a source by changing a voltage applied to a gate. Key performance indicators for MOSFETs include on-resistance, on-state output current, off-state leakage current, and breakdown voltage. However, the on-state and off-state characteristics of the device are mutually restricted, and the improvement of the off-state characteristic usually comes at the cost of the reduction of the on-state characteristic. It is difficult to manufacture a device having a high power quality factor with low on-resistance, high output current, high breakdown voltage, and low leakage current at the same time.
Gallium oxide is a wide bandgap semiconductor with a critical breakdown field strength far higher than that of conventional semiconductors. The MOSFET based on gallium oxide is expected to be applied to the fields of high-voltage direct current power supply, electric automobiles and the like in the future, and higher-performance power processing capacity is achieved. In order to fully exert the material advantages of gallium oxide, obtain high-performance gallium oxide power MOSFET, find better on characteristic and turn-off characteristic compromise scheme become necessary.
In the design of the MOSFET, increasing the distance between the drain and the gate of the MOSFET and reducing the doping concentration of the channel can reduce leakage current and improve breakdown voltage, but the on-resistance is obviously increased, the on-loss is increased, and even the power quality factor of the device is reduced. Decreasing the gate-drain spacing, increasing the channel doping concentration, if considered from the standpoint of reducing the on-resistance alone, may also result in a decrease in the power quality factor. In addition, in order to prevent unexpected current paths in the circuit when the circuit fails in practical application, the normally-off MOSFET is more likely to be practically applied. However, due to the lack of a p-type doping method for gallium oxide, normally-off gallium oxide MOSFETs are not easily realized. The current normally-off gallium oxide MOSFET is usually realized at the cost of reducing output current and increasing on-resistance.
Disclosure of Invention
In view of the above, the present invention provides a MOSFET with a high-resistance layer, a method for manufacturing the MOSFET, and a power transistor module, so as to at least partially solve at least one of the above-mentioned problems.
In order to achieve the above object, as one aspect of the present invention, there is provided a MOSFET with a high-resistance layer, comprising: a semi-insulating substrate layer, a buffer layer, an epitaxial layer and a high-resistance layer; a source electrode, a drain electrode, and a gate electrode; the semi-insulating substrate layer, the buffer layer and the epitaxial layer are sequentially arranged from bottom to top; the source electrode and the drain electrode are arranged on the upper surface of the epitaxial layer, and ohmic contact is formed between the source electrode and the epitaxial layer and between the source electrode and the drain electrode and between the source electrode and the epitaxial layer; a gate dielectric is arranged on the upper surface of the non-ohmic contact area of the epitaxial layer; the gate electrode is arranged on the upper surface of the gate dielectric; a high-resistance layer is arranged in a non-ohmic contact area between the gate electrode and the drain electrode in the epitaxial layer; the high-resistance layer comprises N-type gallium oxide, and the carrier concentration comprises 0-1 multiplied by 10 16 cm -3 。
According to the embodiment of the invention, the doping impurities of the semi-insulating substrate layer comprise any one of iron and magnesium.
According to an embodiment of the present invention, the carrier concentration of the epitaxial layer includes 1×10 16 cm -3 ～1×10 19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The carrier concentration of the buffer layer includes 1×10 14 cm -3 ～1×10 16 cm -3 。
According to the embodiment of the invention, the source electrode comprises one or more of Ti, al and Au; the drain electrode includes one or more of Ti, al and Au.
According to an embodiment of the invention, the gate electrode includes one or more of Ni, pt, au, ti.
As another aspect of the present invention, the present invention provides a method for preparing the above MOSFET, comprising: a semi-insulating gallium oxide substrate with a buffer layer and an epitaxial layer is adopted, and an insulating layer is grown on the surface to serve as a mask; etching the insulating layer by adopting a photoetching method and a buffer oxide etching method, and only reserving the insulating layer at the reserved positions among the drain electrode, the source electrode and the gate electrode to expose the epitaxial layer between the drain electrode and the gate electrode; adopting a thermal oxidation method to process the exposed epitaxial layer between the drain electrode and the gate electrode to form a high-resistance layer; removing the residual insulating layer by adopting a buffer oxide etching method, growing a source electrode and a drain electrode by utilizing an electron beam evaporation method, and forming ohmic contact by an annealing method; growing gate dielectric on the surfaces of the source electrode, the drain electrode and the epitaxial layer by adopting an atomic layer deposition method; removing the gate dielectric on the upper surface of the source electrode and the drain electrode by adopting a photoetching method and an etching method; and growing a gate electrode on the upper surface of the gate dielectric by adopting an electron beam evaporation method.
According to the embodiment of the invention, the exposed epitaxial layer between the drain electrode and the gate electrode is treated by a thermal oxidation method to form a high-resistance layer, and the exposed epitaxial layer between the drain electrode and the gate electrode is treated by the thermal oxidation method at 900-1200 ℃ in an oxygen atmosphere under 1 standard atmosphere to form the high-resistance layer.
As another aspect of the present invention, the present invention also provides a power transistor module including: the MOSFET and the deep ultraviolet light-emitting diode; the MOSFET is electrically connected with the deep ultraviolet light emitting diode.
According to an embodiment of the present invention, the power transistor module further includes a substrate, wherein the MOSFET and the deep ultraviolet light emitting diode are integrated on the substrate and electrically connected through the metal layer.
As another aspect of the present invention, the present invention also provides a method for controlling the above power transistor module, including: and according to the on or off state of the MOSFET, controlling the on or off of the deep ultraviolet light emitting diode loop by adopting a voltage control switch. When the MOSFET is in a conducting state, the voltage control switch is closed, the deep ultraviolet light emitting diode loop is conducted, the deep ultraviolet light emitting diode is turned on and irradiates the MOSFET, so that electron hole pairs are generated in the MOSFET, the resistivity is reduced, and the on-resistance of the power transistor module is reduced. When the MOSFET is in an off state, the voltage control switch is turned off, the deep ultraviolet light emitting diode loop is turned on and off, the deep ultraviolet light emitting diode is turned off, the resistivity of the MOSFET is increased, and the leakage current of the power transistor is reduced.
The MOSFET with the high-resistance layer is prepared in the voltage-resistant area of the MOSFET, has very low carrier concentration, increases the resistance of the MOSFET, reduces the leakage current of the MOSFET and improves the breakdown voltage of the MOSFET. Meanwhile, the electron concentration in a channel can be obviously reduced when the gate voltage is zero by introducing the high-resistance layer, and the normally-off gallium oxide MOSFET is realized.
Drawings
FIGS. 1-7 schematically illustrate process flow diagrams of a method of fabricating a MOSFET with a high resistance layer;
fig. 8 schematically shows a schematic structure of a MOSFET with a high-resistance layer;
fig. 9 schematically shows a schematic composition of a power transistor module;
fig. 10 schematically shows a circuit schematic of a power transistor module;
fig. 11 schematically shows a schematic structural diagram of a power transistor module integrated by a metal layer;
fig. 12 schematically illustrates a schematic of packaging a discrete high resistance MOSFET in the same package as a deep ultraviolet light emitting diode.
Detailed Description
The present invention will be further described in detail below with reference to specific embodiments and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent.
The invention provides a MOSFET with a high-resistance layer, and fig. 8 schematically shows a structural schematic diagram of the MOSFET with the high-resistance layer. The semiconductor device comprises a semi-insulating substrate layer 1, a buffer layer 2, an epitaxial layer 3 and a high-resistance layer 4; a source electrode 5, a drain electrode 6, and a gate electrode 7; the semi-insulating substrate layer 1, the buffer layer 2 and the epitaxial layer 3 are sequentially arranged from bottom to top; the source electrode 5 and the drain electrode 6 are arranged on the upper surface of the epitaxial layer 3, and ohmic contact is formed between the source electrode 5 and the drain electrode 6 and the epitaxial layer 3; a gate dielectric 8 is arranged on the upper surface of the non-ohmic contact area of the epitaxial layer 3; the gate electrode 7 is arranged on the upper surface of the gate dielectric 8; a high-resistance layer 4 is arranged in a non-ohmic contact area between the gate electrode 7 and the drain electrode 8 in the epitaxial layer 3; the high-resistance layer 4 comprises N-type gallium oxide, and the carrier concentration comprises 0-1 multiplied by 10 16 cm -3 。
In the embodiment of the invention, the high-resistance layer is prepared in the voltage-resistant area of the MOSFET, the carrier concentration of the high-resistance layer is very low, the resistance of the MOSFET is increased, the leakage current of the MOSFET is reduced, and the breakdown voltage of the MOSFET is improved. Meanwhile, the electron concentration in a channel can be obviously reduced when the gate voltage is zero by introducing the high-resistance layer, and the normally-off gallium oxide MOSFET is realized.
According to the embodiment of the invention, the doping impurities of the semi-insulating substrate layer comprise any one of iron and magnesium.
According to an embodiment of the present invention, the carrier concentration of the epitaxial layer includes 1×10 16 cm -3 ～1×10 19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The carrier concentration of the buffer layer includes 1×10 14 cm -3 ～1×10 16 cm -3 。
In the embodiment of the invention, the carrier concentration of the epitaxial layer is higher than that of the buffer layer, and the carrier concentration of the high-resistance layer is similar to or lower than that of the buffer layer.
According to the embodiment of the invention, the source electrode comprises one or more of Ti, al and Au; the drain electrode includes one or more of Ti, al and Au.
According to an embodiment of the invention, the gate electrode includes one or more of Ni, pt, au, ti.
As another aspect of the present invention, the present invention provides a method of manufacturing the above MOSFET, as shown in fig. 1 to 7, comprising: a semi-insulating gallium oxide substrate 1 with a buffer layer 2 and an epitaxial layer 3 is adopted, and an insulating layer 9 is grown on the surface to be used as a mask; etching the insulating layer 9 by adopting a photoetching method and a buffer oxide etching method, and only reserving the insulating layer 9 at the reserved positions among the drain electrode 6, the source electrode 5 and the gate electrode 7 to expose the epitaxial layer 3 between the drain electrode 6 and the gate electrode 7; the epitaxial layer 3 exposed between the drain electrode 6 and the gate electrode 7 is treated by adopting a thermal oxidation method to form a high-resistance layer 4; removing the residual insulating layer 9 by adopting a buffer oxide etching method, growing the source electrode 5 and the drain electrode 6 by utilizing an electron beam evaporation method, and forming ohmic contact by utilizing an annealing method; an atomic layer deposition method is adopted to grow a gate dielectric 8 on the surfaces of the source electrode 5, the drain electrode 6 and the high-resistance layer 4; removing the gate dielectric 8 on the upper surfaces of the source electrode 5 and the drain electrode 6 by adopting a photoetching method and an etching method; and growing a gate electrode 7 on the upper surface of the gate dielectric 8 by adopting an electron beam evaporation method.
In the embodiment of the invention, the semi-insulating gallium oxide substrate with the buffer layer and the epitaxial layer can be directly adopted, and the gallium oxide substrate doped with higher concentration or the semi-insulating gallium oxide substrate only with the epitaxial layer can also be selected.
According to an embodiment of the present invention, the insulating layer 9 is grown on the surface by ion-enhanced chemical vapor deposition (PECVD) of a material selected from the group consisting of, but not limited to, si 3 N 4 Insulating layer growth methods include, but are not limited to, ion-enhanced chemical vapor deposition (PECVD).
According to the embodiment of the invention, the epitaxial layer 3 exposed between the drain electrode 6 and the gate electrode 7 is treated by a thermal oxidation method to form the high-resistance layer 4, and the epitaxial layer 3 exposed between the drain electrode 6 and the gate electrode 7 is treated by the thermal oxidation method in an oxygen atmosphere at 900-1200 ℃ and 1 standard atmosphere to form the high-resistance layer 4.
In the embodiment of the invention, the realization idea of forming the high-resistance layer is to reduce the electron concentration of the gallium oxide epitaxial layer doped with higher concentration, and other methods capable of reducing the electron concentration in the gallium oxide epitaxial layer can be adopted to prepare the high-resistance layer, for example: halide Vapor Phase Epitaxy (HVPE) method, molecular Beam Epitaxy (MBE) method, metal Organic Chemical Vapor Deposition (MOCVD) method, pulsed Laser Deposition (PLD) method, magnetron sputtering method.
According to the embodiment of the invention, ti/Au laminated metal is used as a source electrode and a drain electrode, and is grown by an electron beam evaporation method, and N is used at 470 DEG C 2 Annealing for 1min under atmosphere to form ohmic contact between the source electrode 5 and the drain electrode 6 and the upper surface of the epitaxial layer 3.
In the embodiment of the invention, because the source electrode and the drain electrode can adopt different metal materials, the ohmic contact process parameters, such as annealing temperature, annealing time and gas atmosphere, can be properly adjusted according to the actually adopted metal materials.
According to the embodiment of the invention, al is used 2 O 3 As the gate dielectric, for example, an atomic layer deposition method is adopted to grow Al on the surfaces of the source electrode 5, the drain electrode 6 and the high-resistance layer 4 2 O 3 A film. Removing Al on the upper surface of the source electrode 5 and the drain electrode 6 by adopting a photoetching method and an etching method 2 O 3 A film.
According to the embodiment of the invention, taking Ni/Au laminated metal as a gate electrode as an example, a gate electrode 7 is grown on the upper surface of a gate dielectric 8 by adopting an electron beam evaporation method.
The electrode growth method in the embodiment of the invention comprises, but is not limited to, an electron beam evaporation method, and magnetron sputtering and other suitable metal coating processes can also be adopted.
As another aspect of the present invention, the present invention also provides a power transistor module, fig. 9 schematically illustrates a composition diagram of the power transistor module, and fig. 10 schematically illustrates a circuit diagram of the power transistor module. As shown in fig. 9 and 10, the device includes: the MOSFET (M1) with the high-resistance layer and the deep ultraviolet light-emitting diode D2; the MOSFET (M1) with the high-resistance layer is electrically connected with the deep ultraviolet light emitting diode D2.
By applying deep ultraviolet light when the MOSFET with the high-resistance layer works in the on state, the electron concentration in the MOSFET channel with the high-resistance layer can be increased, the on-resistance of the MOSFET channel with the high-resistance layer can be reduced, and the output current can be increased. When the MOSFET with the high-resistance layer is turned off, the deep ultraviolet light emitting diode is also kept in an off state, and the power transistor module can keep excellent voltage-withstanding characteristics of the MOSFET with the high-resistance layer.
In the embodiment of the present invention, including but not limited to, the MOSFET with high-resistance layer and the deep ultraviolet light emitting diode are assembled on the same circuit board, and the discrete MOSFET (M1) with high-resistance layer and the deep ultraviolet light emitting diode D2 can be packaged in the same package after being electrically connected by the circuit of fig. 10, as shown in fig. 12.
In the embodiment of the invention, the mode of the MOSFET with the high-resistance layer and the deep ultraviolet light-emitting diode group power transistor can also be realized by adopting the integration of bare chips in the package, the integration between the packages and the utilization of the external ultraviolet light source and the external ultraviolet irradiation when the MOSFET with the high-resistance layer is used.
In the embodiment of the invention, the power transistor is integrated by adopting the bare chip in the package in the following manner: the unpackaged MOSFET with high resistance layer and unpackaged deep ultraviolet light emitting diode are stacked, connected by via hole, metal layer, etc. according to the circuit structure shown in fig. 10, and then packaged in the same package.
In the embodiment of the invention, the power transistor is integrated between the packages in the following manner: the packaged MOSFET with high resistance layer and the packaged deep ultraviolet light emitting diode are connected on the substrate according to the circuit structure shown in fig. 10, and the electrical connection shown in fig. 10 can also be realized by using a package stacking mode.
Fig. 11 schematically shows a schematic structural diagram of a power transistor integrated by a metal layer, according to an embodiment of the present invention. As shown in fig. 11, the deep ultraviolet light emitting diode adopts the following structure: the p-GaN hole accumulation layer 01A, p-AlGaN hole accumulation layer 01B, alGaN quantum well active layer 02, the n-AlGaN layer 03, the AlN/AlGaN superlattice buffer layer 04 and the AlN layer 05 are sequentially arranged from top to bottom, and an anode 06 and a cathode 07 respectively adopt a Ni/Au lamination and a Ti/Al/Ti/Au lamination. The MOSFET (M1) is manufactured by the method of the present invention, and the MOSFET (M1) and the deep ultraviolet light emitting diode D2 are integrated on the substrate 11, and are electrically connected through the metal layer.
In the embodiment of the invention, the materials and structures adopted by the deep ultraviolet light emitting diode are not limited to the common structures mentioned in the embodiment of the invention.
In the embodiment of the invention, the power transistor module comprises, but is not limited to, a deep ultraviolet light emitting diode, and the light emitting diode with a proper wave band can be selected according to the different growth modes of gallium oxide materials and the forbidden band width of the gallium oxide materials.
As another aspect of the present invention, the present invention also provides a method for controlling the above power transistor module, as shown in fig. 10, including: according to the on or off state of the MOSFET (M1), a voltage control switch K1 is adopted to control the on or off of a deep ultraviolet light emitting diode (D2) loop.
In the embodiment of the invention, a control signal is led out from a circuit of the MOSFET (M1) to control the on-off of a deep ultraviolet light emitting diode D2, wherein the control signal comprises but is not limited to a voltage signal.
Taking a voltage signal as an example, when the voltage difference between the gate electrode and the source electrode of the MOSFET (M1) is greater than the threshold voltage, the MOSFET (M1) is in a conducting state, the voltage control switch K1 is closed, the deep ultraviolet light emitting diode D2 is turned on and irradiates the MOSFET (M1), and after the high-resistance layer of the MOSFET (M1) absorbs the deep ultraviolet light, electron hole pairs are generated inside, the resistivity is reduced, the on-resistance of the power transistor module is reduced, and the output current is increased.
When the voltage difference between the gate electrode and the source electrode of the MOSFET (M1) is smaller than the threshold voltage, the MOSFET (M1) is in an off state, the voltage control switch K1 is turned off, the loop of the deep ultraviolet light emitting diode D2 is turned on and off, the deep ultraviolet light emitting diode D2 is turned off, the resistivity of the MOSFET (M1) is increased, the leakage current of the power transistor is reduced, and the power transistor module bears high voltage by virtue of the MOSFET with the high-resistance layer.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the invention thereto, but to limit the invention thereto, and any modifications, equivalents, improvements and equivalents thereof may be made without departing from the spirit and principles of the invention.
Claims (7)
1. A method of controlling a power transistor module, comprising: a metal oxide semiconductor field effect transistor with a high resistance layer, a substrate and a deep ultraviolet light emitting diode; the metal oxide semiconductor field effect transistor and the deep ultraviolet light emitting diode are integrated on the substrate and are electrically connected through the metal layer;
according to the on or off state of the metal oxide semiconductor type field effect transistor, a voltage control switch is adopted to control the on or off of the deep ultraviolet light emitting diode loop;
when the metal oxide semiconductor type field effect transistor is in a conducting state, the voltage control switch is closed, the deep ultraviolet light emitting diode loop is conducted, the deep ultraviolet light emitting diode is turned on and irradiates the metal oxide semiconductor type field effect transistor, so that electron hole pairs are generated in the metal oxide semiconductor type field effect transistor, the resistivity is reduced, and the on-resistance of the power transistor module is reduced;
when the metal oxide semiconductor type field effect transistor is in an off state, the voltage control switch is turned off, the deep ultraviolet light emitting diode loop is turned on and off, the deep ultraviolet light emitting diode is turned off, the resistivity of the metal oxide semiconductor type field effect transistor is increased, and the leakage current of the power transistor is reduced;
wherein, the metal oxide semiconductor type field effect transistor includes:
a semi-insulating substrate layer, a buffer layer, an epitaxial layer and a high-resistance layer;
a source electrode, a drain electrode, and a gate electrode;
wherein,,
the semi-insulating substrate layer, the buffer layer and the epitaxial layer are sequentially arranged from bottom to top;
the source electrode and the drain electrode are arranged on the upper surface of the epitaxial layer, and ohmic contact is formed between the source electrode and the epitaxial layer and between the drain electrode and the epitaxial layer;
a gate medium is arranged on the upper surface of the non-ohmic contact area of the epitaxial layer;
the gate electrode is arranged on the upper surface of the gate dielectric;
the non-ohmic contact area between the gate electrode and the drain electrode in the epitaxial layer is provided with the high-resistance layer;
the high-resistance layer comprises N-type gallium oxide, and the carrier concentration comprises 0-1 multiplied by 10 16 cm -3 。
2. The method of claim 1, wherein the doping impurities of the semi-insulating substrate layer comprise any one of iron and magnesium.
3. The method of claim 1, wherein the carrier concentration of the epitaxial layer comprises 1 x 10 16 cm -3 ～1×10 19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The carrier concentration of the buffer layer comprises 1×10 14 cm -3 ～1×10 16 cm -3 。
4. The method of claim 1, wherein the source electrode comprises one or more of Ti, al, au; the drain electrode comprises one or more of Ti, al and Au.
5. The method of claim 1, wherein the gate electrode comprises one or more of Ni, pt, au, ti.
6. The method of claim 1, wherein the method for fabricating a metal oxide semiconductor field effect transistor comprises:
a semi-insulating gallium oxide substrate with a buffer layer and an epitaxial layer is adopted, and an insulating layer is grown on the surface to serve as a mask;
etching the insulating layer by adopting a photoetching method and a buffer oxide etching method, and only reserving the insulating layer at reserved positions among the drain electrode, the source electrode and the gate electrode to expose the epitaxial layer between the drain electrode and the gate electrode;
the epitaxial layer exposed between the drain electrode and the gate electrode is treated by adopting a thermal oxidation method to form a high-resistance layer;
removing the residual insulating layer by adopting a buffer oxide etching method, growing the source electrode and the drain electrode by adopting an electron beam evaporation method, and forming ohmic contact by adopting an annealing method;
growing gate dielectric on the surfaces of the source electrode, the drain electrode and the high-resistance layer by adopting an atomic layer deposition method;
removing the gate dielectric on the upper surfaces of the source electrode and the drain electrode by adopting a photoetching method and an etching method;
and growing a gate electrode on the upper surface of the gate dielectric by adopting an electron beam evaporation method.
7. The method of claim 6, wherein the thermally oxidizing the exposed epitaxial layer between the drain electrode and the gate electrode to form a high-resistance layer comprises thermally oxidizing the exposed epitaxial layer between the drain electrode and the gate electrode at 900-1200 ℃ in an oxygen atmosphere at 1 standard atmosphere to form a high-resistance layer.
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| CN110164769B (en) * | 2019-06-20 | 2021-08-31 | 中国电子科技集团公司第十三研究所 | Gallium oxide field effect transistor and preparation method thereof |
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