CN113299756A - MOSFET with high-resistance layer, preparation method thereof and power transistor module - Google Patents
MOSFET with high-resistance layer, preparation method thereof and power transistor module Download PDFInfo
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- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910001195 gallium oxide Inorganic materials 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims description 56
- 230000005669 field effect Effects 0.000 claims description 16
- 229910044991 metal oxide Inorganic materials 0.000 claims description 16
- 150000004706 metal oxides Chemical class 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
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- 229910052737 gold Inorganic materials 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
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- 238000001259 photo etching Methods 0.000 claims description 7
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 229910052742 iron Inorganic materials 0.000 claims description 3
- 229910052749 magnesium Inorganic materials 0.000 claims description 3
- 239000011777 magnesium Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims 1
- 239000002245 particle Substances 0.000 abstract 1
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- 239000000463 material Substances 0.000 description 5
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- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 3
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- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000004549 pulsed laser deposition Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
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- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
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Abstract
The invention discloses a MOSFET with a high-resistance layer, a preparation method thereof and a power transistor module, wherein the MOSFET with the high-resistance layer comprises: the semiconductor device comprises a semi-insulating substrate layer, a buffer layer, an epitaxial layer and a high-resistance layer; a source electrode, a drain electrode, a gate electrode; the semi-insulating substrate layer, the buffer layer and the epitaxial layer are sequentially arranged from bottom to top; the source electrode and the drain electrode are arranged on the upper surface of the epitaxial layer and form ohmic contact with the epitaxial layer; a gate dielectric is arranged on the upper surface of the non-ohmic contact area of the epitaxial layer; the gate electrode is arranged on the upper surface of the gate dielectric; a high-resistance layer is arranged in a non-ohmic contact area between the gate electrode and the drain electrode in the epitaxial layer; the high-resistance layer comprises N-type gallium oxide and carries currentThe concentration of the seed particles is 0 to 1X 1016cm‑3。
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a MOSFET with a high-resistance layer, a preparation method of the MOSFET and a power transistor module.
Background
A MOSFET (metal oxide semiconductor type field effect transistor) is a switching device that can control the magnitude of current between a drain and a source by changing a voltage applied to a gate. Key performance indicators for MOSFETs include on-resistance, on-state output current, off-state leakage current, and breakdown voltage. However, the on-state characteristics and the off-state characteristics of the device are mutually restricted, and the improvement of the off-state characteristics is usually at the expense of the reduction of the on-state characteristics. It is difficult to fabricate devices with high power quality factor that have low on-resistance, large output current, high breakdown voltage, and low leakage current.
Gallium oxide is a wide bandgap semiconductor with much higher critical breakdown field strength than conventional semiconductors. The MOSFET based on gallium oxide is expected to be applied to the fields of high-voltage direct-current power supply, electric automobiles and the like in the future, and the power processing capability with higher performance is realized. In order to fully exert the material advantages of gallium oxide and obtain a high-performance gallium oxide power MOSFET, it is necessary to find a better compromise between on-state characteristics and off-state characteristics.
In the design of the MOSFET, the drain electrode and grid electrode distance of the MOSFET is increased, the channel doping concentration is reduced, the leakage current can be reduced, the breakdown voltage is improved, but the on-resistance is obviously increased, the on-loss is increased, and even the power quality factor of the device is reduced. The power quality factor may also be reduced if the gate-drain spacing is reduced and the channel doping concentration is increased only from the viewpoint of reducing the on-resistance. In addition, in order to prevent the current path from being accidentally generated in the circuit when the circuit fails in practical application, the normally-off MOSFET is more likely to be practically applied. However, normally-off gallium oxide MOSFETs are not easily implemented due to the lack of p-type doping methods for gallium oxide. The current realization of normally-off gallium oxide MOSFET usually costs the reduction of output current and the increase of on-resistance.
Disclosure of Invention
In view of the above, the present invention provides a MOSFET with a high resistance layer, a method for manufacturing the MOSFET, and a power transistor module, so as to at least partially solve at least one of the above technical problems.
In order to achieve the above object, as one aspect of the present invention, there is provided a MOSFET with a high resistance layer, comprising: the semiconductor device comprises a semi-insulating substrate layer, a buffer layer, an epitaxial layer and a high-resistance layer; a source electrode, a drain electrode, a gate electrode; the semi-insulating substrate layer, the buffer layer and the epitaxial layer are sequentially arranged from bottom to top; the source electrode and the drain electrode are arranged on the upper surface of the epitaxial layer and form ohmic contact with the epitaxial layer; a gate dielectric is arranged on the upper surface of the non-ohmic contact area of the epitaxial layer; the gate electrode is arranged on the upper surface of the gate dielectric; a high-resistance layer is arranged in a non-ohmic contact area between the gate electrode and the drain electrode in the epitaxial layer; the high-resistance layer comprises N-type gallium oxide and has a carrier concentration of 0-1 × 1016cm-3。
According to the embodiment of the invention, the doping impurities of the semi-insulating substrate layer comprise any one of iron and magnesium.
According to the embodiment of the invention, the carrier concentration of the epitaxial layer comprises 1 × 1016cm-3～1×1019cm-3(ii) a The carrier concentration of the buffer layer comprises 1 × 1014cm-3～1×1016cm-3。
According to the embodiment of the invention, the source electrode comprises one or more of Ti, Al and Au; the drain electrode comprises one or more of Ti, Al and Au.
According to an embodiment of the invention, the gate electrode comprises one or more of Ni, Pt, Au, Ti.
As another aspect of the present invention, the present invention provides a method of manufacturing the above MOSFET, comprising: adopting a semi-insulating gallium oxide substrate with a buffer layer and an epitaxial layer, and growing an insulating layer on the surface of the semi-insulating gallium oxide substrate to be used as a mask; etching the insulating layer by adopting a photoetching method and a buffer oxide etching method, only reserving the insulating layer at the reserved positions among the drain electrode, the source electrode and the gate electrode, and exposing the epitaxial layer between the drain electrode and the gate electrode; processing the epitaxial layer exposed between the drain electrode and the gate electrode by adopting a thermal oxidation method to form a high-resistance layer; removing the residual insulating layer by adopting a buffer oxide etching method, growing a source electrode and a drain electrode by using an electron beam evaporation method, and forming ohmic contact by an annealing method; growing a gate medium on the surfaces of the source electrode, the drain electrode and the epitaxial layer by adopting an atomic layer deposition method; removing the gate dielectric on the upper surfaces of the source electrode and the drain electrode by adopting a photoetching method and an etching method; and growing a gate electrode on the upper surface of the gate dielectric by adopting an electron beam evaporation method.
According to the embodiment of the invention, the epitaxial layer exposed between the drain electrode and the gate electrode is processed by adopting a thermal oxidation method to form the high-resistance layer, and the method comprises the step of processing the epitaxial layer exposed between the drain electrode and the gate electrode by adopting the thermal oxidation method at 900-1200 ℃ in 1 oxygen atmosphere under standard atmospheric pressure to form the high-resistance layer.
As another aspect of the present invention, the present invention also provides a power transistor module, comprising: the MOSFET and deep ultraviolet light emitting diode described above; the MOSFET is electrically connected with the deep ultraviolet light emitting diode.
According to the embodiment of the invention, the power transistor module further comprises a substrate, wherein the MOSFET and the deep ultraviolet light emitting diode are integrated on the substrate and electrically connected through the metal layer.
As another aspect of the present invention, the present invention also provides a method of controlling the above power transistor module, comprising: and controlling the on-off of the deep ultraviolet light-emitting diode loop by adopting a voltage control switch according to the on-off state of the MOSFET. When the MOSFET is in a conducting state, the voltage control switch is closed, the deep ultraviolet light emitting diode loop is conducted, and the deep ultraviolet light emitting diode is started and irradiates the MOSFET, so that electron hole pairs are generated inside the MOSFET, the resistivity is reduced, and the conducting resistance of the power transistor module is reduced. When the MOSFET is in a turn-off state, the voltage control switch is switched off, the deep ultraviolet light emitting diode loop is switched on and off, the deep ultraviolet light emitting diode is switched off, the resistivity of the MOSFET is increased, and the leakage current of the power transistor is reduced.
According to the MOSFET with the high-resistance layer, the high-resistance layer is prepared in the voltage-resistant area of the MOSFET, the carrier concentration of the high-resistance layer is very low, the resistance of the MOSFET is increased, the leakage current of the MOSFET is reduced, and the breakdown voltage of the MOSFET is improved. Meanwhile, the introduction of the high-resistance layer can obviously reduce the electron concentration in the channel at zero gate voltage, and a normally-off gallium oxide MOSFET is realized.
Drawings
Fig. 1-7 schematically illustrate process flow diagrams of a method of fabricating a MOSFET with a high resistance layer;
FIG. 8 schematically illustrates a structural view of a MOSFET with a high resistance layer;
FIG. 9 schematically illustrates a schematic composition diagram of a power transistor module;
FIG. 10 schematically illustrates a circuit schematic of a power transistor module;
fig. 11 schematically shows a schematic structural view of a power transistor module integrated by a metal layer;
fig. 12 schematically shows a schematic diagram of packaging a discrete MOSFET with a high resistance layer in the same package as a deep ultraviolet light emitting diode.
Detailed Description
In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.
The invention provides a MOSFET with a high-resistance layer, and a structural schematic diagram of the MOSFET with the high-resistance layer is schematically shown in FIG. 8. The buffer layer structure comprises a semi-insulating substrate layer 1, a buffer layer 2, an epitaxial layer 3 and a high-resistance layer 4; a source electrode 5, a drain electrode 6, a gate electrode 7; wherein, the semi-insulating substrate layer 1, the buffer layer 2 and the epitaxial layer 3 are arranged in sequence from bottom to top; the source electrode 5 and the drain electrode 6 are both arranged on the upper surface of the epitaxial layer 3, and the source electrode 5, the drain electrode 6 and the epitaxial layer 3 form ohmic contact; a gate dielectric 8 is arranged on the upper surface of the non-ohmic contact area of the epitaxial layer 3; the gate electrode 7 is arranged on the upper surface of the gate dielectric 8; a high-resistance layer 4 is arranged in a non-ohmic contact area between the gate electrode 7 and the drain electrode 8 in the epitaxial layer 3; the high-resistance layer 4 comprises N-type gallium oxide and has a carrier concentration of 0-1 × 1016cm-3。
In the embodiment of the invention, the high-resistance layer is prepared in the voltage-resistant area of the MOSFET, the carrier concentration of the high-resistance layer is very low, the resistance of the MOSFET is increased, the leakage current of the MOSFET is reduced, and the breakdown voltage of the MOSFET is improved. Meanwhile, the introduction of the high-resistance layer can obviously reduce the electron concentration in the channel at zero gate voltage, and a normally-off gallium oxide MOSFET is realized.
According to the embodiment of the invention, the doping impurities of the semi-insulating substrate layer comprise any one of iron and magnesium.
According to the embodiment of the invention, the carrier concentration of the epitaxial layer comprises 1 × 1016cm-3～1×1019cm-3(ii) a The carrier concentration of the buffer layer comprises 1 × 1014cm-3～1×1016cm-3。
In the embodiment of the invention, the carrier concentration of the epitaxial layer is higher than that of the buffer layer, and the carrier concentration of the high-resistance layer is similar to or lower than that of the buffer layer.
According to the embodiment of the invention, the source electrode comprises one or more of Ti, Al and Au; the drain electrode comprises one or more of Ti, Al and Au.
According to an embodiment of the invention, the gate electrode comprises one or more of Ni, Pt, Au, Ti.
As another aspect of the present invention, the present invention provides a method of manufacturing the above MOSFET, as shown in fig. 1 to 7, comprising: adopting a semi-insulating gallium oxide substrate 1 with a buffer layer 2 and an epitaxial layer 3, and growing an insulating layer 9 on the surface as a mask; etching the insulating layer 9 by adopting a photoetching method and a buffer oxide etching method, only reserving the drain electrode 6, the source electrode 5, the insulating layer 9 at the reserved position between the source electrode 5 and the gate electrode 7, and exposing the epitaxial layer 3 between the drain electrode 6 and the gate electrode 7; processing the epitaxial layer 3 exposed between the drain electrode 6 and the gate electrode 7 by adopting a thermal oxidation method to form a high-resistance layer 4; removing the residual insulating layer 9 by adopting a buffer oxide etching method, growing the source electrode 5 and the drain electrode 6 by adopting an electron beam evaporation method, and forming ohmic contact by adopting an annealing method; growing a gate medium 8 on the surfaces of the source electrode 5, the drain electrode 6 and the high-resistance layer 4 by adopting an atomic layer deposition method; removing the gate dielectric 8 on the upper surfaces of the source electrode 5 and the drain electrode 6 by adopting a photoetching method and an etching method; and growing a gate electrode 7 on the upper surface of the gate dielectric 8 by adopting an electron beam evaporation method.
In the embodiment of the invention, a semi-insulating gallium oxide substrate with a buffer layer and an epitaxial layer can be directly adopted, and a gallium oxide substrate doped with higher concentration or a semi-insulating gallium oxide substrate with only an epitaxial layer can also be selected.
According to the embodiment of the present invention, the insulating layer 9 is grown on the surface by Plasma Enhanced Chemical Vapor Deposition (PECVD), and the selected material includes but is not limited to Si3N4The insulating layer growth method includes, but is not limited to, a Plasma Enhanced Chemical Vapor Deposition (PECVD) method.
According to the embodiment of the invention, the epitaxial layer 3 exposed between the drain electrode 6 and the gate electrode 7 is processed by a thermal oxidation method to form the high-resistance layer 4, and the thermal oxidation method is adopted to process the epitaxial layer 3 exposed between the drain electrode 6 and the gate electrode 7 in an oxygen atmosphere at 900-1200 ℃ under 1 standard atmospheric pressure to form the high-resistance layer 4.
In the embodiment of the present invention, the idea of forming the high resistance layer is to reduce the electron concentration of the higher-concentration doped gallium oxide epitaxial layer, and other methods that can reduce the electron concentration in the gallium oxide of the epitaxial layer may also be used to prepare the high resistance layer, for example: halide Vapor Phase Epitaxy (HVPE), Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), Pulsed Laser Deposition (PLD), magnetron sputtering.
According to the embodiment of the invention, Ti/Au laminated metal is taken as an example of a source electrode and a drain electrode, the Ti/Au laminated metal is grown by an electron beam evaporation method, and N is performed at 470 DEG C2Annealing for 1min in the atmosphere to form ohmic contacts between the source electrode 5 and the drain electrode 6 and the upper surface of the epitaxial layer 3.
In the embodiment of the invention, different metal materials can be adopted for the source electrode and the drain electrode, and the process parameters of ohmic contact, such as annealing temperature, annealing time and gas atmosphere, can be properly adjusted according to the actually adopted metal materials.
According to the embodiment of the invention, Al is used2O3As an example of the gate dielectric, Al is grown on the surfaces of the source electrode 5, the drain electrode 6 and the high-resistance layer 4 by adopting an atomic layer deposition method2O3A film. Removing Al on the upper surfaces of the source electrode 5 and the drain electrode 6 by adopting a photoetching method and an etching method2O3A film.
According to the embodiment of the invention, taking Ni/Au laminated metal as an example of the gate electrode, the gate electrode 7 is grown on the upper surface of the gate dielectric 8 by adopting an electron beam evaporation method.
The electrode growth method in the embodiment of the present invention includes, but is not limited to, electron beam evaporation, and magnetron sputtering and other suitable metal coating processes may also be used.
As another aspect of the present invention, the present invention further provides a power transistor module, fig. 9 schematically shows a composition schematic diagram of the power transistor module, and fig. 10 schematically shows a circuit schematic diagram of the power transistor module. As shown in fig. 9 and 10, the method includes: the MOSFET (M1) with the high-resistance layer and the deep ultraviolet light emitting diode D2; and the MOSFET (M1) with the high-resistance layer is electrically connected with the deep ultraviolet light-emitting diode D2.
The electron concentration in the MOSFET channel with the high-resistance layer can be improved by applying deep ultraviolet illumination when the MOSFET with the high-resistance layer works in a conducting state, the conducting resistance of the MOSFET is reduced, and the output current is increased. When the MOSFET with the high-resistance layer is turned off, the deep ultraviolet light emitting diode also keeps the turn-off state, and the power transistor module can be ensured to keep the excellent voltage withstanding characteristic of the MOSFET with the high-resistance layer.
In the embodiment of the invention, including but not limited to mounting the MOSFET with the high resistance layer and the deep ultraviolet light emitting diode on the same circuit board, the MOSFET with the high resistance layer (M1) and the deep ultraviolet light emitting diode D2 can be packaged in the same package after being electrically connected by the circuit of fig. 10, as shown in fig. 12.
In the embodiment of the invention, the mode that the MOSFET with the high-resistance layer and the deep ultraviolet light-emitting diode form the power transistor can also be realized by in-package bare chip integration, inter-package integration and utilization of a deep ultraviolet light source and ultraviolet illumination when the MOSFET with the high-resistance layer is used.
In the embodiment of the invention, the mode of integrating the power transistor by using the bare chip in the package is as follows: the unpackaged MOSFET with the high resistance layer and the unpackaged deep ultraviolet light emitting diode are stacked, connected according to the circuit structure shown in fig. 10 through a through hole, a metal layer and the like, and then packed in the same package.
In the embodiment of the invention, the mode of integrating the power transistor between the packages is as follows: the packaged MOSFET with the high resistance layer and the packaged deep ultraviolet light emitting diode are connected on the substrate according to the circuit structure shown in fig. 10, and the electrical connection shown in fig. 10 can also be realized by using a package stacking mode.
Fig. 11 schematically shows a schematic structural diagram of a power transistor integrated through a metal layer, according to an embodiment of the present invention. As shown in fig. 11, the deep ultraviolet light emitting diode adopts the following structure: the quantum well active layer 02 is composed of a p-GaN hole accumulation layer 01A, p and an AlGaN hole accumulation layer 01B, AlGaN in sequence from top to bottom, an n-type AlGaN layer 03, an AlN/AlGaN superlattice buffer layer 04 and an AlN layer 05, wherein an anode 06 and a cathode 07 of the p-GaN hole accumulation layer are respectively a Ni/Au lamination and a Ti/Al/Ti/Au lamination. The MOSFET (M1) is prepared by the method of the invention, and the MOSFET (M1) and the deep ultraviolet light emitting diode D2 are integrated on the substrate 11 and electrically connected through a metal layer.
In the embodiment of the present invention, the materials and structures used for the deep ultraviolet light emitting diode are not limited to the common structures mentioned in the embodiment of the present invention.
In the embodiment of the invention, the power transistor module includes, but is not limited to, a deep ultraviolet light emitting diode, and the light emitting diode with a proper waveband can be selected according to different growth modes of gallium oxide materials and the forbidden bandwidth of the gallium oxide materials.
As another aspect of the present invention, the present invention also provides a method of controlling the above power transistor module, as shown in fig. 10, including: according to the on or off state of the MOSFET (M1), the voltage control switch K1 is used for controlling the on or off of the deep ultraviolet light emitting diode (D2) loop.
In the embodiment of the invention, a control signal is led out from the circuit of the MOSFET (M1) to control the on-off of the path of the deep ultraviolet light-emitting diode D2, and the control signal comprises but is not limited to a voltage signal.
Taking a voltage signal as an example, when the voltage difference between the gate electrode and the source electrode of the MOSFET (M1) is greater than the threshold voltage, the MOSFET (M1) is in a conducting state, the voltage control switch K1 is closed, the deep ultraviolet light emitting diode D2 is in a loop conduction state, the deep ultraviolet light emitting diode D2 is turned on and irradiates the MOSFET (M1), and after the high-resistance layer of the MOSFET (M1) absorbs the deep ultraviolet light, electron hole pairs are generated inside, the resistivity is reduced, the on-resistance of the power transistor module is reduced, and the output current is increased.
When the voltage difference between the gate electrode and the source electrode of the MOSFET (M1) is smaller than the threshold voltage, the MOSFET (M1) is in an off state, the voltage control switch K1 is switched off, the loop of the deep ultraviolet light emitting diode D2 is switched on and off, the deep ultraviolet light emitting diode D2 is switched off, the resistivity of the MOSFET (M1) is increased, the leakage current of the power transistor is reduced, and the power transistor module bears high voltage by virtue of the MOSFET with the high-resistance layer.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A metal oxide semiconductor type field effect transistor with a high resistance layer includes:
the semiconductor device comprises a semi-insulating substrate layer, a buffer layer, an epitaxial layer and a high-resistance layer;
a source electrode, a drain electrode, a gate electrode;
wherein the content of the first and second substances,
the semi-insulating substrate layer, the buffer layer and the epitaxial layer are sequentially arranged from bottom to top;
the source electrode and the drain electrode are arranged on the upper surface of the epitaxial layer, and ohmic contact is formed between the source electrode and the epitaxial layer;
a gate dielectric is arranged on the upper surface of the non-ohmic contact area of the epitaxial layer;
the gate electrode is arranged on the upper surface of the gate dielectric;
the high-resistance layer is arranged in a non-ohmic contact area between the gate electrode and the drain electrode in the epitaxial layer;
the high-resistance layer comprises N-type gallium oxide, and the carrier concentration comprises 0-1 × 1016cm-3。
2. The metal oxide semiconductor type field effect transistor of claim 1, wherein the doping impurity of the semi-insulating substrate layer includes any one of iron and magnesium.
3. The metal oxide semiconductor type field effect transistor of claim 1, wherein a carrier concentration of the epitaxial layer comprises 1 x 1016cm-3～1×1019cm-3(ii) a The carrier concentration of the buffer layer comprises 1 × 1014cm-3～1×1016cm-3。
4. The metal oxide semiconductor type field effect transistor of claim 1, wherein the source electrode comprises one or more of Ti, Al, Au; the drain electrode comprises one or more of Ti, Al and Au.
5. The metal oxide semiconductor type field effect transistor of claim 1, wherein the gate electrode comprises one or more of Ni, Pt, Au, Ti.
6. A method for preparing the metal oxide semiconductor field effect transistor according to any one of claims 1 to 5, comprising:
adopting a semi-insulating gallium oxide substrate with a buffer layer and an epitaxial layer, and growing an insulating layer on the surface of the semi-insulating gallium oxide substrate to be used as a mask;
etching the insulating layer by adopting a photoetching method and a buffer oxide etching method, only reserving the insulating layer at the reserved positions among the drain electrode, the source electrode and the gate electrode, and exposing the epitaxial layer between the drain electrode and the gate electrode;
processing the epitaxial layer exposed between the drain electrode and the gate electrode by adopting a thermal oxidation method to form a high-resistance layer;
removing the residual insulating layer by adopting a buffer oxide etching method, growing the source electrode and the drain electrode by adopting an electron beam evaporation method, and forming ohmic contact by adopting an annealing method;
growing a gate medium on the surface of the source electrode, the drain electrode and the high-resistance layer by adopting an atomic layer deposition method;
removing the gate dielectric on the upper surfaces of the source electrode and the drain electrode by adopting a photoetching method and an etching method;
and growing a gate electrode on the upper surface of the gate dielectric by adopting an electron beam evaporation method.
7. The method of claim 6, wherein the step of processing the exposed epitaxial layer between the drain electrode and the gate electrode by thermal oxidation to form the high-resistance layer comprises the step of processing the exposed epitaxial layer between the drain electrode and the gate electrode by thermal oxidation at 900-1200 ℃ in 1 atmosphere of oxygen under standard atmospheric pressure to form the high-resistance layer.
8. A power transistor module, comprising:
the metal oxide semiconductor field effect transistor and the deep ultraviolet light emitting diode according to any one of claims 1 to 5;
the metal oxide semiconductor field effect transistor is electrically connected with the deep ultraviolet light emitting diode.
9. The power transistor module of claim 8, further comprising:
and the metal oxide semiconductor field effect transistor and the deep ultraviolet light emitting diode are integrated on the substrate and are electrically connected through a metal layer.
10. A method of controlling the power transistor module of claim 8 or 9, comprising:
controlling the on or off of the deep ultraviolet light-emitting diode loop by adopting a voltage control switch according to the on or off state of the metal oxide semiconductor type field effect transistor;
when the metal oxide semiconductor type field effect transistor is in a conducting state, the voltage control switch is closed, the deep ultraviolet light emitting diode loop is conducted, and the deep ultraviolet light emitting diode is started and irradiates the metal oxide semiconductor type field effect transistor, so that electron hole pairs are generated in the metal oxide semiconductor type field effect transistor, the resistivity is reduced, and the conducting resistance of the power transistor module is reduced;
when the metal oxide semiconductor field effect transistor is in a turn-off state, the voltage control switch is switched off, the deep ultraviolet light emitting diode loop is switched on and off, the deep ultraviolet light emitting diode is switched off, the resistivity of the metal oxide semiconductor field effect transistor is increased, and the leakage current of the power transistor is reduced.
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