CN110164769A - Gallium oxide field effect transistor and preparation method thereof - Google Patents
Gallium oxide field effect transistor and preparation method thereof Download PDFInfo
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- CN110164769A CN110164769A CN201910537173.XA CN201910537173A CN110164769A CN 110164769 A CN110164769 A CN 110164769A CN 201910537173 A CN201910537173 A CN 201910537173A CN 110164769 A CN110164769 A CN 110164769A
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- 229910001195 gallium oxide Inorganic materials 0.000 title claims abstract description 145
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 title claims abstract description 144
- 238000002360 preparation method Methods 0.000 title claims abstract description 23
- 238000002353 field-effect transistor method Methods 0.000 title abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 29
- 108090000723 Insulin-Like Growth Factor I Proteins 0.000 claims abstract description 7
- 102000013275 Somatomedins Human genes 0.000 claims abstract description 7
- 230000005669 field effect Effects 0.000 claims description 34
- 238000000137 annealing Methods 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052681 coesite Inorganic materials 0.000 claims description 8
- 229910052906 cristobalite Inorganic materials 0.000 claims description 8
- 238000005516 engineering process Methods 0.000 claims description 8
- 229910052682 stishovite Inorganic materials 0.000 claims description 8
- 229910052905 tridymite Inorganic materials 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 229910001020 Au alloy Inorganic materials 0.000 claims description 6
- CPLXHLVBOLITMK-UHFFFAOYSA-N Magnesium oxide Chemical compound [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 238000005260 corrosion Methods 0.000 claims description 4
- 230000007797 corrosion Effects 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 3
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 3
- 239000000395 magnesium oxide Substances 0.000 claims description 3
- 229910052594 sapphire Inorganic materials 0.000 claims description 3
- 239000010980 sapphire Substances 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 13
- 239000004065 semiconductor Substances 0.000 abstract description 7
- 239000000463 material Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 description 3
- 241001354791 Baliga Species 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000002178 crystalline material Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- -1 gallium oxide metal-oxide Chemical class 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
- H01L21/477—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The present invention relates to semiconductor field, in particular to a kind of gallium oxide field effect transistor and preparation method thereof.This method comprises: extension N-shaped gallium oxide channel layer on substrate；Source electrode and drain electrode is respectively formed on the N-shaped gallium oxide channel layer；The somatomedin layer on the source electrode, drain electrode and N-shaped gallium oxide channel layer；Part corresponding with grid region in the dielectric layer is removed, and carries out the high temperature anneal comprising at least two temperature；Grid is prepared on N-shaped gallium oxide channel layer region corresponding with grid region.The above method can improve the breakdown characteristics of device, and the on state characteristic of retainer member is constant.
Description
Technical field
The present invention relates to semiconductor field, in particular to a kind of gallium oxide field effect transistor and preparation method thereof.
Background technique
Power electronic devices is mainly used for the power change and circuit control of power equipment, is to carry out electric energy (power) processing
Core devices.Environment resource problem faces a severe test within the scope of Present Global, and various countries promulgate energy-saving and emission-reduction policy in succession, makees
For the core devices of the equipment such as industrial plants, household electrical appliance controlling electric energy and conversion, power semiconductor industry will face new skill
Art challenge and opportunity to develop.Silicon-based semiconductor devices are the power devices that current electric system most generally uses, performance phase
Theoretical limit when improving and close to being determined by its material property, so that the growth of its power density is in saturation trend.
It is increasingly becoming the weight of power semiconductor in recent years using gallium oxide as the ultra-wide forbidden band power electronic devices of representative
Development field is wanted, and is expected to certain specific areas and replaces traditional Si base power device.Ultra-wide forbidden band gallium oxide is as a kind of new
Semiconductor material, disruptive field intensity, Bali add (Baliga) figure of merit and in terms of advantage it is prominent.It generallys use in the world bar
Benefit plus (Baliga) figure of merit (~ε μ Eb 3) come characterize material be suitble to power device degree.β-Ga2O3Material Bali adds the figure of merit to be
4 times of GaN material are 10 times of SiC material, are 3444 times of Si material.β-Ga2O3Power device and GaN and SiC device phase
With in pressure resistance situation, conducting resistance is lower, and power consumption is smaller, can greatly reduce electric energy loss when device work.
Since 2013 Japanimation Communication Studies mechanism (NICT) develop first gallium oxide metal-oxide semiconductor (MOS)
Field effect transistor (Ga2O3MOSFET) since device, scientific research personnel is by improving Ga2O3Crystalline material quality, optimised devices system
Make technique, including the doping of optimization channel layer, Ohmic contact and the methods of Schottky contacts technique and grid field plate structure, constantly mentions
Rise Ga2O3MOSFET element performance.2016, NICT used Al2O3As medium under grid, and grid field plate structure is combined, preparation
Ga2O3MOSFET element breakdown voltage reaches 750V.2019, ETRI used source field plate structure, while passing through fluorine in test process
Change liquid and completely cut off device air breakdown, device electric breakdown strength reaches 2320V, for report peak at present.
However, Ga reported at present2O3The breakdown voltage and on state characteristic of field effect transistor (FET) device are also remote low
In materials expectations value.
Summary of the invention
In view of this, the embodiment of the invention provides the preparation method and its structure of a kind of gallium oxide field effect transistor,
To solve Ga in the prior art2O3The breakdown voltage and on state characteristic of field effect transistor (FET) device are far below materials expectations value
The problem of.
The first aspect of the embodiment of the present invention provides a kind of preparation method of gallium oxide field effect transistor, comprising:
Extension N-shaped gallium oxide channel layer on substrate；
Source electrode and drain electrode is respectively formed on the N-shaped gallium oxide channel layer；
The somatomedin layer on the source electrode, drain electrode and N-shaped gallium oxide channel layer；
Part corresponding with grid region in the dielectric layer is removed, and is carried out at the high annealing comprising at least two temperature
Reason；
Grid is prepared on N-shaped gallium oxide channel layer region corresponding with grid region.
Optionally, the N-shaped of the extension on substrate gallium oxide channel layer includes:
Undoped gallium oxide layer is formed on the substrate；
N-shaped gallium oxide channel layer is formed on the undoped gallium oxide layer.
Optionally, the substrate is high resistant gallium oxide substrate, semi-insulation SiC substrate, magnesia or Sapphire Substrate.
Optionally, the N-shaped gallium oxide channel layer is realized by doping Si or Sn；
The N-shaped gallium oxide channel layer doping concentration is 1.0 × 1015cm-3To 1.0 × 1020cm-3；
The N-shaped gallium oxide channel layer is with a thickness of 10nm to 1000nm.
It is optionally, described to be respectively formed source electrode and drain electrode on the N-shaped gallium oxide channel layer, comprising:
By high temperature alloy technique or ion implantation technology on the N-shaped gallium oxide channel layer region corresponding with source region
It covers metal layer and forms source electrode, region overlay metal layer corresponding with drain region forms drain electrode on the N-shaped gallium oxide channel layer.
Optionally, the metal layer is Ti/Au alloy or Ti/Al/Ni/Au alloy.
Optionally, the somatomedin layer on the source electrode, drain electrode and N-shaped gallium oxide channel layer, comprising:
SiO2 medium is grown on the source electrode, drain electrode and N-shaped gallium oxide channel layer by pecvd process or sputtering technology
Layer；Wherein, the SiO2 thickness of dielectric layers is 50nm to 3000nm.
Optionally, described to include: by part corresponding with grid region in dielectric layer removal
Corrode part corresponding with grid region in the dielectric layer by dry etch process etching or wet corrosion technique, directly
To the exposing N-shaped gallium oxide channel layer.
Optionally, described includes that the process conditions of the high temperature anneal of at least two temperature include:
The temperature range of the high annealing is 200 DEG C to 900 DEG C；
The time range of the high annealing is 10 seconds to 10 minutes.
Optionally, described include the high temperature anneal of at least two temperature includes the annealing side using high temperature after first low temperature
The annealing way of low temperature after formula, or first high temperature.
Optionally, after the high temperature anneal comprising at least two temperature, the N-shaped gallium oxide channel layer and grid region
Corresponding exposed region is low electron concentration region, and electron concentration is from the inside to upper surface of the N-shaped gallium oxide channel layer
Successively reduce.
The second aspect of the embodiment of the present invention provides a kind of gallium oxide field effect transistor, comprising:
Substrate；
N-shaped gallium oxide channel layer is formed over the substrate；Wherein, corresponding with grid region in the N-shaped gallium oxide channel layer
Region be formed with low electron concentration region；
Source electrode and drain electrode is respectively formed on the corresponding region on the N-shaped gallium oxide channel layer；
Dielectric layer, be formed on the source electrode, in the drain electrode and on the N-shaped gallium oxide channel layer except the low electricity
On region except sub- concentration range；
Grid is formed in region corresponding with grid region on the N-shaped gallium oxide channel layer.
Optionally, the gallium oxide field effect transistor further include:
Undoped gallium oxide layer is formed between the substrate and the N-shaped gallium oxide channel layer.
Existing beneficial effect is the embodiment of the present invention compared with prior art: the embodiment of the present invention is preparing gallium oxide field
When effect transistor, by removing part corresponding with grid region in dielectric layer, and the high temperature comprising at least two temperature is carried out
Annealing makes N-shaped gallium oxide channel layer exposed region corresponding with grid region form low electron concentration region, and electron concentration from
The inside of N-shaped gallium oxide channel layer is successively reduced to upper surface.By reducing N-shaped gallium oxide channel layer and grid region corresponding region
Electron concentration can improve the breakdown characteristics of device, and the on state characteristic of retainer member is constant, and electron concentration is from N-shaped gallium oxide
The inside of channel layer successively reduces the breakdown characteristics that can further promote device to upper surface.
Detailed description of the invention
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to embodiment or description of the prior art
Needed in attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description is only of the invention some
Embodiment for those of ordinary skill in the art without any creative labor, can also be according to these
Attached drawing obtains other attached drawings.
Fig. 1 is the preparation method flow diagram of gallium oxide field effect transistor provided in an embodiment of the present invention；
Fig. 2 is the corresponding cross-section structure signal of preparation method of gallium oxide field effect transistor provided in an embodiment of the present invention
Figure；
Fig. 3 is the structural schematic diagram of gallium oxide field effect transistor provided in an embodiment of the present invention.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, attached drawing is compareed below and is combined implements
Example, the present invention is further elaborated.It should be appreciated that specific embodiment described herein is only used to explain this
Invention, is not intended to limit the present invention.
Referring to Figures 1 and 2, Fig. 1 is the preparation method process of gallium oxide field effect transistor provided in an embodiment of the present invention
Schematic diagram, Fig. 2 are the corresponding cross-section structure signals of preparation method of gallium oxide field effect transistor provided in an embodiment of the present invention
Figure.The preparation method of the gallium oxide field effect transistor may include:
Step S101, on substrate extension N-shaped gallium oxide channel layer.
Optionally, the N-shaped of the extension on substrate gallium oxide channel layer may include: formed on substrate 201 it is undoped
Gallium oxide layer；N-shaped gallium oxide channel layer 202 is formed on the undoped gallium oxide layer.
Optionally, the substrate 201 is high resistant gallium oxide substrate, semi-insulation SiC substrate, magnesia or Sapphire Substrate.
Optionally, N-shaped gallium oxide channel layer 202 can be realized by doping Si or Sn；The N-shaped gallium oxide channel layer is mixed
Miscellaneous concentration is 1.0 × 1015cm-3To 1.0 × 1020cm-3；The N-shaped gallium oxide channel layer is with a thickness of 10nm to 1000nm.
Specifically, after forming undoped gallium oxide layer on substrate 201, by the undoped gallium oxide layer
Middle Doped ions concentration is 1.0 × 1015cm-3To 1.0 × 1020cm-3Si or Sn, formed with a thickness of 10nm to 1000nm N-shaped
Gallium oxide channel layer.
Step S102 is respectively formed source electrode and drain electrode on the N-shaped gallium oxide channel layer.
Optionally, described to be respectively formed source electrode and drain electrode on the N-shaped gallium oxide channel layer, it may include: to pass through height
Temperature alloy technique or ion implantation technology the region overlay metal layer corresponding with source region on the N-shaped gallium oxide channel layer are formed
Source electrode, region overlay metal layer corresponding with drain region forms drain electrode on the N-shaped gallium oxide channel layer.
In embodiments of the present invention, it referring to Fig. 2 (1), can be divided in the preparation process of gallium oxide field effect transistor
Three regions, comprising: source region, drain region and grid region；Wherein, the source electrode is grown on the N-shaped gallium oxide channel layer and source region
Corresponding region；The drain electrode is grown in region corresponding with drain region on the N-shaped gallium oxide channel layer；The grid is grown in
Region corresponding with grid region on the N-shaped gallium oxide channel layer.
Specifically, with reference to Fig. 2 (2), passing through high temperature alloy work under the premise of adopting the method as described above for dividing region
Skill or ion implantation technology the region overlay metal layer corresponding with source region on the N-shaped gallium oxide channel layer 202 form source electrode
203, region overlay metal layer corresponding with drain region forms drain electrode 204 on the N-shaped gallium oxide channel layer 202.
Optionally, the metal layer can be Ti/Au alloy or Ti/Al/Ni/Au alloy.
Specifically, being used to prepare source electrode 203 and drain electrode on the gallium oxide channel layer 202 of N-shaped referring to Fig. 2 (2)
204 metal layers covered, can be using metals such as Ti/Au or Ti/Al/Ni/Au.
Step S103, the somatomedin layer on the source electrode, drain electrode and N-shaped gallium oxide channel layer.
Optionally, the somatomedin layer on the source electrode, drain electrode and N-shaped gallium oxide channel layer, may include: to pass through
Pecvd process or sputtering technology grow SiO on the source electrode, drain electrode and N-shaped gallium oxide channel layer2Dielectric layer；Wherein, described
SiO2Thickness of dielectric layers is 50nm to 3000nm.Wherein, dielectric layer can also select SiN or Al2O3Equal dielectric layers.
Specifically, referring to Fig. 2 (3), by pecvd process or sputtering technology in the source electrode 203, drain electrode 204 and N-shaped oxygen
Change and grows SiO on gallium channel layer 2022Dielectric layer 205, SiO2Dielectric layer 205 with a thickness of 50nm to 3000nm.
Step S104 removes part corresponding with grid region in the dielectric layer, and carries out comprising at least two temperature
The high temperature anneal；
Optionally, described remove part corresponding with grid region in the dielectric layer may include: by dry etching work
Skill etching or wet corrosion technique corrode part corresponding with grid region in the dielectric layer, until exposing the N-shaped gallium oxide ditch
Channel layer.
Specifically, corroding SiO using dry etch process etching or wet corrosion technique2Dielectric layer 205 is corresponding with grid region
Part, until expose N-shaped gallium oxide channel layer 202, remove part SiO2Structural representation such as Fig. 2 (4) institute after dielectric layer 205
Show.
Optionally, described include the process conditions of the high temperature anneal of at least two temperature includes: the high annealing
Temperature range be 200 DEG C to 900 DEG C in；The time range of the high annealing is 10 seconds to 10 minutes.
Optionally, described include the high temperature anneal of at least two temperature includes the annealing side using high temperature after first low temperature
The annealing way of low temperature after formula, or first high temperature.
Optionally, after the high temperature anneal comprising at least two temperature, the N-shaped gallium oxide channel layer and grid region
Corresponding exposed region is low electron concentration region, and electron concentration is from the inside to upper surface of the N-shaped gallium oxide channel layer
Successively reduce.
Specifically, since usual channel region can adulterate, such as doping Si, it can make channel that N-type (having more electronics) be presented；If ditch
Channel layer is GaO, and through overdoping, channel region is then rendered as n-GaO；After thermal oxide, the vacancy O in GaO is filled in Si
Vacancy has more electronics to reduce, so that N-type weakens, electron concentration becomes low concentration from high concentration.Reference Fig. 2 (5), will
The sample clean formed after step S103 is clean, is placed in oxygen atmosphere and carries out at the high annealing comprising at least two temperature
It manages, in 200 DEG C to 900 DEG C of temperature range, time range is 10 seconds to 10 minutes, and N-shaped gallium oxide channel layer 202 and figure are got the bid
The corresponding exposed region in the grid region shown forms low electron concentration region 206, and the low electron concentration region 206 of formation is aoxidized from N-shaped
The upper surface of gallium channel layer 202 extends to inside；Using the high temperature anneal of different temperatures so that and electron concentration from N-shaped
The inside of gallium oxide channel layer 202 is successively reduced to upper surface, is more advantageous to promotion breakdown characteristic of device.
Step S105 prepares grid on N-shaped gallium oxide channel layer region corresponding with grid region.
Specifically, preparing grid 207 on the corresponding N-shaped gallium oxide channel layer 202 in grid region as shown in Fig. 2 (6).
For in grid, close to the lower section of drain electrode, there are very strong channel spike electric field, the points in gallium oxide MOSFET element
The intensity of peak electric field is directly related with channel electrons concentration, and spike electric field can be effectively reduced by reducing channel electrons concentration, mentions
Device electric breakdown strength characteristic is risen, but reduces channel electrons concentration and will lead to the conducting resistance increase of device, it is special to the conducting of device
Property is unfavorable.
The embodiment of the present invention is when preparing gallium oxide field effect transistor, by by part corresponding with grid region in dielectric layer
Removal, and the high temperature anneal comprising at least two temperature is carried out, make N-shaped gallium oxide channel layer exposed area corresponding with grid region
Domain forms low electron concentration region；Due to only removing the dielectric layer with grid region corresponding part, so that it is attached only to reduce spike electric field
The electron concentration of near field, avoid device on state characteristic be deteriorated the problem of；It is moved back by the inclusion of the high temperature of at least two temperature
Fire processing, so that electron concentration is successively reduced from the inside of N-shaped gallium oxide channel layer to upper surface, to further improve device
The breakdown voltage characteristics of part.
Corresponding to the production method of the gallium oxide field effect transistor in foregoing embodiments, Fig. 3 shows a kind of gallium oxide
The structural schematic diagram of field effect transistor, referring to Fig. 3, which may include:
Substrate 301；
N-shaped gallium oxide channel layer 302 forms over the substrate 301；Wherein, in the N-shaped gallium oxide channel layer 302
Region corresponding with grid region is formed with low electron concentration region 303；
Source electrode 304 and drain electrode 305, are respectively formed on the corresponding region on the N-shaped gallium oxide channel layer 302；
Dielectric layer 306, be formed on the source electrode 304, it is described drain electrode 305 on and the N-shaped gallium oxide channel layer 302
On on region in addition to the low electron concentration region 303；
Grid 307 is formed in region corresponding with grid region on the N-shaped gallium oxide channel layer 302.
Above-mentioned gallium oxide field effect transistor is formed with low electron concentration region, can improve the breakdown characteristics of device；Institute
It states low electron concentration region and is only formed in N-shaped gallium oxide channel layer region corresponding with grid region, it is dense to avoid reduction channel electrons
It the problem of degree causes the conducting resistance of device to increase, can breakdown voltage constant with the on state characteristic of retainer member and improving device
Characteristic.
Optionally, gallium oxide field effect transistor can also include: undoped gallium oxide layer, be formed in the substrate and
Between the N-shaped gallium oxide channel layer.
Optionally, the grid length is 20nm to 10um.
The forming process of each section in above-mentioned gallium oxide field effect transistor, can be with reference to pair in preceding method embodiment
Process is answered, details are not described herein.
Embodiment described above is only to illustrate the technical solution of the application, rather than its limitations；Although referring to aforementioned reality
Example is applied the application is described in detail, those skilled in the art should understand that: it still can be to aforementioned each
Technical solution documented by embodiment is modified or equivalent replacement of some of the technical features；And these are modified
Or replacement, the spirit and scope of each embodiment technical solution of the application that it does not separate the essence of the corresponding technical solution should all
Comprising within the scope of protection of this application.
Claims (14)
1. a kind of production method of gallium oxide field effect transistor characterized by comprising
Extension N-shaped gallium oxide channel layer on substrate；
Source electrode and drain electrode is respectively formed on the N-shaped gallium oxide channel layer；
The somatomedin layer on the source electrode, drain electrode and N-shaped gallium oxide channel layer；
Part corresponding with grid region in the dielectric layer is removed, and carries out the high temperature anneal comprising at least two temperature；
Grid is prepared on N-shaped gallium oxide channel layer region corresponding with grid region.
2. the preparation method of gallium oxide field effect transistor as described in claim 1, which is characterized in that described outer on substrate
Prolonging N-shaped gallium oxide channel layer includes:
Undoped gallium oxide layer is formed on the substrate；
N-shaped gallium oxide channel layer is formed on the undoped gallium oxide layer.
3. the preparation method of gallium oxide field effect transistor as described in claim 1, which is characterized in that the substrate is high resistant
Gallium oxide substrate, semi-insulation SiC substrate, magnesia or Sapphire Substrate.
4. the preparation method of gallium oxide field effect transistor as described in claim 1, which is characterized in that
The N-shaped gallium oxide channel layer is realized by doping Si or Sn；
The N-shaped gallium oxide channel layer doping concentration is 1.0 × 1015cm-3To 1.0 × 1020cm-3；
The N-shaped gallium oxide channel layer is with a thickness of 10nm to 1000nm.
5. the preparation method of gallium oxide field effect transistor as described in claim 1, which is characterized in that described in the N-shaped
Source electrode and drain electrode is respectively formed on gallium oxide channel layer, comprising:
By high temperature alloy technique or ion implantation technology on the N-shaped gallium oxide channel layer region overlay corresponding with source region
Metal layer forms source electrode, and region overlay metal layer corresponding with drain region forms drain electrode on the N-shaped gallium oxide channel layer.
6. the preparation method of gallium oxide field effect transistor as claimed in claim 5, which is characterized in that the metal layer is
Ti/Au alloy or Ti/Al/Ni/Au alloy.
7. the preparation method of gallium oxide field effect transistor as described in claim 1, which is characterized in that described in the source
Somatomedin layer on pole, drain electrode and N-shaped gallium oxide channel layer, comprising:
SiO2 dielectric layer is grown on the source electrode, drain electrode and N-shaped gallium oxide channel layer by pecvd process or sputtering technology；
Wherein, the SiO2 thickness of dielectric layers is 50nm to 3000nm.
8. the preparation method of gallium oxide field effect transistor as described in claim 1, which is characterized in that described by the medium
Part corresponding with grid region, which removes, in layer includes:
Corrode part corresponding with grid region in the dielectric layer by dry etch process etching or wet corrosion technique, until dew
The N-shaped gallium oxide channel layer out.
9. the preparation method of gallium oxide field effect transistor as claimed in claim 8, which is characterized in that described includes at least two
The process conditions of the high temperature anneal of kind of temperature include:
The temperature range of the high annealing is 200 DEG C to 900 DEG C；
The time range of the high annealing is 10 seconds to 10 minutes.
10. the preparation method of gallium oxide field effect transistor as claimed in claim 9, which is characterized in that described comprising at least
The high temperature anneal of two kinds of temperature includes the annealing side using low temperature after the annealing way of high temperature after first low temperature, or first high temperature
Formula.
11. the preparation method of the gallium oxide field effect transistor as described in claim 9 or 10, which is characterized in that by comprising
After the high temperature anneal of at least two temperature, N-shaped gallium oxide channel layer exposed region corresponding with grid region is low electronics
Concentration range, and electron concentration is successively reduced from the inside of the N-shaped gallium oxide channel layer to upper surface.
12. a kind of gallium oxide field effect transistor characterized by comprising
Substrate；
N-shaped gallium oxide channel layer is formed over the substrate；Wherein, in N-shaped gallium oxide channel layer area corresponding with grid region
Domain is formed with low electron concentration region；
Source electrode and drain electrode is respectively formed on the corresponding region on the N-shaped gallium oxide channel layer；
Dielectric layer, be formed on the source electrode, in the drain electrode and on the N-shaped gallium oxide channel layer except the low electronics is dense
It spends on the region except region；
Grid is formed in region corresponding with grid region on the N-shaped gallium oxide channel layer.
13. gallium oxide field effect transistor as claimed in claim 12, which is characterized in that further include:
Undoped gallium oxide layer is formed between the substrate and the N-shaped gallium oxide channel layer.
14. gallium oxide field effect transistor as claimed in claim 12, which is characterized in that the grid length be 20nm extremely
10um。
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