CN113224153B - 高电子迁移率晶体管及其制作方法 - Google Patents

高电子迁移率晶体管及其制作方法 Download PDF

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CN113224153B
CN113224153B CN202010081655.1A CN202010081655A CN113224153B CN 113224153 B CN113224153 B CN 113224153B CN 202010081655 A CN202010081655 A CN 202010081655A CN 113224153 B CN113224153 B CN 113224153B
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CN113224153A (zh
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苏柏文
张明华
吕水烟
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United Microelectronics Corp
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Abstract

本发明公开一种高电子迁移率晶体管及其制作方法，其中该制作方法为，主要先形成一图案化掩模于一基底上，然后利用图案化掩模去除基底以形成多个隆起部以及一受损层于该等隆起部上，然后去除该受损层，形成一阻障层于隆起部上，形成一P型半导体层于阻障层上，再形成一源极电极以及一漏极电极于P型半导体层两侧。

Description

高电子迁移率晶体管及其制作方法
技术领域
本发明涉及一种高电子迁移率晶体管及其制作方法。
背景技术
以氮化镓基材料(GaN-based materials)为基础的高电子迁移率晶体管具有于电子、机械以及化学等特性上的众多优点，例如宽带隙、高击穿电压、高电子迁移率、大弹性模数(elastic modulus)、高压电与压阻系数(high piezoelectric and piezoresistivecoefficients)等与化学钝性。上述优点使氮化镓基材料可用于如高亮度发光二极管、功率开关元件、调节器、电池保护器、面板显示驱动器、通讯元件等应用的元件的制作。
发明内容
本发明一实施例揭露一种制作高电子迁移率晶体管的方法，其主要先形成一图案化掩模于一基底上，然后利用图案化掩模去除基底以形成多个隆起部以及一受损层于该等隆起部上，然后去除该受损层，形成一阻障层于隆起部上，形成一P型半导体层于阻障层上，再形成一源极电极以及一漏极电极于P型半导体层两侧。
本发明另一实施例揭露一种高电子迁移率晶体管，其主要包含多个隆起部沿着第一方向延伸于一基底上、P型半导体层沿着第二方向延伸于基底上、一阻障层设于基底以及P型半导体层之间以及一源极电极及一漏极电极设于P型半导体层两侧。
附图说明
图1至图7为本发明一实施例制作高电子迁移率晶体管的方法示意图；
图8为本发明一实施例的高电子迁移率晶体管的立体结构示意图。
主要元件符号说明
12:基底
14:缓冲层
16:图案化掩模
18:开口
20:隆起部
22:凹槽
24:受损层
26:阻障层
28:P型半导体层
30:图案化掩模
32:保护层
34:栅极电极
36:源极电极
38:漏极电极
40:栅极结构
具体实施方式
请参照图1，图1为本发明一实施例制作一高电子迁移率晶体管的方法示意图，其中图1中半部为本发明制备高电子迁移率晶体管的一上视图，图1上半部为中半部沿着切线AA’的剖面示意图，图1下半部为中半部沿着切线BB’的剖面示意图。如图1所示，首先提供一基底12，例如一由硅、碳化硅或氧化铝(或可称蓝宝石)所构成的基底，其中基底12可为单层基底、多层基底、梯度基底或上述的组合。依据本发明其他实施例基底12又可包含一硅覆绝缘(silicon-on-insulator,SOI)基底。
然后于基底12上形成一缓冲层14。在一实施例中，缓冲层14包含III-V族半导体例如氮化镓，其厚度可介于0.5微米至10微米之间。在一实施例中，可利用分子束外延制作工艺(molecular-beam epitaxy,MBE)、有机金属气相沉积(metal organic chemical vapordeposition,MOCVD)制作工艺、化学气相沉积(chemical vapor deposition,CVD)制作工艺、氢化物气相外延(hydride vapor phase epitaxy,HVPE)制作工艺或上述组合于基底12上形成缓冲层14。随后形成一图案化掩模16于缓冲层14上，其中图案化掩模16具有多个开口18暴露出部分缓冲层14表面。在本实施例中，图案化掩模16可由图案化光致抗蚀剂或介电材料如氮化硅所构成。
请继续参照图2，图2为接续图1制备高电子迁移率晶体管的方法示意图，其中图2中半部为本发明制备高电子迁移率晶体管的一上视图，图2上半部为中半部沿着切线CC’的剖面示意图，图2下半部为中半部沿着切线DD’的剖面示意图。如图2所示，再利用图案化掩模16为掩模去除部分缓冲层14以形成多个隆起部20或山脊状结构以及多个凹槽22于隆起部20之间，其中隆起部20与凹槽22均沿着一第一方向延伸于基底12上。依据本发明一实施例，利用图案化掩模16去除部分缓冲层14以形成隆起部20及凹槽22的步骤可依据图案化掩模16的材料采用干蚀刻制作工艺或湿蚀刻制作工艺等方式来达成。举例来说，若图案化掩模16是由图案化光致抗蚀剂所构成，可采用干蚀刻制作工艺例如氧气等离子体制作工艺来去除部分缓冲层14以形成隆起部20及凹槽22。另外若图案化掩模16由介电材料如氮化硅所构成，则可采用湿蚀刻制作工艺利用如磷酸等蚀刻配方来去除部分缓冲层14形成隆起部20及凹槽22，这些变化形均属本发明所涵盖的范围。
需注意的是，无论是采用上述干蚀刻制作工艺或湿蚀刻制作工艺于基底12或缓冲层14上形成山脊状的隆起部20，所使用的蚀刻配方均较佳于蚀刻制作工艺过程中损害部分缓冲层14表面，并于形成隆起部20的同时形成一受损层(damaged layer)24于隆起部20表面或更具体而言凹槽22内的隆起部20表面。依据本发明一实施例，受损层24的材料较佳取决于缓冲层14本身所使用的材料，例如本实施例的缓冲层14若由氮化镓所构成，则受损层24则较佳包含氮化镓或更具体而言具有碳键结的氮化镓。另外又需注意的是，由于本实施例所制备的为高电子迁移率晶体管元件，因此在此阶段所形成隆起部20与凹槽22的尺寸规模包括其宽度与深度均远大于一般鳍状结构场效晶体管元件中鳍状结构的宽度与深度规模。例如在本实施例中，凹槽22以及/或隆起部20的宽度较佳大于180纳米或更佳介于180纳米至600纳米，此外凹槽22以及/或隆起部20的深度也较佳大于180纳米或更佳介于180纳米至600纳米。
请继续参照图3，图3为接续图2制备高电子迁移率晶体管的方法示意图，其中图3中半部为本发明制备高电子迁移率晶体管的一上视图，图3上半部为中半部沿着切线EE’的剖面示意图，图3下半部为中半部沿着切线FF’的剖面示意图。如图3所示，接着先去除图案化掩模16，再进行一清洗制作工艺去除所有的受损层24并暴露出凹槽22内的缓冲层14。在本实施例中，清洗制作工艺所使用的清洗溶液可包含但不局限于盐酸(HCl)以及/或硫化铵((NH4)2S)。
请继续参照图4，图4为接续图3制备高电子迁移率晶体管的方法示意图，其中图4中半部为本发明制备高电子迁移率晶体管的一上视图，图4上半部为中半部沿着切线GG’的剖面示意图，图4下半部为中半部沿着切线HH’的剖面示意图。如图4所示，然后全面性形成一阻障层26于隆起部20上。在本实施例中，阻障层较佳包含III-V族半导体例如氮化铝镓(AlxGa1-xN)，其中0<x<1，。如同上述形成缓冲层14的方式，可利用分子束外延制作工艺(molecular-beam epitaxy,MBE)、有机金属气相沉积(metal organic chemical vapordeposition,MOCVD)制作工艺、化学气相沉积(chemical vapor deposition,CVD)制作工艺、氢化物气相外延(hydride vapor phase epitaxy,HVPE)制作工艺或上述组合于隆起部20表面以及凹槽22内形成阻障层26但不填满凹槽22。
请继续参照图5，图5为接续图4制备高电子迁移率晶体管的方法示意图，其中图5中半部为本发明制备高电子迁移率晶体管的一上视图，图5上半部为中半部沿着切线II’的剖面示意图，图5下半部为中半部沿着切线JJ’的剖面示意图。如图5所示，接着先形成一P型半导体层28全面性覆盖于阻障层26表面并填满凹槽22，再形成一图案化掩模30例如一图案化光致抗蚀剂于P型半导体层28上，其中图案化掩模30较佳沿着与隆起部20垂直的方向延伸且图案化掩模30两侧较佳暴露出P型半导体层28。
在一实施例中，P型半导体层28较佳包含P型氮化镓，且可利用分子束外延制作工艺(molecular-beam epitaxy,MBE)、有机金属气相沉积(metal organic chemical vapordeposition,MOCVD)制作工艺、化学气相沉积(chemical vapor deposition,CVD)制作工艺、氢化物气相外延(hydride vapor phase epitaxy,HVPE)制作工艺或上述组合于阻障层26表面形成P型半导体层28。
请继续参照图6，图6为接续图5制备高电子迁移率晶体管的方法示意图，其中图6中半部为本发明制备高电子迁移率晶体管的一上视图，图6上半部为中半部沿着切线KK’的剖面示意图，图6下半部为中半部沿着切线LL’的剖面示意图。如图6所示，然后进行一图案转移制作工艺，例如利用图案化掩模30为掩模去除两侧的P型半导体层28，由此将图案化掩模30的图案转移至P型半导体层28上以形成图案化的P型半导体层28并去除图案化掩模30，其中被图案化的P型半导体层28较佳与图案化掩模30一般沿着与隆起部20垂直的方向延伸于隆起部20上。
请继续参照图7至图8，图7为接续图6制备高电子迁移率晶体管的方法示意图，其中图7中半部为本发明制备高电子迁移率晶体管的一上视图，图7上半部为中半部沿着切线MM’的剖面示意图，图7下半部为中半部沿着切线NN’的剖面示意图，图8则为图7中高电子迁移率晶体管的立体结构示意图。如图7所示，先形成一保护层32于阻障层26及P型半导体层28上，再形成一栅极电极34于P型半导体层28上以及源极电极36与漏极电极38于栅极电极34两侧，其中P型半导体层28与栅极电极34可一同构成一栅极结构40。
在本实施例中，可先进行一光刻暨蚀刻制作工艺去除P型半导体层28上的部分保护层32形成凹槽(图未示)，形成一栅极电极34于凹槽内，去除P型半导体层28两侧的部分保护层32及部分阻障层26形成二凹槽，再分别形成源极电极36与漏极电极38于栅极电极34两侧。需注意的是，本实施例所形成的源极电极36与漏极电极38较佳为插槽(slot)状电极，因此从图7中央的上视图以及图8的立体结构来看源极电极36与漏极电极38较佳沿着与P型半导体层28或栅极电极34相同的方向延伸于P型半导体层28两侧，且其底部较佳同时电连接并接触多根下方的隆起部20，而保护层32则环绕P型半导体层28及源极电极36与漏极电极38周围。
又需注意的是，本实施例中的源极电极36与漏极电极38底部虽直接接触隆起部20或缓冲层14，但不局限于此，依据本发明一实施例又可于图案化保护层32形成源极电极36与漏极电极38时不去除源极电极36与漏极电极38正下方的部分阻障层26，使源极电极36与漏极电极38底部直接接触阻障层26，此变化型也属本发明所涵盖的范围。另外为了更清楚显示栅极结构40、源极电极36以及漏极电极38等元件，图8所揭露的立体结构中较佳省略环绕栅极结构40、源极电极36以及漏极电极38并填满隆起部20之间凹槽22的保护层32。
在本实施例中，栅极电极34、源极电极36以及漏极电极38较佳由金属所构成，其中栅极电极34较佳由萧特基金属所构成而源极电极36与漏极电极38较佳由欧姆接触金属所构成。依据本发明一实施例，栅极电极34、源极电极36及漏极电极38可各自包含金、银、铂、钛、铝、钨、钯或其组合。在一些实施例中，可利用电镀制作工艺、溅镀制作工艺、电阻加热蒸镀制作工艺、电子束蒸镀制作工艺、物理气相沉积(physical vapor deposition,PVD)制作工艺、化学气相沉积制作工艺(chemical vapor deposition,CVD)制作工艺、或上述组合于上述凹槽内形成导电材料，然后再利用单次或多次蚀刻将电极材料图案化以形成栅极电极34、源极电极36以及漏极电极38。至此即完成本发明一实施例的一高电子迁移率晶体管的制作。
一般而言，现行为了提升高电子迁移率晶体管元件的开启电流(Ion)是通过增加栅极电极的整体宽度来达成，而栅极电极整体宽度的增加又意味着元件的整体面积增加进而导致成本提升。为了改善此缺点，本发明主要先利用图案化掩模搭配光刻暨蚀刻于氮化镓所构成的缓冲层甚至基底上形成多个山脊状的隆起部，然后再依序形成一由图案化P型半导体层横跨隆起部作为栅极结构以及源极电极与漏极电极于P型半导体层两侧。依据上述制作工艺本发明所制备的高电子迁移率晶体管可获得更大的有效栅极宽度(effectivegate width)如图7中间上视角度所示与隆起部20呈垂直方向所延伸的栅极宽度W，进而提供更高的开启电流。另外有鉴于去除部分氮化镓所构成的缓冲层或基底以形成山脊状隆起部时易于隆起部侧壁产生形成受损层而影响元件效能，本发明另一实施例可选择于形成P型半导体层或阻障层之前先进行一道额外的清洗制作工艺来去除所有的受损层，由此确保后续完成高电子迁移率晶体管得到稳定的电性表现。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种制作高电子迁移率晶体管(high electron mobility transistor,HEMT)的方法，其特征在于，包含：
形成缓冲层于基底上；
形成图案化掩模于该缓冲层上；
利用该图案化掩模去除该缓冲层以形成多个隆起部以及受损层于该多个隆起部上；
去除该受损层；
形成阻障层于该多个隆起部上；以及
形成P型半导体层于该阻障层上。
2.如权利要求1所述的方法，另包含去除该缓冲层以形成多个凹槽于该多个隆起部之间。
3.如权利要求2所述的方法，其中该多个凹槽宽度大于180纳米。
4.如权利要求2所述的方法，其中该多个凹槽深度大于180纳米。
5.如权利要求2所述的方法，另包含进行一干蚀刻制作工艺去除该缓冲层以形成该多个隆起部以及该多个凹槽。
6.如权利要求2所述的方法，另包含进行一湿蚀刻制作工艺去除该缓冲层以形成该多个隆起部以及该多个凹槽。
7.如权利要求1所述的方法，另包含于去除该受损层之前去除该图案化掩模。
8.如权利要求1所述的方法，其中该受损层包含氮化镓。
9.如权利要求1所述的方法，其中该缓冲层包含氮化镓。
10.如权利要求1所述的方法，其中该阻障层包含AlxGa1-xN，其中0<x<1。
11.如权利要求1所述的方法，其中该P型半导体层包含P型氮化镓。
12.如权利要求1所述的方法，另包含形成一源极电极以及一漏极电极于该P型半导体层两侧。
13.一种高电子迁移率晶体管(high electron mobility transistor,HEMT)，其特征在于，包含：
缓冲层，设于基底上；
多个隆起部，沿着第一方向延伸于该缓冲层上；
P型半导体层，沿着第二方向延伸于该缓冲层上；
阻障层，设于该缓冲层以及该P型半导体层之间，且直接接触该多个隆起部的顶表面和侧壁；以及
源极电极以及漏极电极，设于该P型半导体层两侧，且直接接触该多个隆起部的顶表面。
14.如权利要求13所述的高电子迁移率晶体管，另包含栅极电极，设于该P型半导体层上。
15.如权利要求14所述的高电子迁移率晶体管，其中该栅极电极包含金属。
16.如权利要求13所述的高电子迁移率晶体管，其中该源极电极以及该漏极电极沿着该第二方向延伸。
17.如权利要求13所述的高电子迁移率晶体管，另包含保护层，环绕该P型半导体层并设于该多个隆起部之间。
18.如权利要求13所述的高电子迁移率晶体管，其中该缓冲层包含氮化镓。
19.如权利要求13所述的高电子迁移率晶体管，其中该P型半导体层包含P型氮化镓。
20.如权利要求13所述的高电子迁移率晶体管，其中该阻障层包含AlxGa1-xN，其中0<x<1。
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