CN113964119A - 半导体元件 - Google Patents
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- 239000003990 capacitor Substances 0.000 claims abstract description 109
- 238000002955 isolation Methods 0.000 claims abstract description 79
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 230000004888 barrier function Effects 0.000 claims description 60
- 229910002601 GaN Inorganic materials 0.000 claims description 13
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 9
- 239000010410 layer Substances 0.000 description 187
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- 239000004020 conductor Substances 0.000 description 30
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- 238000005530 etching Methods 0.000 description 15
- 239000011229 interlayer Substances 0.000 description 13
- 238000000206 photolithography Methods 0.000 description 12
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 9
- 238000001451 molecular beam epitaxy Methods 0.000 description 9
- 239000010936 titanium Substances 0.000 description 9
- 229910052719 titanium Inorganic materials 0.000 description 9
- 229910052721 tungsten Inorganic materials 0.000 description 9
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- 238000010586 diagram Methods 0.000 description 8
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 229910052715 tantalum Inorganic materials 0.000 description 6
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
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- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 3
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- 239000010949 copper Substances 0.000 description 3
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000005566 electron beam evaporation Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
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- 229910052758 niobium Inorganic materials 0.000 description 3
- 239000010955 niobium Substances 0.000 description 3
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 229910052594 sapphire Inorganic materials 0.000 description 3
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- 239000010703 silicon Substances 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 3
- -1 tungsten nitride Chemical class 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
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- 230000004048 modification Effects 0.000 description 1
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Abstract
本发明公开一种半导体元件,其主要包含一电子迁移率晶体管(high electron mobility transistor,HEMT)区以及一电容区定义于基底上、一第一平台隔离设于该HEMT区上、一HEMT设于第一平台隔离上、一第二平台隔离设于电容区以及一电容设于第二平台隔离上。半导体元件另包含一缓冲层设于基底、第一平台隔离以及第二平台隔离之间,其中第一平台隔离底部切齐第二平台隔离底部。
Description
技术领域
本发明涉及一种半导体元件,尤其是涉及一种整合电子迁移率晶体管(highelectron mobility transistor,HEMT)以及电容的半导体元件。
背景技术
以氮化镓基材料(GaN-based materials)为基础的高电子迁移率晶体管具有于电子、机械以及化学等特性上的众多优点,例如宽能隙、高击穿电压、高电子迁移率、大弹性模数(elastic modulus)、高压电与压阻系数(high piezoelectric and piezoresistivecoefficients)等与化学钝性。上述优点使氮化镓基材料可用于如高亮度发光二极管、功率开关元件、调节器、电池保护器、面板显示驱动器、通讯元件等应用的元件的制作。
发明内容
本发明一实施例揭露一种半导体元件,其主要包含一电子迁移率晶体管(highelectron mobility transistor,HEMT)区以及一电容区定义于基底上、一第一平台隔离设于该HEMT区上、一HEMT设于第一平台隔离上、一第二平台隔离设于电容区以及一电容设于第二平台隔离上。半导体元件另包含一缓冲层设于基底、第一平台隔离以及第二平台隔离之间,其中第一平台隔离底部切齐第二平台隔离底部。
本发明另一实施例揭露一种半导体元件,其主要一HEMT区以及一电容区定义于基底上、一平台隔离(mesa isolation)设于该HEMT区上、一HEMT设于该平台隔离上、一电容设于该电容区以及一缓冲层设于该平台隔离、该电容以及该基底之间。
本发明又一实施例揭露一种半导体元件,其主要一HEMT区以及一电容区定义于基底上、一平台隔离(mesa isolation)设于该HEMT区上、一HEMT设于该平台隔离上、一硬掩模环绕HEMT并延伸至电容区以及一电容设于硬掩模上。
附图说明
图1至图3为本发明一实施例制作一半导体元件的方法示意图;
图4至图6为本发明一实施例制作一半导体元件的方法示意图;
图7至图9为本发明一实施例制作一半导体元件的方法示意图。
主要元件符号说明
12:基底
14:HEMT区
16:电容区
18:缓冲层
20:阻障层
22:P型半导体层
24:平台隔离
26:平台隔离
28:硬掩模
30:源极电极
32:漏极电极
34:源极电极延伸
36:漏极电极延伸
38:下电极
40:硬掩模
42:电容介电层
44:栅极电极
46:上电极
48:层间介电层
50:接触插塞
52:HEMT
54:电容
具体实施方式
请参照图1至图3,图1至图3为本发明一实施例制作一半导体元件的方法示意图。如图1所示,首先提供一基底12,例如一由硅、碳化硅或氧化铝(或可称蓝宝石)所构成的基底,其中基底12可为单层基底、多层基底、梯度基底或上述的组合。依据本发明其他实施例基底12又可包含一硅覆绝缘(silicon-on-insulator,SOI)基底。然后于基底12上定义出一电子迁移率晶体管(high electron mobility transistor,HEMT)区14以及一电容区16。
然后于基底12表面形成一缓冲层18。在一实施利中,缓冲层18包含III-V族半导体例如氮化镓,其厚度可介于0.5微米至10微米之间。在一实施利中,可利用分子束外延制作工艺(molecular-beam epitaxy,MBE)、有机金属气相沉积(metal organic chemicalvapor deposition,MOCVD)制作工艺、化学气相沉积(chemical vapor deposition,CVD)制作工艺、氢化物气相外延(hydride vapor phase epitaxy,HVPE)制作工艺或上述组合于基底12上形成缓冲层18。
接着形成一阻障层20于缓冲层18表面。在本实施例中阻障层20较佳包含III-V族半导体例如氮化铝镓(AlxGa1-xN),其中0<x<1,x较佳小于等于20%,且阻障层20较佳包含一由外延成长制作工艺所形成的外延层。如同上述形成缓冲层18的方式,可利用分子束外延制作工艺(molecular-beam epitaxy,MBE)、有机金属气相沉积(metal organic chemicalvapor deposition,MOCVD)制作工艺、化学气相沉积(chemical vapor deposition,CVD)制作工艺、氢化物气相外延(hydride vapor phase epitaxy,HVPE)制作工艺或上述组合于缓冲层18上形成阻障层20。需注意的是,本实施例中阻障层20虽直接设置于缓冲层18表面,但依据本发明另一实施例又可选择于缓冲层18与阻障层20之间额外形成一金属氮化层(图未示)包含例如但不局限于氮化铝,此变化型也属本发明所涵盖的范围。
然后形成一P型半导体层22于阻障层20上。在一实施利中,P型半导体层22较佳包含P型氮化镓(pGaN),且可利用分子束外延制作工艺(molecular-beam epitaxy,MBE)、有机金属气相沉积(metal organic chemical vapor deposition,MOCVD)制作工艺、化学气相沉积(chemical vapor deposition,CVD)制作工艺、氢化物气相外延(hydride vaporphase epitaxy,HVPE)制作工艺或上述组合于阻障层20表面形成P型半导体层22。
随后进行一平台隔离(MESA isolation)制作工艺以于HEMT区14以及电容区16分别形成平台隔离24、26,使元件之间可独立运作而不致受到彼此交互影响。在本实施例中,平台隔离制作工艺可利用一光刻暨蚀刻制作工艺图案化或以蚀刻去除部分P型半导体层22、部分阻障层20以及部分缓冲层18,其中被图案化的P型半导体层22、阻障层20以及缓冲层18较佳具有相同宽度且两者之间的边缘较佳相互切齐,而剩余且未被图案化的部分缓冲层18则与基底12包含相同宽度。另外本实施例的各平台隔离24、26较佳包含图案化的缓冲层18,其中图案化的缓冲层18厚度约300纳米,图案化的阻障层20厚度约10纳米,而图案化的P型半导体层22的厚度则约100纳米。
接着如图2所示,先进行一光刻暨蚀刻制作工艺去除HEMT区14的部分P型半导体层22以及电容区16的所有P型半导体层22,使剩余的P型半导体层22仅设于HEMT区14的阻障层20上而电容区16的阻障层20表面则无留下任何P型半导体层22,其中被图案化的P型半导体层22较佳作为后续HEMT元件的部分栅极结构。然后共形地(conformally)形成一硬掩模28于缓冲层18上并覆盖HEMT区14以及电容区16的平台隔离24、26。在本实施例中硬掩模28较佳包含但不局限于氮化硅,且硬掩模28的厚度约略200纳米但不局限于此。
随后进行一道或一道以上光刻暨蚀刻制作工艺去除HEMT区14的部分硬掩模28以及部分阻障层20以形成多个凹槽(图未示),然后形成导电材料于HEMT区14的凹槽内与硬掩模28表面以及电容区16的硬掩模28上,再搭配进行一图案转移制作工艺去除部分导电材料,其中HEMT区14中填入凹槽内的导电材料较佳作为源极电极30以及漏极电极32,HEMT区14设于源极电极30以及漏极电极32上方并延伸至两侧硬掩模28表面的导电材料则作为源极电极延伸34以及漏极电极延伸36,而电容区16中被图案化并覆盖于硬掩模28表面的导电材料则作为电容下电极38。接着形成另一硬掩模40于HEMT区14的硬掩模28表面并延伸至电容区16的电容下电极38上,其中电容区16的硬掩模40较佳作为一电容介电层42。在本实施例中,电容介电层42的厚度约20-100纳米,但不局限于此。
如图3所示,然后进行一道或一道以上光刻暨蚀刻制作工艺去除HEMT区14的部分硬掩模40及部分硬掩模28以形成凹槽(图未示)并暴露出P型半导体层22,形成另一导电材料于HEMT区14的硬掩模40上填满凹槽并覆盖HEMT区14以及电容区16的硬掩模40表面,再搭配进行一图案转移制作工艺去除部分导电材料,其中HEMT区14中填入凹槽内以及设于部分硬掩模40表面的导电材料较佳作为栅极电极44而电容区16中被图案化的导电材料则成为电容上电极46。
在本实施例中,栅极电极44、源极电极30以及漏极电极32较佳由金属所构成,其中栅极电极44较佳由萧特基金属所构成而源极电极30与漏极电极32较佳由欧姆接触金属所构成。依据本发明一实施例,栅极电极44、源极电极30及漏极电极32可各自包含金、银、铂、钛、铝、钨、钯或其组合。在一些实施例中,可利用电镀制作工艺、溅镀制作工艺、电阻加热蒸镀制作工艺、电子束蒸镀制作工艺、物理气相沉积(physical vapor deposition,PVD)制作工艺、化学气相沉积制作工艺(chemical vapor deposition,CVD)制作工艺、或上述组合于上述凹槽内形成导电材料,然后再利用单次或多次蚀刻将电极材料图案化以形成栅极电极44、源极电极30以及漏极电极32。
随后可进行一接触插塞制作工艺形成接触插塞分别电连接HEMT区14的栅极电极44、源极电极30以及漏极电极32以及电容区16的下电极38以及上电极46。在本实施例中,形成接触插塞的方式可先形成一层间介电层48并覆盖HEMT区14以及电容区16的硬掩模40,然后去除部分层间介电层48以及部分硬掩模40形成接触洞(图未示),再依序沉积一阻隔层(图未示)以及一金属层(图未示)并填满接触洞。接着利用一平坦化制作工艺,例如CMP去除部分金属层、部分阻隔层甚至部分层间介电层48,以于接触洞中形成接触插塞50,其中各接触插塞50顶表面较佳与层间介电层48顶表面切齐。在本实施例中,阻隔层较佳选自由钛、钽、氮化钛、氮化钽以及氮化钨所构成的群组,金属层较佳选自由铝、钛、钽、钨、铌、钼以及铜所构成的群组,但不局限于此。
请再参照图3,图3又揭露本发明一实施例的一半导体元件的结构示意图。如图3所示,半导体元件主要包含HEMT区14以及电容区16定义于基底12上、平台隔离24设于HEMT区14、HEMT 52设于平台隔离24上、另一平台隔离26设于电容区16、缓冲层18设于基底12及平台隔离24、26之间以及一电容54设于平台隔离26上,其中平台隔离24底部切齐该平台隔离26底部且两个平台隔离24、26均包含氮化镓。
另外HEMT 52主要包含阻障层20设于平台隔离24上、P型半导体层22设于阻障层20上、栅极电极44设于P型半导体层22上、源极电极30及漏极电极32设于栅极电极44两侧、源极电极延伸34设于源极电极30上、漏极电极延伸36设于漏极电极32上以及硬掩模28设于平台隔离24及平台隔离26上并环绕源极电极30及漏极电极32。
电容54则包含一下电极38设于硬掩模28上、一电容介电层42设于下电极38上并延伸至HEMT区14的硬掩模28顶部及侧壁以及一上电极46设于电容介电层42上,其中下电极38底部切齐源极电极延伸34底部且上电极46顶部切齐栅极电极44顶部。
请参照图4至图6,图4至图6为本发明一实施例制作一高电子迁移率晶体管的方法示意图,其中为了简便说明,本实施例与前述实施例中所揭露的相同元件较佳沿用相同标号。如图4所示,首先提供一基底12,例如一由硅、碳化硅或氧化铝(或可称蓝宝石)所构成的基底,其中基底12可为单层基底、多层基底、梯度基底或上述的组合。依据本发明其他实施例基底12又可包含一硅覆绝缘(silicon-on-insulator,SOI)基底。然后于基底12上定义出一电子迁移率晶体管(high electron mobility transistor,HEMT)区14以及一电容区16。
然后于基底12表面形成一缓冲层18。在一实施利中,缓冲层18包含III-V族半导体例如氮化镓,其厚度可介于0.5微米至10微米之间。在一实施利中,可利用分子束外延制作工艺(molecular-beam epitaxy,MBE)、有机金属气相沉积(metal organic chemicalvapor deposition,MOCVD)制作工艺、化学气相沉积(chemical vapor deposition,CVD)制作工艺、氢化物气相外延(hydride vapor phase epitaxy,HVPE)制作工艺或上述组合于基底12上形成缓冲层18。
接着形成一阻障层20于缓冲层18表面。在本实施例中阻障层20较佳包含III-V族半导体例如氮化铝镓(AlxGa1-xN),其中0<x<1,x较佳小于等于20%,且阻障层20较佳包含一由外延成长制作工艺所形成的外延层。如同上述形成缓冲层18的方式,可利用分子束外延制作工艺(molecular-beam epitaxy,MBE)、有机金属气相沉积(metal organic chemicalvapor deposition,MOCVD)制作工艺、化学气相沉积(chemical vapor deposition,CVD)制作工艺、氢化物气相外延(hydride vapor phase epitaxy,HVPE)制作工艺或上述组合于缓冲层18上形成阻障层20。需注意的是,本实施例中阻障层20虽直接设置于缓冲层18表面,但依据本发明另一实施例又可选择于缓冲层18与阻障层20之间额外形成一金属氮化层(图未示)包含例如但不局限于氮化铝,此变化型也属本发明所涵盖的范围。
然后形成一P型半导体层22于阻障层20上。在一实施利中,P型半导体层22较佳包含P型氮化镓(pGaN),且可利用分子束外延制作工艺(molecular-beam epitaxy,MBE)、有机金属气相沉积(metal organic chemical vapor deposition,MOCVD)制作工艺、化学气相沉积(chemical vapor deposition,CVD)制作工艺、氢化物气相外延(hydride vaporphase epitaxy,HVPE)制作工艺或上述组合于阻障层20表面形成P型半导体层22。
随后进行一平台隔离(MESA isolation)制作工艺以于HEMT区14形成平台隔离24。在本实施例中,平台隔离制作工艺可利用一光刻暨蚀刻制作工艺图案化或以蚀刻去除部分P型半导体层22、部分阻障层20以及部分缓冲层18,其中被图案化的P型半导体层22、阻障层20以及缓冲层18较佳具有相同宽度且两者之间的边缘较佳相互切齐,而剩余且未被图案化的部分缓冲层18则与基底12包含相同宽度。另外本实施例的平台隔离24较佳包含图案化的缓冲层18,其中图案化的缓冲层18厚度约300纳米,图案化的阻障层20厚度约10纳米,而图案化的P型半导体层22的厚度则约100纳米。
接着如图5所示,先进行一光刻暨蚀刻制作工艺去除HEMT区14的部分P型半导体层22,其中被图案化的P型半导体层22较佳作为后续HEMT元件的栅极结构。然后共形地(conformally)形成一硬掩模28于HEMT区14的平台隔离24以及缓冲层18上并延伸至电容区16的缓冲层18上。在本实施例中硬掩模28较佳包含但不局限于氮化硅,且硬掩模20的厚度约略200纳米但不局限于此。
随后进行一道或一道以上光刻暨蚀刻制作工艺去除HEMT区14的部分硬掩模28与部分阻障层20以及电容区16的大部分硬掩模28,以于HEMT区14及电容区16形成多个凹槽(图未示),然后形成导电材料于HEMT区14以及电容区16的凹槽内,再搭配进行一图案转移制作工艺去除部分导电材料,其中HEMT区14中填入凹槽内的导电材料较佳作为源极电极30以及漏极电极32,HEMT区14设于源极电极30以及漏极电极32上方并延伸至两侧硬掩模28表面的导电材料则作为源极电极延伸34以及漏极电极延伸36,而电容区16中填入凹槽内的导电材料则作为电容下电极38。接着形成另一硬掩模40于HEMT区14的硬掩模40表面并延伸至电容区16的电容下电极38上,其中电容区16的硬掩模40较佳作为一电容介电层42。在本实施例中,电容介电层42的厚度约20-100纳米,但不局限于此。
如图6所示,然后进行一道或一道以上光刻暨蚀刻制作工艺去除HEMT区14的部分硬掩模40及部分硬掩模28以形成凹槽(图未示)并暴露出P型半导体层22,形成另一导电材料于HEMT区14的硬掩模40上填满凹槽并覆盖HEMT区14以及电容区16的硬掩模40表面,再搭配进行一图案转移制作工艺去除部分导电材料,其中HEMT区14中填入凹槽内以及设于部分硬掩模40表面的导电材料较佳作为栅极电极44而电容区16中被图案化的导电材料则成为电容上电极46。
如同前述实施例,栅极电极44、源极电极30以及漏极电极32较佳由金属所构成,其中栅极电极44较佳由萧特基金属所构成而源极电极30与漏极电极32较佳由欧姆接触金属所构成。依据本发明一实施例,栅极电极44、源极电极30及漏极电极32可各自包含金、银、铂、钛、铝、钨、钯或其组合。在一些实施例中,可利用电镀制作工艺、溅镀制作工艺、电阻加热蒸镀制作工艺、电子束蒸镀制作工艺、物理气相沉积(physical vapor deposition,PVD)制作工艺、化学气相沉积制作工艺(chemical vapor deposition,CVD)制作工艺、或上述组合于上述凹槽内形成导电材料,然后再利用单次或多次蚀刻将电极材料图案化以形成栅极电极44、源极电极30以及漏极电极32。
随后可进行一接触插塞制作工艺形成接触插塞分别电连接HEMT区14的栅极电极44、源极电极30以及漏极电极32以及电容区16的下电极38以及上电极46。在本实施例中,形成接触插塞的方式可先形成一层间介电层48并覆盖HEMT区14以及电容区16的硬掩模40,然后去除部分层间介电层48以及部分硬掩模40形成接触洞(图未示),再依序沉积一阻隔层(图未示)以及一金属层(图未示)并填满接触洞。接着利用一平坦化制作工艺,例如CMP去除部分金属层、部分阻隔层甚至部分层间介电层48,以于接触洞中形成接触插塞50,其中各接触插塞50顶表面较佳与层间介电层48顶表面切齐。在本实施例中,阻隔层较佳选自由钛、钽、氮化钛、氮化钽以及氮化钨所构成的群组,金属层较佳选自由铝、钛、钽、钨、铌、钼以及铜所构成的群组,但不局限于此。
请再参照图6,图6又揭露本发明一实施例的一半导体元件的结构示意图。如图6所示,半导体元件主要包含HEMT区14以及电容区16定义于基底12上、平台隔离24设于HEMT区14、HEMT 52设于平台隔离24上、电容54设于电容区16以及一缓冲层18设于平台隔离24、电容54以及基底12之间,其中平台隔离24以及缓冲层18包含氮化镓。
另外HEMT 52主要包含阻障层20设于平台隔离24上、P型半导体层22设于阻障层20上、栅极电极44设于P型半导体层22上、源极电极30及漏极电极32设于栅极电极44两侧、源极电极延伸34设于源极电极30上、漏极电极延伸36设于漏极电极32上以及硬掩模28设于平台隔离24及平台隔离26上并环绕源极电极30及漏极电极32。
电容54则包含一下电极38设于缓冲层18上、一电容介电层42设于下电极38上并延伸至HEMT区14的硬掩模28顶部及侧壁以及一上电极46设于电容介电层42上。相较于前述实施例中的HEMT区14以及电容区16均设有平台隔离24、26,本实施例中仅有HEMT区14设有平台隔离24电容区16则无任何平台隔离,且电容下电极38较佳直接接触缓冲层18顶部并具有约略T形的剖面。另外本实施例中的下电极38整体厚度约略等于HEMT区14中源极电极30与源极电极延伸34的加总高度或漏极电极32与漏极电极延伸36的加总高度例如但不局限于300纳米,电容介电层42的厚度较佳约20-100纳米,上电极46的厚度则约略100纳米。
请参照图7至图9,图7至图9为本发明一实施例制作一高电子迁移率晶体管的方法示意图,其中为了简便说明,本实施例与前述实施例中所揭露的相同元件较佳沿用相同标号。如图7所示,首先提供一基底12,例如一由硅、碳化硅或氧化铝(或可称蓝宝石)所构成的基底,其中基底12可为单层基底、多层基底、梯度基底或上述的组合。依据本发明其他实施例基底12又可包含一硅覆绝缘(silicon-on-insulator,SOI)基底。然后于基底12上定义出一电子迁移率晶体管(high electron mobility transistor,HEMT)区14以及一电容区16。
然后于基底12表面形成一缓冲层18。在一实施利中,缓冲层18包含III-V族半导体例如氮化镓,其厚度可介于0.5微米至10微米之间。在一实施利中,可利用分子束外延制作工艺(molecular-beam epitaxy,MBE)、有机金属气相沉积(metal organic chemicalvapor deposition,MOCVD)制作工艺、化学气相沉积(chemical vapor deposition,CVD)制作工艺、氢化物气相外延(hydride vapor phase epitaxy,HVPE)制作工艺或上述组合于基底12上形成缓冲层18。
接着形成一阻障层20于缓冲层18表面。在本实施例中阻障层20较佳包含III-V族半导体例如氮化铝镓(AlxGa1-xN),其中0<x<1,x较佳小于等于20%,且阻障层20较佳包含一由外延成长制作工艺所形成的外延层。如同上述形成缓冲层18的方式,可利用分子束外延制作工艺(molecular-beam epitaxy,MBE)、有机金属气相沉积(metal organic chemicalvapor deposition,MOCVD)制作工艺、化学气相沉积(chemical vapor deposition,CVD)制作工艺、氢化物气相外延(hydride vapor phase epitaxy,HVPE)制作工艺或上述组合于缓冲层18上形成阻障层20。需注意的是,本实施例中阻障层20虽直接设置于缓冲层18表面,但依据本发明另一实施例又可选择于缓冲层18与阻障层20之间额外形成一金属氮化层(图未示)包含例如但不局限于氮化铝,此变化型也属本发明所涵盖的范围。
然后形成一P型半导体层22于阻障层20上。在一实施利中,P型半导体层22较佳包含P型氮化镓(pGaN),且可利用分子束外延制作工艺(molecular-beam epitaxy,MBE)、有机金属气相沉积(metal organic chemical vapor deposition,MOCVD)制作工艺、化学气相沉积(chemical vapor deposition,CVD)制作工艺、氢化物气相外延(hydride vaporphase epitaxy,HVPE)制作工艺或上述组合于阻障层20表面形成P型半导体层22。
随后进行一平台隔离(MESA isolation)制作工艺以于HEMT区14形成平台隔离24。在本实施例中,平台隔离制作工艺可利用一光刻暨蚀刻制作工艺图案化或以蚀刻去除部分P型半导体层22、部分阻障层20以及部分缓冲层18,其中被图案化的P型半导体层22、阻障层20以及缓冲层18较佳具有相同宽度且两者之间的边缘较佳相互切齐,而剩余且未被图案化的部分缓冲层18则与基底12包含相同宽度。另外本实施例的平台隔离24较佳包含图案化的缓冲层18,其中图案化的缓冲层18厚度约300纳米,图案化的阻障层20厚度约10纳米,而图案化的P型半导体层22的厚度则约100纳米。
接着先进行一光刻暨蚀刻制作工艺去除HEMT区14的部分P型半导体层22,其中被图案化的P型半导体层22较佳作为后续HEMT元件的栅极结构,然后共形地(conformally)形成一硬掩模28于HEMT区16的平台隔离24以及缓冲层18上并延伸至电容区16的缓冲层18上。在本实施例中硬掩模28较佳包含但不局限于氮化硅,且硬掩模28的厚度约略200纳米但不局限于此。
接着如图8所示,进行一道或一道以上光刻暨蚀刻制作工艺去除HEMT区14的部分硬掩模28与部分阻障层20以于HEMT区14形成多个凹槽(图未示),然后形成导电材料于HEMT区14的凹槽内并覆盖HEMT区14以及电容区16的硬掩模28表面,再搭配进行一图案转移制作工艺去除部分导电材料,其中HEMT区14中填入凹槽内的导电材料较佳作为源极电极30以及漏极电极32,HEMT区14设于源极电极30以及漏极电极32上方并延伸至两侧硬掩模28表面的导电材料则作为源极电极延伸34以及漏极电极延伸36,而电容区16中设于硬掩模28表面的导电材料则作为电容下电极38。接着形成另一硬掩模40于HEMT区16的硬掩模28表面并延伸至电容区16的电容下电极38上,其中电容区16的硬掩模40较佳作为一电容介电层42。在本实施例中,电容介电层42的厚度约20-100纳米,但不局限于此。
如图9所示,然后进行一道或一道以上光刻暨蚀刻制作工艺去除HEMT区14的部分硬掩模40及部分硬掩模28以形成凹槽(图未示)并暴露出P型半导体层22,形成另一导电材料于HEMT区14的硬掩模40上填满凹槽并覆盖HEMT区14以及电容区16的硬掩模40表面,再搭配进行一图案转移制作工艺去除部分导电材料,其中HEMT区14中填入凹槽内以及设于部分硬掩模40表面的导电材料较佳作为栅极电极44而电容区16中被图案化的导电材料则成为电容上电极46。
如同前述实施例,栅极电极44、源极电极30以及漏极电极32较佳由金属所构成,其中栅极电极44较佳由萧特基金属所构成而源极电极30与漏极电极32较佳由欧姆接触金属所构成。依据本发明一实施例,栅极电极44、源极电极30及漏极电极32可各自包含金、银、铂、钛、铝、钨、钯或其组合。在一些实施例中,可利用电镀制作工艺、溅镀制作工艺、电阻加热蒸镀制作工艺、电子束蒸镀制作工艺、物理气相沉积(physical vapor deposition,PVD)制作工艺、化学气相沉积制作工艺(chemical vapor deposition,CVD)制作工艺、或上述组合于上述凹槽内形成导电材料,然后再利用单次或多次蚀刻将电极材料图案化以形成栅极电极44、源极电极30以及漏极电极32。
随后可进行一接触插塞制作工艺形成接触插塞分别电连接HEMT区14的栅极电极44、源极电极30以及漏极电极32以及电容区16的下电极38以及上电极46。在本实施例中,形成接触插塞的方式可先形成一层间介电层48并覆盖HEMT区14以及电容区16的硬掩模40,然后去除部分层间介电层48以及部分硬掩模40形成接触洞(图未示),再依序沉积一阻隔层(图未示)以及一金属层(图未示)并填满接触洞。接着利用一平坦化制作工艺,例如CMP去除部分金属层、部分阻隔层甚至部分层间介电层48,以于接触洞中形成接触插塞50,其中各接触插塞50顶表面较佳切齐层间介电层48顶表面。在本实施例中,阻隔层较佳选自由钛、钽、氮化钛、氮化钽以及氮化钨所构成的群组,金属层较佳选自由铝、钛、钽、钨、铌、钼以及铜所构成的群组,但不局限于此。
请再参照图9,图9又揭露本发明一实施例的一半导体元件的结构示意图。如图9所示,半导体元件主要包含HEMT区14以及电容区16定义于基底12上、平台隔离24设于HEMT区14、HEMT 52设于平台隔离24上、硬掩模28环绕HEMT 52并延伸至电容区16、电容54设于电容区16以及一缓冲层18设于平台隔离24、电容54以及基底12之间,其中平台隔离24以及缓冲层18包含氮化镓。
另外HEMT 52主要包含阻障层20设于平台隔离24上、P型半导体层22设于阻障层20上、栅极电极44设于P型半导体层22上、源极电极30及漏极电极32设于栅极电极44两侧、源极电极延伸34设于源极电极30上以及漏极电极延伸36设于漏极电极32上。
电容54则包含一下电极38设于硬掩模28上、一电容介电层42设于下电极38上并延伸至HEMT区14的硬掩模28顶部及侧壁以及一上电极46设于电容介电层42上。相较于前述实施例中的电容下电极38是设于缓冲层18上且下电极38的整体厚度约略等于HEMT区14中源极电极30与源极电极延伸34的加总高度或漏极电极32与漏极电极延伸36的加总高度,本实施例中的下电极38厚度仅较佳等于HEMT区14中源极电极延伸34或漏极电极延伸36的高度例如但不局限于100纳米,电容介电层42的厚度较佳约20-100纳米,上电极46的厚度约略100纳米。
以上所述仅为本发明的优选实施例,凡依本发明权利要求所做的均等变化与修饰,都应属本发明的涵盖范围。
Claims (20)
1.一种半导体元件,其特征在于,包含:
基底,包含电子迁移率晶体管(high electron mobility transistor,HEMT)区以及电容区;
第一平台隔离(mesa isolation),设于该HEMT区;
HEMT,设于该第一平台隔离上;
第二平台隔离,设于该电容区;以及
电容,设于该第二平台隔离上。
2.如权利要求1所述的半导体元件,另包含缓冲层,设于该基底、该第一平台隔离以及该第二平台隔离之间。
3.如权利要求1所述的半导体元件,其中该第一平台隔离底部切齐该第二平台隔离底部。
4.如权利要求1所述的半导体元件,其中该第一平台隔离以及该第二平台隔离包含氮化镓。
5.如权利要求1所述的半导体元件,其中该HEMT包含:
阻障层,设于该第一平台隔离上;
P型半导体层,设于该阻障层上;
栅极电极,设于该P型半导体层上;
源极电极以及漏极电极,设于该栅极电极两侧;
源极电极,延伸设于该源极电极上;以及
漏极电极,延伸设于该漏极电极上。
6.如权利要求5所述的半导体元件,另包含硬掩模,设于该第一平台隔离以及该第二平台隔离上并环绕该源极电极以及该漏极电极。
7.如权利要求6所述的半导体元件,其中该电容包含:
下电极,设于该硬掩模上;
电容介电层,设于该下电极上并延伸至该HEMT区的该硬掩模;以及
上电极,设于该电容介电层上。
8.如权利要求7所述的半导体元件,其中该下电极底部切齐该源极电极延伸底部。
9.如权利要求7所述的半导体元件,其中该上电极顶部切齐该栅极电极顶部。
10.一种半导体元件,其特征在于,包含:
基底,包含电子迁移率晶体管(high electron mobility transistor,HEMT)区以及电容区;
平台隔离(mesa isolation),设于该HEMT区;
HEMT,设于该平台隔离上;
电容,设于该电容区;以及
缓冲层,设于该平台隔离、该电容以及该基底之间。
11.如权利要求10所述的半导体元件,其中该平台隔离以及该缓冲层包含氮化镓。
12.如权利要求10所述的半导体元件,其中该HEMT包含:
阻障层,设于该平台隔离上;
P型半导体层,设于该阻障层上;
栅极电极,设于该P型半导体层上;
源极电极以及漏极电极,设于该栅极电极两侧;
源极电极,延伸设于该源极电极上;以及
漏极电极,延伸设于该漏极电极上。
13.如权利要求12所述的半导体元件,另包含硬掩模,设于该第一平台隔离上并环绕该源极电极以及该漏极电极。
14.如权利要求13所述的半导体元件,其中该电容包含:
下电极,设于该缓冲层上;
电容介电层,设于该下电极上并延伸至该HEMT区的该硬掩模;以及
上电极,设于该电容介电层上。
15.一种半导体元件,其特征在于,包含:
基底,包含电子迁移率晶体管(high electron mobility transistor,HEMT)区以及电容区;
平台隔离(mesa isolation),设于该HEMT区;
HEMT,设于该平台隔离上;
硬掩模,环绕该HEMT并延伸至该电容区;以及
电容,设于该硬掩模上。
16.如权利要求15所述的半导体元件,另包含缓冲层,设于该平台隔离、该硬掩模以及该基底之间。
17.如权利要求16所述的半导体元件,其中该平台隔离以及该缓冲层包含氮化镓。
18.如权利要求15所述的半导体元件,其中该HEMT包含:
阻障层,设于该平台隔离上;
P型半导体层,设于该阻障层上;
栅极电极,设于该P型半导体层上;
源极电极以及漏极电极,设于该栅极电极两侧;
源极电极,延伸设于该源极电极上;以及
漏极电极,延伸设于该漏极电极上。
19.如权利要求18所述的半导体元件,其中该硬掩模环绕该P型半导体层、该栅极电极、该源极电极以及该漏极电极。
20.如权利要求15所述的半导体元件,其中该电容包含:
下电极,设于该硬掩模上;
电容介电层,设于该下电极上并延伸至该HEMT区的该硬掩模;以及
上电极,设于该电容介电层上。
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WO2019111113A1 (ja) * | 2017-12-06 | 2019-06-13 | 株式会社半導体エネルギー研究所 | 半導体装置 |
US11276764B1 (en) * | 2020-08-09 | 2022-03-15 | Global Communication Semiconductors, Llc | Method of making high frequency InGaP/GaAs HBTs |
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2020
- 2020-07-21 CN CN202010704978.1A patent/CN113964119A/zh active Pending
- 2020-08-16 US US16/994,646 patent/US11688800B2/en active Active
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US20220029005A1 (en) | 2022-01-27 |
US11688800B2 (en) | 2023-06-27 |
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