CN113161422B - Low-radiation electric leakage high-voltage LDMOS device structure - Google Patents
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- 210000000746 body region Anatomy 0.000 claims abstract description 32
- 230000005855 radiation Effects 0.000 claims abstract description 25
- 239000012535 impurity Substances 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 208000032750 Device leakage Diseases 0.000 abstract description 3
- 230000001413 cellular effect Effects 0.000 abstract 3
- 238000010586 diagram Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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Abstract
The invention provides a low-radiation leakage high-voltage LDMOS device structure, which comprises three different cross-section structures of AB, AC and AD. Compared with the traditional high-voltage LDMOS device structure, the high-voltage LDMOS device structure has the advantage that an AC section structure is added between the AB section and the AD section. The second conductive type source region is deleted from the junction of the cellular region and the non-cellular region (field region) to one side of the cellular region, namely an AC section, and the first conductive type body region extends rightwards to be tangent to the second conductive type source region in the AD section, so that a radiation leakage path is cut off, the device leakage phenomenon caused by total dose radiation is avoided, the off-state loss of the device is reduced, and the total dose radiation resistance of the device is improved.
Description
Technical Field
The invention belongs to the field of semiconductor power devices, and particularly relates to a high-voltage LDMOS device structure with low radiation leakage.
Background
With the application of power semiconductor devices in electronic systems of aerospace and the like becoming more and more extensive, the radiation-resistant reinforcement technology becomes a research focus of various companies and colleges for power management systems and gate drive circuits. The high-voltage LDMOS device is used as a core part of the analog circuit, and is characterized by large occupied area and larger field oxide layer. Therefore, under radiation environments such as gamma rays, the LDMOS device is easy to have the phenomena of voltage resistance degradation, threshold drift and leakage current increase, so that the static power consumption of the circuit is increased, the device fails in severe cases, and the whole circuit cannot normally work, so that the low-radiation leakage high-voltage LDMOS device needs to be researched.
Disclosure of Invention
In order to solve the problem that the leakage current of the high-voltage LDMOS device is increased after the total dose radiation, the invention provides a high-voltage LDMOS device structure with low radiation leakage. The total dose radiation damage is mainly caused by trapped charges generated at the interface of silicon and silicon dioxide. The high-voltage LDMOS device generates electron-hole pairs in the oxidation layer after radiation, and the electron-hole pairs jump to the interface of silicon and silicon dioxide under the action of an external electric field and are captured by the traps of the oxidation layer to form trapped charges. The positively charged trapped charges generate mirror charges at the interface between the drift region of the second conductivity type and the cell region and the non-cell region, thereby providing a leakage path for the device through the drift region of the second conductivity type, the well region of the first conductivity type and the source region of the second conductivity type. The invention innovates the first conduction type body area, deletes the second conduction type source area on the AC section, and extends the first conduction type body area to the right to be tangent with the second conduction type source area in the AD section, thereby cutting off the radiation leakage path, avoiding the device leakage phenomenon caused by total dose radiation, reducing the off-state loss of the device and improving the total dose radiation resistance of the device.
In order to realize the purpose of the invention, the technical scheme of the invention is as follows:
the high-voltage LDMOS device structure with low radiation leakage comprises three different cross-section structures of AB, AC and AD; wherein AB is the direction from the inside of the device to the outside along the radius and sequentially passes through the second conductive type drain region 6, the active region 8, the second conductive type drift region 4 and the first conductive type well region 3; AC is the direction from the inside of the device to the outside along the radius and sequentially passes through a second conduction type drain region 6, an active region 8, a second conduction type drift region 4, the active region 8, a first conduction type well region 3 and a first conduction type body region 1; the AD sequentially passes through a second conductive type drain region 6, an active region 8, a second conductive type drift region 4, the active region 8, a first conductive type well region 3, a second conductive type source region 2 and a first conductive type body region 1 from the inside of the device along the radial direction;
along section AB: the field oxide layer 14 is formed on a first conduction type substrate 7, the second conduction type drift region 4 is formed on the buried oxide layer 14, the first conduction type well region 3 is positioned at the inner upper left corner of the second conduction type drift region 4, the second conduction type well region 5 is positioned at the inner upper right corner of the second conduction type drift region 4, the second conduction type drain region 6 is positioned at the inner upper right corner of the second conduction type well region 5, the field oxide layer 12 is positioned on the surface of a device, extends and covers part of the surface of the second conduction type well region 5, the polycrystalline gate electrode 10 is positioned above the field oxide layer 12, and the drain electrode 13 is positioned above the second conduction type drain region 6;
along the AC cross section: the field oxide layer 14 is formed on a first conduction type substrate 7, the second conduction type drift region 4 is formed on the buried oxide layer 14, the first conduction type well region 3 is positioned at the left upper corner inside the second conduction type drift region 4, the first conduction type body region 1 is positioned inside the first conduction type 3, the source electrode 9 is arranged above the first conduction type body region 1, the second conduction type well region 5 is positioned at the right upper corner inside the second conduction type drift region 4, the second conduction type drain region 6 is positioned at the right upper corner inside the second conduction type well region 5, the drain electrode 13 is arranged above the second conduction type drain region 6, the field oxide layer 12 is arranged on the surface of the device, extends and covers part of the surface of the second conduction type well region 5, and the gate oxide layer 11 is positioned below the polycrystalline gate electrode 10 and is connected with the field oxide layer 12;
section along AD: comprising a buried oxide layer 14 formed on a first conductivity type substrate 7, a second conductivity type drift region 4 formed on the buried oxide layer 14, a first conductivity type well region 3 located in the upper left corner inside the second conductivity type drift region 4, a first conductivity type body region 1 located inside the first conductivity type 3, a second conductivity type source region 2 located on the right side of the first conductivity type body region 1 within the first conductivity type well region 3, a source electrode 9 disposed above the first conductivity type body region 1 and above the second conductivity type source region 2, and the first conductive type body region 1 and the second conductive type source region 2 are in short circuit, the second conductive type well region 5 is positioned at the upper right corner inside the second conductive type drift region 4, the second conductive type drain region 6 is positioned inside the second conductive type well region 5, the drain electrode 13 is positioned above the second conductive type drain region 6, the field oxide layer 12 is positioned on the surface of the device, extends and covers part of the surface of the second conductive type well region 5, and the gate oxide layer 11 is positioned below the polycrystalline gate electrode 10 and is connected with the field oxide layer 12.
Preferably, the material of the field oxide layer 12 is silicon dioxide or a low-K material with K less than or equal to 2.8.
Preferably, the first conductivity type body region 1 cuts off a path of leakage due to total dose radiation.
Preferably, when the first conductive type doping impurity is an acceptor type doping impurity, the second conductive type doping impurity is a donor type doping impurity, and at this time, the drain electrode is biased to a positive potential with respect to the source electrode; when the first conductivity type impurity is donor type, the second conductivity type impurity is acceptor type, and the drain electrode is biased to negative potential with respect to the source electrode.
The invention has the beneficial effects that: the invention provides a low-radiation leakage high-voltage LDMOS device structure, which is characterized in that a second conduction type source region is deleted in the AC section direction, and a first conduction type body region is rightwards extended to be tangent to the second conduction type source region in the AD section, so that a leakage path caused by total dose radiation is cut off, the device leakage phenomenon caused by the total dose radiation is avoided, the off-state loss of the device is reduced, and the total dose radiation resistance of the device is improved.
Drawings
FIG. 1 is a top view of a circular layout structure of a conventional high-voltage LDMOS device.
Fig. 2 is a schematic diagram of a leakage path of a conventional high-voltage LDMOS device.
FIG. 3 is a top view of the circular layout structure of the device of the present invention.
Fig. 4 is a schematic diagram of a leakage cut-off approach of the device of the present invention.
Fig. 5 is a schematic view of the device structure along section AB in fig. 3.
Fig. 6 is a schematic diagram of the device structure along the AC cross-section in fig. 3.
Fig. 7 is a schematic diagram of the device structure along section AD in fig. 3.
The structure comprises a substrate, a first conductive type body region 1, a second conductive type source region 2, a first conductive type well region 3, a second conductive type drift region 4, a second conductive type well region 5, a second conductive type drain region 6, a first conductive type substrate 7, an active region 8, a source electrode 9, a polycrystalline gate electrode 10, a gate oxide layer 11, a field oxide layer 12, a drain electrode 13 and a buried oxide layer 14.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
FIG. 1 is a top view of a circular layout of a conventional high-voltage LDMOS device. The structures on the two cross sections AB and AD can describe the structure of the whole device, and a leakage path is formed at the boundary of the cell region and the non-cell region after radiation of the conventional high-voltage LDMOS device structure, as shown in fig. 2. The leakage path increases the leakage current caused by total dose radiation, so that the static power consumption of the circuit is increased, the device is failed in serious conditions, and the whole circuit cannot work normally.
To avoid this leakage path, the present invention makes an innovation in the structure of the first conductivity type body region 1 in the active region 8, as shown in fig. 3. The whole device structure is described from three sections of AB, AC and AD, wherein the AC section structure is the innovation point of the invention. In the AC section, the second conduction type source region is deleted, and the first conduction type body region extends rightwards to be tangent to the second conduction type source region in the AD section, so that a leakage path is cut off, as shown in figure 4, the leakage phenomenon caused by total dose radiation is effectively avoided, the off-state loss of the device is reduced, and the total dose radiation resistance of the device is improved.
Examples
The embodiment provides a low-radiation leakage high-voltage LDMOS device structure, which comprises three different cross-section structures of AB, AC and AD, wherein the AB is a direction sequentially passing through a second conductive type drain region 6, an active region 8, a second conductive type drift region 4 and a first conductive type well region 3 from the inside of the device along the radius to the outside; the AC is the direction from the inside of the device to the outside along the radius and sequentially passes through the second conductive type drain region 6, the active region 8, the second conductive type drift region 4, the active region 8, the first conductive type well region 3 and the first conductive type body region 1; AD is a direction from inside the device along a radius outward in sequence through the second conductive type drain region 6, the active region 8, the second conductive type drift region 4, the active region 8, the first conductive type well region 3, the second conductive type source region 2, and the first conductive type body region 1.
Along section AB: the floating gate structure comprises a buried oxide layer 14 formed on a first conduction type substrate 7, a second conduction type drift region 4 formed on the buried oxide layer 14, a first conduction type well region 3 located at the inner upper left corner of the second conduction type drift region 4, a second conduction type well region 5 located at the inner upper right corner of the second conduction type drift region 4, a second conduction type drain region 6 located at the inner upper right corner of the second conduction type well region 5, a field oxide layer 12 located on the surface of a device and extending to cover part of the surface of the second conduction type well region 5, a polycrystalline gate electrode 10 located above the field oxide layer 12, and a drain electrode 13 located above the second conduction type drain region 6.
Along the AC cross section: comprising a buried oxide layer 14 formed on a first conductivity type substrate 7, a second conductivity type drift region 4 formed on the buried oxide layer 14, a first conductivity type well region 3 located at the inner upper left corner of the second conductivity type drift region 4, a first conductivity type body region 1 located inside the first conductivity type 3, a source electrode 9 disposed above the first conductivity type body region 1, the second conductive type well region 5 is located at the inner upper right corner of the second conductive type drift region 4, the second conductive type drain region 6 is located at the inner upper right corner of the second conductive type well region 5, the drain electrode 13 is located above the second conductive type drain region 6, the field oxide layer 12 is located on the surface of the device, extends and covers part of the surface of the second conductive type well region 5, and the gate oxide layer 11 is located below the polycrystalline gate electrode 10 and is connected with the field oxide layer 12.
Section along AD: comprising a buried oxide layer 14 formed on a first conductivity type substrate 7, a second conductivity type drift region 4 formed on the buried oxide layer 14, a first conductivity type well region 3 located in the upper left corner inside the second conductivity type drift region 4, a first conductivity type body region 1 located inside the first conductivity type 3, a second conductivity type source region 2 located on the right side of the first conductivity type body region 1 within the first conductivity type well region 3, a source electrode 9 disposed above the first conductivity type body region 1 and above the second conductivity type source region 2, and the first conductive type body region 1 and the second conductive type source region 2 are in short circuit, the second conductive type well region 5 is positioned at the upper right corner inside the second conductive type drift region 4, the second conductive type drain region 6 is positioned inside the second conductive type well region 5, the drain electrode 13 is positioned above the second conductive type drain region 6, the field oxide layer 12 is positioned on the surface of the device, extends and covers part of the surface of the second conductive type well region 5, and the gate oxide layer 11 is positioned below the polycrystalline gate electrode 10 and is connected with the field oxide layer 12.
The field oxide layer 12 is made of silicon dioxide or a low-K material with K less than or equal to 2.8.
The first conductivity type body region 1 cuts off the leakage path due to the total dose radiation.
When the first conductive type doping impurities are acceptor type doping impurities and the second conductive type doping impurities are donor type doping impurities, the drain electrode is biased to be positive potential relative to the source electrode; when the first conductivity type impurity is donor type, the second conductivity type impurity is acceptor type, and the drain electrode is biased to negative potential with respect to the source electrode.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.
Claims (4)
1. The high-voltage LDMOS device structure with low radiation leakage is characterized in that: the structure comprises three different cross-sectional structures of AB, AC and AD; AB is the direction from the inside of the device to the outside along the radius and sequentially passes through the second conductive type drain region (6), the active region (8), the second conductive type drift region (4) and the first conductive type well region (3); AC is the direction which sequentially passes through a second conduction type drain region (6), an active region (8), a second conduction type drift region (4), the active region (8), a first conduction type well region (3) and a first conduction type body region (1) from the inside of the device along the radius outwards; the AD sequentially passes through a second conduction type drain region (6), an active region (8), a second conduction type drift region (4), the active region (8), a first conduction type well region (3), a second conduction type source region (2) and a first conduction type body region (1) from the inside of the device along the radius outwards;
along section AB: the field oxide layer is arranged on the surface of the device, the field oxide layer (12) is arranged on the surface of the device, extends and covers part of the surface of the second conductive type well region (5), the polycrystalline gate electrode (10) is arranged above the field oxide layer (12), and the drain electrode (13) is arranged above the second conductive type drain region (6);
along the AC section: the transistor comprises a buried oxide layer (14) formed on a first conduction type substrate (7), a second conduction type drift region (4) formed on the buried oxide layer (14), a first conduction type well region (3) is positioned at the left upper corner inside the second conduction type drift region (4), a first conduction type body region (1) is positioned inside the first conduction type (3), a source electrode (9) is arranged above the first conduction type body region (1), a second conduction type well region (5) is positioned at the right upper corner inside the second conduction type drift region (4), a second conduction type drain region (6) is arranged at the right upper corner inside the second conduction type well region (5), a drain electrode (13) is arranged above the second conduction type drain region (6), a field oxide layer (12) is arranged on the surface of the device, extends and covers part of the surface of the second conduction type well region (5), and a gate oxide layer (11) is arranged below a polycrystalline gate electrode (10) and is connected with the field oxide layer (12);
section along AD: the field oxide type field oxide device comprises a buried oxide layer (14) formed on a first conduction type substrate (7), a second conduction type drift region (4) formed on the buried oxide layer (14), a first conduction type well region (3) is located in the upper left corner inside the second conduction type drift region (4), a first conduction type body region (1) is located inside the first conduction type (3), a second conduction type source region (2) is located on the right side of the first conduction type body region (1) inside the first conduction type well region (3), a source electrode (9) is located above the first conduction type body region (1) and above the second conduction type source region (2) and short-circuits the first conduction type body region (1) and the second conduction type source region (2), the upper right corner of the second conduction type well region (5) is located inside the second conduction type drift region (4), the second conduction type drain region (6) is located inside the second conduction type well region (5), a drain electrode (13) is located above the second conduction type drain region (6), a drain electrode layer (12) is located on the surface, the surface of the second conduction type field oxide layer (5) extends, and the polycrystalline field oxide layer (10) is connected with a field oxide layer (10).
2. The low-radiation leakage high-voltage LDMOS device structure of claim 1, wherein: the field oxide layer (12) is made of silicon dioxide or a low-K material with the dielectric constant K less than or equal to 2.8.
3. The low-radiation leakage high-voltage LDMOS device structure of claim 1, wherein: the first conductivity type body region (1) cuts off the leakage path due to total dose radiation.
4. The low-radiation leakage high-voltage LDMOS device structure of claim 1, wherein: when the first conductive type doped impurity is of a donor type, the second conductive type doped impurity is of a donor type, and at the moment, the drain electrode is biased to be a positive potential relative to the source electrode; when the first conductivity type impurity is donor type, the second conductivity type impurity is acceptor type, and the drain electrode is biased to negative potential with respect to the source electrode.
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| CN113594258B (en) * | 2021-08-27 | 2023-04-25 | 电子科技大学 | Low-radiation leakage high-voltage LDMOS device |
| CN113675274B (en) * | 2021-08-27 | 2023-04-25 | 电子科技大学 | Low-radiation leakage high-voltage Double RESURF LDMOS device |
| CN114551574B (en) * | 2022-02-28 | 2023-09-15 | 电子科技大学 | High-voltage single-particle reinforced LDMOS device |
| CN117238970B (en) * | 2023-11-13 | 2024-02-09 | 中国电子科技集团公司第五十八研究所 | High-voltage radiation-resistant lateral MOSFET device |
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| CN102074580A (en) * | 2010-11-17 | 2011-05-25 | 北京时代民芯科技有限公司 | Transistor structure with reinforced total dose radiation resistance |
| WO2016026422A1 (en) * | 2014-08-22 | 2016-02-25 | 无锡华润上华半导体有限公司 | Ldmos device and manufacturing method thereof |
| TW202018941A (en) * | 2018-11-07 | 2020-05-16 | 新唐科技股份有限公司 | High voltage semiconductor devices |
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| CN101419986B (en) * | 2008-12-05 | 2011-05-11 | 北京时代民芯科技有限公司 | Double edge total dose resistant radiation reinforcement pattern construction preventing edge electricity leakage |
| US9281232B2 (en) * | 2013-10-21 | 2016-03-08 | Texas Instruments Incorporated | Device having improved radiation hardness and high breakdown voltages |
| CN109585531B (en) * | 2018-11-29 | 2022-03-15 | 中国电子科技集团公司第四十七研究所 | MOS field effect transistor for resisting total dose effect |
| CN109904237B (en) * | 2019-03-18 | 2020-11-27 | 电子科技大学 | Transverse SOI high-voltage device with instantaneous dose rate radiation reinforcing structure |
| CN110137248A (en) * | 2019-05-29 | 2019-08-16 | 电子科技大学 | A kind of LDMOS device of resistant to total dose effect |
| CN110190121B (en) * | 2019-05-29 | 2023-04-25 | 电子科技大学 | Lateral SOI high voltage device with instant dose rate radiation reinforcing structure |
| CN111987145B (en) * | 2020-09-09 | 2022-11-29 | 电子科技大学 | Total dose ionizing radiation resistant super junction VDMOS device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102074580A (en) * | 2010-11-17 | 2011-05-25 | 北京时代民芯科技有限公司 | Transistor structure with reinforced total dose radiation resistance |
| WO2016026422A1 (en) * | 2014-08-22 | 2016-02-25 | 无锡华润上华半导体有限公司 | Ldmos device and manufacturing method thereof |
| TW202018941A (en) * | 2018-11-07 | 2020-05-16 | 新唐科技股份有限公司 | High voltage semiconductor devices |
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