CN113594258B - Low-radiation leakage high-voltage LDMOS device - Google Patents
Low-radiation leakage high-voltage LDMOS device Download PDFInfo
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- CN113594258B CN113594258B CN202110998545.6A CN202110998545A CN113594258B CN 113594258 B CN113594258 B CN 113594258B CN 202110998545 A CN202110998545 A CN 202110998545A CN 113594258 B CN113594258 B CN 113594258B
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- 230000005855 radiation Effects 0.000 claims abstract description 22
- 210000000746 body region Anatomy 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 239000002019 doping agent Substances 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 230000001413 cellular effect Effects 0.000 abstract description 6
- 208000032750 Device leakage Diseases 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
Abstract
The invention provides a low-radiation leakage high-voltage LDMOS device structure, which comprises three different cross-section structures AB, AC and AD. Compared with the traditional high-voltage LDMOS device structure, the AC cross-section structure is added between the AB cross section and the AD cross section. The junction of the cellular region and the non-cellular region (field region) is filled with a heavily doped region of the first conductivity type to the side of the non-cellular region, namely the AC section, so that the radiation leakage path is cut off, the device leakage phenomenon caused by total dose radiation is avoided, the off-state loss of the device is reduced, and the total dose radiation resistance of the device is improved.
Description
Technical Field
The invention belongs to the field of semiconductor power devices, and particularly relates to a low-radiation leakage high-voltage LDMOS device structure.
Background
Along with the wider application of power semiconductor devices in aerospace electronic systems and the like, the radiation-resistant reinforcement technology is the research focus of various companies and universities aiming at power management systems and gate driving circuits. The high-voltage LDMOS device is used as a core part of an analog circuit, and the LDMOS device is characterized by large occupied area and larger field oxide layer. Therefore, under the radiation environment such as gamma rays, the LDMOS device is easy to generate the phenomena of voltage resistance degradation, threshold drift and leakage current increase, the static power consumption of the circuit is increased, the device is invalid when serious, and the whole circuit cannot work normally, so that the low-radiation leakage high-voltage LDMOS device needs to be studied.
Disclosure of Invention
In order to solve the problem of increased leakage current of the device after the total radiation dose of the high-voltage LDMOS device, the invention provides a high-voltage LDMOS device structure with low radiation leakage. The total dose radiation damage is mainly caused by trapped charges generated at the silicon and silicon dioxide interface. The high-voltage LDMOS device generates electron hole pairs in the oxide layer after radiation, and under the action of an external electric field, the electron hole pairs are transited to the interface of silicon and silicon dioxide and are trapped by traps of the oxide layer to form trap charges. The positively charged trapped charges create mirror charges at the interfaces of the second conductivity type drift region and the cell region with the non-cell region, thereby providing a leakage path for the device through the second conductivity type drift region, the first conductivity type well region and the second conductivity type source region. The invention innovates the first conductive type body region, and supplements and injects a first conductive type heavily doped region in the AC section, thereby cutting off the radiation leakage path, avoiding the device leakage phenomenon caused by the total dose radiation, reducing the off-state loss of the device and improving the total dose radiation resistance of the device.
In order to achieve the above object, the present invention has the following technical scheme:
a low-radiation leakage high-voltage LDMOS device structure comprises three different cross-section structures AB, AC and AD. AB is a direction from the inside of the device along a radius outwards and sequentially passing through the second conductivity type drain region 6, the active region 8, the second conductivity type well region 5, the second conductivity type drift region 4 and the first conductivity type well region 3; AC is the direction from the inside of the device along the radius outwards through the second conductivity type drain region 6, the active region 8, the second conductivity type well region 5, the second conductivity type drift region 4 and the first conductivity type heavily doped region 15; AD is the direction from the inside of the device radially outward through the second conductivity type drain region 6, the active region 8, the second conductivity type well region 5, the second conductivity type drift region 4, the active region 8, the first conductivity type well region 3, the second conductivity type source region 2, and the first conductivity type body region 1.
Along the AB section: comprising a buried oxide layer 14 formed on a first conductivity type substrate 7, a second conductivity type drift region 4 formed on the buried oxide layer 14, a first conductivity type well region 3 located at an inner upper left corner of the second conductivity type drift region 4, a second conductivity type well region 5 located at an inner upper right corner of the second conductivity type drift region 4, a second conductivity type drain region 6 located at an inner upper right corner of the second conductivity type well region 5, a field oxide layer 12 located at a device surface, extending and covering a part of the surface of the second conductivity type well region 5, a polycrystalline gate electrode 10 located above the field oxide layer 12, and a drain electrode 13 located above the second conductivity type drain region 6.
Along the AC section: comprising a buried oxide layer 14 formed on a first conductivity type substrate 7, a second conductivity type drift region 4 formed on the buried oxide layer 14, a first conductivity type heavily doped region 15 located at an inner upper left corner of the second conductivity type drift region 4, a second conductivity type well region 5 located at an inner upper right corner of the second conductivity type drift region 4, a second conductivity type drain region 6 located at an inner upper right corner of the second conductivity type well region 5, a field oxide layer 12 located on a device surface, extending and covering a part of the surface of the second conductivity type well region 5, a polycrystalline gate electrode 10 located above the field oxide layer 12, and a drain electrode 13 located above the second conductivity type drain region 6.
Along the AD section: comprising a buried oxide layer 14 formed on a first conductivity type substrate 7, a second conductivity type drift region 4 formed on the buried oxide layer 14, a first conductivity type well region 3 located at an inner upper left corner of the second conductivity type drift region 4, a first conductivity type body region 1 located inside the first conductivity type 3, a second conductivity type source region 2 located at a right side of the first conductivity type body region 1 within the first conductivity type well region 3, a source electrode 9 located above the first conductivity type body region 1 and above the second conductivity type source region 2 and shorting the first conductivity type body region 1 and the second conductivity type source region 2, a second conductivity type well region 5 located at an inner upper right corner of the second conductivity type drift region 4, a second conductivity type drain region 6 located inside the second conductivity type well region 5, a drain electrode 13 located above the second conductivity type drain region 6, a field oxide layer 12 located at a device surface extending and covering a portion of the surface of the second conductivity type well region 5, a gate oxide layer 11 located below the polycrystalline gate electrode 10 and connected to the field oxide layer 12.
Preferably, the material of the field oxide layer 12 is silicon dioxide or a low-K material with K less than or equal to 2.8.
Preferably, the heavily doped region 15 of the first conductivity type cuts off the leakage path due to the total dose of radiation.
Preferably, the second conductivity type doped impurity is donor type when the first conductivity type doped impurity is acceptor type, and the drain electrode is biased to a positive potential with respect to the source electrode; the second conductivity type dopant is acceptor type when the first conductivity type dopant is donor type, and the drain electrode is biased to a negative potential with respect to the source electrode.
The beneficial effects of the invention are as follows: the invention provides a low-radiation leakage high-voltage LDMOS device structure, which is characterized in that a heavily doped region of a first conductive type is additionally injected in the direction of an AC section, so that a leakage path caused by total-dose radiation is cut off, the device leakage phenomenon caused by the total-dose radiation is avoided, the off-state loss of the device is reduced, and the total-dose radiation resistance of the device is improved.
Drawings
Fig. 1 is a top view of a circular layout of a conventional high voltage LDMOS device.
Fig. 2 is a schematic diagram of a leakage path of a conventional high-voltage LDMOS device.
FIG. 3 is a top view of a circular layout structure of the device of the present invention.
Fig. 4 is a schematic diagram of the device of the present invention for cutting off the leakage path.
Fig. 5 is a schematic view of the device structure along the AB section in fig. 3.
Fig. 6 is a schematic view of the device structure along the AC section in fig. 3.
Fig. 7 is a schematic view of the device structure along the AD section in fig. 3.
1 is a first conductive type body region, 2 is a second conductive type source region, 3 is a first conductive type well region, 4 is a second conductive type drift region, 5 is a second conductive type well region, 6 is a second conductive type drain region, 7 is a first conductive type substrate, 8 is an active region, 9 is a source electrode, 10 is a polycrystalline gate electrode, 11 is a gate oxide layer, 12 is a field oxide layer, 13 is a drain electrode, 14 is a buried oxide layer, and 15 is a first conductive type heavily doped region.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Fig. 1 is a top view of a circular layout of a conventional high voltage LDMOS device. The structure in both sections AB and AD can describe the structure of the entire device, where 1 is a first conductivity type body region, 2 is a second conductivity type source region, 3 is a first conductivity type well region, 4 is a second conductivity type drift region, 5 is a second conductivity type well region, 6 is a second conductivity type drain region, and 8 is an active region. After the conventional high-voltage LDMOS device structure is radiated, a leakage path is formed at the junction of the cellular region and the non-cellular region, as shown in FIG. 2. The leakage path increases leakage current caused by total radiation dose, so that static power consumption of the circuit is increased, and the device is disabled when serious, so that the whole circuit cannot work normally.
In order to avoid the generation of the leakage path, the present invention innovates the structure of the first conductivity type well region 3 in the non-cellular region, as shown in fig. 3. The entire device structure is described from three sections AB, AC and AD, where AC cross-sectional structure is the innovation of the present invention. In the AC section, a heavily doped region of the first conductivity type is implanted in a complementary manner, so that a leakage path is cut off, as shown in fig. 4, the leakage phenomenon caused by total dose radiation is effectively avoided, the off-state loss of the device is reduced, and the total dose radiation resistance of the device is improved.
Examples
The embodiment provides a low-radiation leakage high-voltage LDMOS device structure, which comprises three different cross-section structures AB, AC and AD. AB is a direction from the inside of the device along a radius outwards and sequentially passing through the second conductivity type drain region 6, the active region 8, the second conductivity type well region 5, the second conductivity type drift region 4 and the first conductivity type well region 3; AC is the direction from the inside of the device along the radius outwards through the second conductivity type drain region 6, the active region 8, the second conductivity type well region 5, the second conductivity type drift region 4 and the first conductivity type heavily doped region 15; AD is the direction from the inside of the device radially outward through the second conductivity type drain region 6, the active region 8, the second conductivity type well region 5, the second conductivity type drift region 4, the active region 8, the first conductivity type well region 3, the second conductivity type source region 2, and the first conductivity type body region 1.
Along the AB section: comprising a buried oxide layer 14 formed on a first conductivity type substrate 7, a second conductivity type drift region 4 formed on the buried oxide layer 14, a first conductivity type well region 3 located at an inner upper left corner of the second conductivity type drift region 4, a second conductivity type well region 5 located at an inner upper right corner of the second conductivity type drift region 4, a second conductivity type drain region 6 located at an inner upper right corner of the second conductivity type well region 5, a field oxide layer 12 located at a device surface, extending and covering a part of the surface of the second conductivity type well region 5, a polycrystalline gate electrode 10 located above the field oxide layer 12, and a drain electrode 13 located above the second conductivity type drain region 6.
Along the AC section: comprising a buried oxide layer 14 formed on a first conductivity type substrate 7, a second conductivity type drift region 4 formed on the buried oxide layer 14, a first conductivity type heavily doped region 15 located at an inner upper left corner of the second conductivity type drift region 4, a second conductivity type well region 5 located at an inner upper right corner of the second conductivity type drift region 4, a second conductivity type drain region 6 located at an inner upper right corner of the second conductivity type well region 5, a field oxide layer 12 located on a device surface, extending and covering a part of the surface of the second conductivity type well region 5, a polycrystalline gate electrode 10 located above the field oxide layer 12, and a drain electrode 13 located above the second conductivity type drain region 6.
Along the AD section: comprising a buried oxide layer 14 formed on a first conductivity type substrate 7, a second conductivity type drift region 4 formed on the buried oxide layer 14, a first conductivity type well region 3 located at an inner upper left corner of the second conductivity type drift region 4, a first conductivity type body region 1 located inside the first conductivity type 3, a second conductivity type source region 2 located at a right side of the first conductivity type body region 1 within the first conductivity type well region 3, a source electrode 9 located above the first conductivity type body region 1 and above the second conductivity type source region 2 and shorting the first conductivity type body region 1 and the second conductivity type source region 2, a second conductivity type well region 5 located at an inner upper right corner of the second conductivity type drift region 4, a second conductivity type drain region 6 located inside the second conductivity type well region 5, a drain electrode 13 located above the second conductivity type drain region 6, a field oxide layer 12 located at a device surface extending and covering a portion of the surface of the second conductivity type well region 5, a gate oxide layer 11 located below the polycrystalline gate electrode 10 and connected to the field oxide layer 12.
The field oxide layer 12 is made of silicon dioxide or a low-K material with K less than or equal to 2.8.
The heavily doped region 15 of the first conductivity type cuts off the leakage path due to the total dose of radiation.
The second conductive type doped impurity is donor type when the first conductive type doped impurity is acceptor type, and at the moment, the drain electrode is biased to be positive potential relative to the source electrode; the second conductivity type dopant is acceptor type when the first conductivity type dopant is donor type, and the drain electrode is biased to a negative potential with respect to the source electrode.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims of this invention, which are within the skill of those skilled in the art, can be made without departing from the spirit and scope of the invention disclosed herein.
Claims (4)
1. The utility model provides a low radiation electric leakage high voltage LDMOS device structure which characterized in that: the semiconductor device comprises three different cross-sectional structures AB, AC and AD, wherein AB is the direction from the inside of the device to the outside along the radius and sequentially passes through a second conductive type drain region (6), an active region (8), a second conductive type well region (5), a second conductive type drift region (4) and a first conductive type well region (3); AC is the direction from the inside of the device to the outside along the radius and sequentially passes through the second conductive type drain region (6), the active region (8), the second conductive type well region (5), the second conductive type drift region (4) and the first conductive type heavily doped region (15); AD is the direction from the inside of the device to the outside along the radius and sequentially passes through the second conduction type drain region (6), the active region (8), the second conduction type well region (5), the second conduction type drift region (4), the active region (8), the first conduction type well region (3), the second conduction type source region (2) and the first conduction type body region (1);
along the AB section: the device comprises a buried oxide layer (14) formed on a first conductive type substrate (7), a second conductive type drift region (4) formed on the buried oxide layer (14), a first conductive type well region (3) positioned at the inner upper left corner of the second conductive type drift region (4), a second conductive type well region (5) positioned at the inner upper right corner of the second conductive type drift region (4), a second conductive type drain region (6) positioned at the inner upper right corner of the second conductive type well region (5), a field oxide layer (12) positioned on the surface of the device and extending and covering part of the surface of the second conductive type well region (5), a polycrystalline gate electrode (10) positioned above the field oxide layer (12), and a drain electrode (13) positioned above the second conductive type drain region (6);
along the AC section: the semiconductor device comprises a buried oxide layer (14) formed on a first conductive type substrate (7), a second conductive type drift region (4) formed on the buried oxide layer (14), a first conductive type heavily doped region (15) positioned at the inner upper left corner of the second conductive type drift region (4), a second conductive type well region (5) positioned at the inner upper right corner of the second conductive type drift region (4), a second conductive type drain region (6) positioned at the inner upper right corner of the second conductive type well region (5), a field oxide layer (12) positioned on the surface of the device and extending to cover part of the surface of the second conductive type well region (5), a polycrystalline gate electrode (10) positioned above the field oxide layer (12), and a drain electrode (13) positioned above the second conductive type drain region (6);
along the AD section: the semiconductor device comprises a buried oxide layer (14) formed on a first conductive type substrate (7), a second conductive type drift region (4) formed on the buried oxide layer (14), a first conductive type well region (3) located at the inner upper left corner of the second conductive type drift region (4), a first conductive type well region (1) located inside the first conductive type well region (3), a second conductive type source region (2) located at the right side of the first conductive type well region (1) in the first conductive type well region (3), a source electrode (9) located above the first conductive type well region (1) and above the second conductive type source region (2), and shorting the first conductive type well region (1) and the second conductive type source region (2), a second conductive type well region (5) located at the inner upper right corner of the second conductive type drift region (4), a second conductive type drain region (6) located inside the second conductive type well region (5), a drain electrode (13) located above the second conductive type field (6), an oxide layer (12) located above the second conductive type well region (2), and a gate electrode (12) located below the gate electrode (12) and a polycrystalline oxide layer (10) located on the surface of the polycrystalline oxide layer.
2. The low-radiation, leakage, high-voltage LDMOS device structure of claim 1, wherein: the field oxide layer (12) is made of silicon dioxide or a low-K material with K less than or equal to 2.8.
3. The low-radiation, leakage, high-voltage LDMOS device structure of claim 1, wherein: the heavily doped region (15) of the first conductivity type cuts off the leakage path due to the total dose of radiation.
4. The low-radiation, leakage, high-voltage LDMOS device structure of claim 1, wherein: the second conductive type doped impurity is donor type when the first conductive type doped impurity is acceptor type, and at the moment, the drain electrode is biased to be positive potential relative to the source electrode; the second conductivity type dopant is acceptor type when the first conductivity type dopant is donor type, and the drain electrode is biased to a negative potential with respect to the source electrode.
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| CN114823631B (en) * | 2022-04-27 | 2023-05-26 | 电子科技大学 | High-voltage device structure of anti-radiation |
| CN117238970B (en) * | 2023-11-13 | 2024-02-09 | 中国电子科技集团公司第五十八研究所 | High-voltage radiation-resistant lateral MOSFET device |
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| CN101840935B (en) * | 2010-05-17 | 2012-02-29 | 电子科技大学 | SOI (Silicon-on-insulator) MOSFET lateral (metal-oxide-semiconductor field effect transistor) device |
| US10038058B2 (en) * | 2016-05-07 | 2018-07-31 | Silicon Space Technology Corporation | FinFET device structure and method for forming same |
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