CN114597251B - Shielding grid VDMOS for resisting total dose radiation reinforcement - Google Patents
Shielding grid VDMOS for resisting total dose radiation reinforcement Download PDFInfo
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
Abstract
The invention provides a shielded gate VDMOS resisting total dose radiation reinforcement, which comprises the following components: the semiconductor device comprises a drain metal, a heavily doped first-conductivity-type semiconductor substrate, a first-layer first-conductivity-type semiconductor drift region, a second-conductivity-type semiconductor well region, a heavily doped second-conductivity-type semiconductor ohmic contact region, a heavily doped first-conductivity-type semiconductor source region, a shielding gate polysilicon electrode, a shielding gate dielectric layer, an isolation dielectric layer, a gate dielectric layer, an inter-gate-source dielectric layer and source metal. The invention provides a drift region non-uniform doping distribution of a shielded gate VDMOS, which can lead the longitudinal electric field of the drift region to be uniformly distributed after a device is irradiated by a certain dose of total dose, and the breakdown voltage at the moment is the maximum value. Thus, the device undergoes a first increase and then decrease change in breakdown voltage as the radiation dose increases when subjected to the total dose of radiation, such that a greater radiation dose is required to degrade the device to failure.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a shielded gate VDMOS reinforced by total dose radiation resistance.
Background
In contrast to conventional trench-gate VDMOS, the shield gate VDMOS (SGT VDMOS) provides a polysilicon shield gate connected to the source below the gate polysilicon in the trench. The shielding grid not only modulates the longitudinal electric field of the drift region as a field plate in the body to ensure that the breakdown voltage of the device is increased, but also most of grid-drain capacitance C gd Converted to gate-source capacitance C gs So that the device has higher switching speed. However, the more uniform drift region electric field distribution also makes the breakdown voltage degradation of the shielded gate VDMOS at the total dose of radiation more severe. When the shielded gate VDMOS is irradiated by total dose, fixed positive charges and interface state charges are formed at the semiconductor interface of the internal oxide layer, and the net charge quantity of the fixed positive charges and the interface state charges is positive. The positive charges in the oxide layer on the side wall of the shielding gate change the longitudinal electric field distribution of the drift region, the electric field at the bottom of the trench is reduced, P base -N drift The junction electric field is enhanced resulting in a decrease in breakdown voltage. To limit this degradation process, a total dose radiation-resistant reinforcement design of the shielded gate VDMOS is required.
Disclosure of Invention
In view of the degradation phenomenon existing in the total dose radiation in the prior art, the invention provides a shielded gate VDMOS structure capable of inhibiting breakdown voltage degradation in the total dose radiation process. The structure adopts non-uniform drift region doping distribution, so that the longitudinal electric field of the drift region is uniformly distributed after the device is subjected to a certain dose of total dose radiation, the breakdown voltage is the maximum value at the moment, the breakdown voltage is smaller than the maximum value when the radiation dose is smaller than the maximum value, and the breakdown voltage is smaller than the maximum value when the radiation dose exceeds the maximum value. Therefore, when the device provided by the invention is subjected to total dose radiation, as the radiation dose increases, the breakdown voltage changes from increasing to decreasing, which delays the failure of the device, so that a larger radiation dose is required to degrade the device to failure.
In order to achieve the above objective, the present invention proposes a shielded gate VDMOS device with a non-uniformly doped drift region, where the drift region is divided into two parts, a first layer drift region below and a second layer drift region above, the doping concentration of the first layer drift region increases linearly from top to bottom, and the second layer drift region is uniformly doped with a low concentration. By adopting the doping distribution, the longitudinal electric field of the drift region can be uniformly distributed when a certain amount of positive charges exist in the oxidation layer of the side wall of the shielding gate.
The technical scheme adopted by the invention is as follows:
the utility model provides a shielding gate VDMOS of anti total dose radiation reinforcement, including drain metal 1, heavily doped first conductivity type semiconductor substrate 2, first layer first conductivity type semiconductor drift region 3, second layer first conductivity type semiconductor drift region 4, second conductivity type semiconductor well region 5, heavily doped second conductivity type semiconductor ohmic contact region 6, heavily doped first conductivity type semiconductor source region 7, shielding gate polycrystalline silicon electrode 8, gate polycrystalline silicon electrode 9, shielding gate dielectric layer 10, isolation dielectric layer 11, gate dielectric layer 12, inter-gate source dielectric layer 13, source metal 14;
a heavily doped first conductivity type semiconductor substrate 2 is located above the drain metal 1, a first layer of first conductivity type semiconductor drift region 3 is located above the heavily doped first conductivity type semiconductor substrate 2, and a second layer of first conductivity type semiconductor drift region 4 is located above the first layer of first conductivity type semiconductor drift region 3; the second layer of the first conductivity type semiconductor drift region 4 has a doping concentration of less than 1e16cm -3 The doping concentration of the first layer first conductivity type semiconductor drift region 3 is linearly distributed in an increasing manner from top to bottom; and the doping concentration of the first layer first conductive type semiconductor drift region 3 at the junction with the second layer first conductive type semiconductor drift region 4 is the same as the doping concentration of the second layer first conductive type semiconductor drift region 4; the second conductive type semiconductor well region 5 is positioned above the second layer first conductive type semiconductor drift region 4, the heavily doped second conductive type semiconductor ohmic contact region 6 is positioned in the middle above the second conductive type semiconductor well region 5, and two sides of the heavily doped second conductive type semiconductor ohmic contact region 6 are heavily doped with the first conductive type semiconductor source region 7; a groove structure formed by the shielding gate polysilicon electrode 8, the gate polysilicon electrode 9, the shielding gate dielectric layer 10 and the isolation dielectric layer 11 extends into the first layer of the first conductivity type semiconductor drift region 3, and the groove structure is positioned at two sides of a cell; inside the trench, a shielding gate polysilicon electrode 8 is positioned below the gate polysilicon electrode 9, and is separated by an isolation medium layer 11, and the space between the shielding gate polysilicon electrode 8 and the first layer first conductivity type semiconductor drift region 3 and the space between the shielding gate polysilicon electrode 8 and the second layer first conductivity type semiconductor drift region 4 are respectively formed byThe shielding gate dielectric layer 10 is separated, and the gate dielectric layer 12 is separated between the gate polysilicon electrode 9 and the second conductive type semiconductor well region 5 and between the gate polysilicon electrode 9 and the heavily doped first conductive type semiconductor source region 7; the inter-gate-source dielectric layer 13 is located above the gate polysilicon electrode 9, and the inter-gate-source dielectric layer 13 covers a part of the heavily doped first conductivity type semiconductor source region 7; the source metal 14 is located above the heavily doped second conductivity type semiconductor ohmic contact region 6 and covers another portion of the heavily doped first conductivity type semiconductor source region 7; the gate polysilicon electrode 9 is connected with the gate potential, the drain metal 1 is connected with the drain potential, the shielding gate polysilicon electrode 8 is short-circuited with the source metal 14 and is connected with the source potential.
Preferably, the heavily doped second conductivity type semiconductor ohmic contact region 6 is deeper than the heavily doped first conductivity type semiconductor source region 7 and not deeper than the second conductivity type semiconductor well region 5.
Preferably, the source metal 14 protrudes into the semiconductor material and is still in contact with the heavily doped second conductivity type semiconductor ohmic contact region 6 and the heavily doped first conductivity type semiconductor source region 7.
Preferably, the dielectric layer material is silicon dioxide or a high-K material with a dielectric constant higher than that of silicon dioxide.
Preferably, the semiconductor material is silicon or silicon carbide.
Preferably, the first conductivity type semiconductor is an N-type semiconductor, and the second conductivity type semiconductor is a P-type semiconductor; or the first conductive type semiconductor is a P-type semiconductor and the second conductive type semiconductor is an N-type semiconductor.
Preferably, the doping concentration of heavy doping is more than 1e19cm -3 。
The beneficial effects of the invention are as follows: the structure adopts non-uniform drift region doping distribution, so that the longitudinal electric field of the drift region is uniformly distributed after the device is subjected to a certain dose of total dose radiation, the breakdown voltage is the maximum value at the moment, the breakdown voltage is smaller than the maximum value when the radiation dose is smaller than the maximum value, and the breakdown voltage is smaller than the maximum value when the radiation dose exceeds the maximum value. Therefore, when the device provided by the invention is subjected to total dose radiation, as the radiation dose increases, the breakdown voltage changes from increasing to decreasing, which delays the failure of the device, so that a larger radiation dose is required to degrade the device to failure.
Drawings
Fig. 1 is a schematic diagram of a cell structure of a shielding gate VDMOS reinforced by radiation of an anti-total dose according to embodiment 1 of the present invention.
Fig. 2 shows a lateral electric field distribution in a shielded gate VDMOS drift region and a shielded gate oxide layer reinforced by radiation of a total dose according to embodiment 1 of the present invention.
Fig. 3 is a diagram showing a doping concentration profile of a drift region theoretically deduced in example 1 of the present invention.
Fig. 4 is a doping concentration profile of the drift region actually used in embodiment 1 of the present invention.
Fig. 5 is a schematic diagram of the longitudinal electric field distribution of the drift region of the device according to example 1 when the radiation dose is equal to the set value.
Fig. 6 is a schematic diagram of the longitudinal electric field distribution of the drift region of the device according to the present invention in example 1 when the radiation dose is smaller than the set value.
Fig. 7 is a schematic diagram of the longitudinal electric field distribution of the drift region of the device according to the present invention in example 1 when the radiation dose is larger than the set value.
Fig. 8 is a graph showing the breakdown voltage of the device according to embodiment 1 of the present invention as a function of radiation dose.
1 is drain metal, 2 is a heavily doped first conductivity type semiconductor substrate, 3 is a first layer first conductivity type semiconductor drift region, 4 is a second layer first conductivity type semiconductor drift region, 5 is a second conductivity type semiconductor well region, 6 is a heavily doped second conductivity type semiconductor ohmic contact region, 7 is a heavily doped first conductivity type semiconductor source region, 8 is a shielded gate polysilicon electrode, 9 is a gate polysilicon electrode, 10 is a shielded gate dielectric layer, 11 is an isolation dielectric layer, 12 is a gate dielectric layer, 13 is an inter-gate source dielectric layer, and 14 is source metal.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Example 1
The embodiment provides a shielding gate VDMOS with reinforced radiation resisting total dose, and the cell structure comprises:
the semiconductor device comprises a drain metal 1, a heavily doped first-conductivity-type semiconductor substrate 2, a first-layer first-conductivity-type semiconductor drift region 3, a second-layer first-conductivity-type semiconductor drift region 4, a second-conductivity-type semiconductor well region 5, a heavily doped second-conductivity-type semiconductor ohmic contact region 6, a heavily doped first-conductivity-type semiconductor source region 7, a shielding gate polysilicon electrode 8, a gate polysilicon electrode 9, a shielding gate dielectric layer 10, an isolation dielectric layer 11, a gate dielectric layer 12, an inter-gate-source dielectric layer 13 and a source metal 14;
a heavily doped first conductivity type semiconductor substrate 2 is located above the drain metal 1, a first layer of first conductivity type semiconductor drift region 3 is located above the heavily doped first conductivity type semiconductor substrate 2, and a second layer of first conductivity type semiconductor drift region 4 is located above the first layer of first conductivity type semiconductor drift region 3; the second layer of the first conductivity type semiconductor drift region 4 has a doping concentration of less than 1e16cm -3 The doping concentration of the first layer first conductivity type semiconductor drift region 3 is linearly distributed in an increasing manner from top to bottom; and the doping concentration of the first layer first conductive type semiconductor drift region 3 at the junction with the second layer first conductive type semiconductor drift region 4 is the same as the doping concentration of the second layer first conductive type semiconductor drift region 4; the second conductive type semiconductor well region 5 is positioned above the second layer first conductive type semiconductor drift region 4, the heavily doped second conductive type semiconductor ohmic contact region 6 is positioned in the middle above the second conductive type semiconductor well region 5, and the two sides of the heavily doped second conductive type semiconductor ohmic contact region 6 are heavily doped with the first conductive type semiconductor sourceZone 7; a groove structure formed by the shielding gate polysilicon electrode 8, the gate polysilicon electrode 9, the shielding gate dielectric layer 10 and the isolation dielectric layer 11 extends into the first layer of the first conductivity type semiconductor drift region 3, and the groove structure is positioned at two sides of a cell; inside the trench, a shielding gate polysilicon electrode 8 is positioned below a gate polysilicon electrode 9, the shielding gate polysilicon electrode 8 and the first layer of the first conductivity type semiconductor drift region 3 are separated by an isolation dielectric layer 11, the shielding gate polysilicon electrode 8 and the second layer of the first conductivity type semiconductor drift region 4 are separated by a shielding gate dielectric layer 10, and the gate polysilicon electrode 9 and the second conductivity type semiconductor well region 5, and the gate polysilicon electrode 9 and the heavily doped first conductivity type semiconductor source region 7 are separated by a gate dielectric layer 12; the inter-gate-source dielectric layer 13 is located above the gate polysilicon electrode 9, and the inter-gate-source dielectric layer 13 covers a part of the heavily doped first conductivity type semiconductor source region 7; the source metal 14 is located above the heavily doped second conductivity type semiconductor ohmic contact region 6 and covers another portion of the heavily doped first conductivity type semiconductor source region 7; the gate polysilicon electrode 9 is connected with the gate potential, the drain metal 1 is connected with the drain potential, the shielding gate polysilicon electrode 8 is short-circuited with the source metal 14 and is connected with the source potential.
Preferably, the dielectric layer material is silicon dioxide or a high-K material with a dielectric constant higher than silicon dioxide.
Preferably, the semiconductor material is silicon or silicon carbide.
Preferably, the first conductivity type semiconductor is an N-type semiconductor, and the second conductivity type semiconductor is a P-type semiconductor; or the first conductive type semiconductor is a P-type semiconductor and the second conductive type semiconductor is an N-type semiconductor.
The doping concentration of heavy doping is more than 1e19cm -3 。
Taking a first conductive type semiconductor as an N-type semiconductor, a second conductive type semiconductor as a P-type semiconductor, a dielectric layer material as silicon dioxide, and a semiconductor material as silicon as an example to explain the basic working principle: when the grid bias voltage is larger than the threshold voltage, an inversion layer is formed on the surface of the channel region, and under the action of the high voltage of the drain electrode, electrons flow out from the source electrode and sequentially pass through the channel regionThe second layer drift region, the first layer drift region, then enters the substrate to form a complete current path, which is the on state of the device. When the grid bias voltage is smaller than the threshold voltage, the channel region does not form an inversion layer, the device is in an off state, and the channel region is formed by P base -N drift The junction assumes the drain-source voltage.
The structure provided by the invention has the following effect of improving the total dose radiation degradation: in the total dose radiation process, electron-hole pairs are excited in an oxide layer in the device, electrons with higher mobility move out of the oxide layer under the action of an electric field, holes with lower mobility are trapped by hole traps in the oxide layer to form fixed positive charges, and the fixed positive charges of the oxide layer have adverse effects on the electrical characteristics of the device. Wherein, the fixed positive charges in the oxidation layer of the side wall of the shielding gate destroy the original charge balance of the device, so that the longitudinal electric field of the drift region is weakened near the bottom of the trench and is reduced at P base -N drift The enhancement near the junction reduces the breakdown voltage of the device. As the radiation dose increases, the variation of the longitudinal electric field of such drift region becomes more severe, and thus the breakdown voltage of the device continues to decrease. In the practical application process of the device, when the breakdown voltage is reduced to the practical voltage at two ends of the drain and source of the device, the device is in failure. In order to suppress such degradation, the doping profile of the drift region may be adjusted such that the longitudinal electric field of the drift region is uniformly distributed when a certain radiation dose, i.e. a certain fixed positive charge, is present in the shield gate oxide layer, at which time the breakdown voltage of the device is at a maximum. Then, when the radiation dose is smaller than the set value, the longitudinal electric field of the drift region is at P base -N drift Weaker near the junction and stronger near the trench bottom; when the radiation dose is larger than the set value, the longitudinal electric field of the drift region is at P base -N drift Stronger near the junction and weaker near the trench bottom. When the radiation dose is larger or smaller than the set value, the longitudinal electric field of the drift region is non-uniform, and the breakdown voltage is smaller than the maximum value, so that the breakdown voltage of the device changes from increasing to decreasing with the increase of the radiation dose, thereby the radiation dose required by the breakdown voltage to drop to the failure value becomes larger, and the failure process of the device is delayed。
The impurity concentration profile of the drift region to be used in the present invention is quantitatively deduced as follows:
assuming that the longitudinal electric field of the drift region of the device is uniformly distributed after being subjected to a certain dose of total dose radiation, the potential distribution in the y-direction, i.e. longitudinal, in the drift region is proportional to the drift region depth y:
V(y)＝E y ·y＝E c ·y (1)
wherein V (y) is the on-line distance P in the drift region base -N drift A drift region potential at junction depth y, E y For the drift region longitudinal electric field, E c Is the critical breakdown field.
In the lateral direction of the drift region, according to the boundary conditions of maxwell's equations, it is possible to obtain:
wherein ε is ox Dielectric constant of oxide layer, ε si Is the dielectric constant of silicon, E ox To shield the transverse electric field in the gate oxide layer E x Is the lateral electric field in silicon.
As shown in fig. 2, the lateral electric field distribution of the device is shown, so that the potential at any depth y in the drift region centerline can also be expressed as:
wherein V is ox V is the pressure drop in the oxide layer s Is the voltage drop across the semiconductor, E ox To shield the transverse electric field in the gate oxide layer, t ox To shield the thickness of the gate oxide layer E x Is a lateral electric field in silicon, W M For drift region width, Q ox For positive charge quantity epsilon in shielding gate oxide layer corresponding to certain radiation dose ox Dielectric constant of oxide layer, ε si Is the dielectric constant of silicon.
In addition, in the lateral direction, there are:
wherein E is x Is a lateral electric field in silicon, W M For drift region width ε si Is the dielectric constant of silicon, q is the meta-charge, N D (y) is the doping concentration of the drift region at a depth y.
Substituting (1) and (4) into (3) can solve the doping concentration N of the drift region D The variation relation of (y) with depth y is:
doping concentration N of visible drift region D (y) is a linear function of depth y, and a schematic diagram thereof is shown in FIG. 3. At a depth less than L D1 When the resolved doping concentration is negative, i.e. the doping type is P-type, which conflicts with the assumption that there will be a depth less than L D1 The drift region doping concentration at this time is set to be a uniform lightly doped N-type as shown in fig. 4.
The breakdown voltage simulation of a shielded gate VDMOS with the doping profile described in the above method is performed, and FIG. 5 shows the longitudinal electric field profile of the drift region when the radiation dose is equal to the set value, and it can be seen that the electric field profile in the whole drift region is approximately uniform; FIG. 6 shows the longitudinal electric field distribution of the drift region when the radiation dose is less than the set value, and the electric field is gradually increased from the PN junction to the bottom of the trench; fig. 7 shows the longitudinal electric field distribution of the drift region when the radiation dose is greater than the set value, and the electric field gradually decreases from the PN junction to the bottom of the trench. Fig. 8 is a schematic diagram showing the breakdown voltage of the device according to the present invention as a function of radiation dose, and the breakdown voltage of the device increases and decreases with increasing radiation dose, consistent with theoretical predictions.
Example 2
The difference between this embodiment and embodiment 1 is that: the heavily doped second conductivity type semiconductor ohmic contact region 6 is deeper than the heavily doped first conductivity type semiconductor source region 7 and not deeper than the second conductivity type semiconductor well region 5.
Example 3
The difference between this embodiment and embodiment 1 is that: the source metal 14 protrudes into the semiconductor material and is still in contact with the heavily doped second conductivity type semiconductor ohmic contact region 6 and the heavily doped first conductivity type semiconductor source region 7.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims of this invention, which are within the skill of those skilled in the art, can be made without departing from the spirit and scope of the invention disclosed herein.
Claims (7)
1. A shielded gate VDMOS resistant to total dose radiation reinforcement, characterized by: the semiconductor device comprises drain metal (1), a heavily doped first-conductivity-type semiconductor substrate (2), a first-layer first-conductivity-type semiconductor drift region (3), a second-layer first-conductivity-type semiconductor drift region (4), a second-conductivity-type semiconductor well region (5), a heavily doped second-conductivity-type semiconductor ohmic contact region (6), a heavily doped first-conductivity-type semiconductor source region (7), a shielding gate polysilicon electrode (8), a gate polysilicon electrode (9), a shielding gate dielectric layer (10), an isolation dielectric layer (11), a gate dielectric layer (12), an inter-gate-source dielectric layer (13) and source metal (14);
a heavily doped first conductivity type semiconductor substrate (2) is located above the drain metal (1), a first layer of first conductivity type semiconductor drift region (3) is located above the heavily doped first conductivity type semiconductor substrate (2), and a second layer of first conductivity type semiconductor drift region (4) is located above the first layer of first conductivity type semiconductor drift region (3); the second layer of the first conductivity type semiconductor drift region (4) has a doping concentration of less than 1e16cm -3 The doping concentration of the first layer first conductivity type semiconductor drift region (3) is linearly increasing distribution from top to bottom; and a first layer of first conductivityThe doping concentration of the type semiconductor drift region (3) at the junction with the second layer first conductivity type semiconductor drift region (4) is the same as the doping concentration of the second layer first conductivity type semiconductor drift region (4); the second conductive type semiconductor well region (5) is positioned above the second layer first conductive type semiconductor drift region (4), the heavily doped second conductive type semiconductor ohmic contact region (6) is positioned in the middle of the upper part of the second conductive type semiconductor well region (5), and the heavily doped first conductive type semiconductor source region (7) is arranged at two sides of the heavily doped second conductive type semiconductor ohmic contact region (6); a groove structure formed by a shielding gate polysilicon electrode (8), a gate polysilicon electrode (9), a shielding gate dielectric layer (10) and an isolation dielectric layer (11) stretches into the first layer first conductivity type semiconductor drift region (3), and the groove structure is positioned at two sides of a cell; inside the trench, a shielding gate polysilicon electrode (8) is positioned below a gate polysilicon electrode (9), the shielding gate polysilicon electrode (8) and the first layer first conductive type semiconductor drift region (3) are separated by an isolation dielectric layer (11), the shielding gate polysilicon electrode (8) and the second layer first conductive type semiconductor drift region (4) are separated by a shielding gate dielectric layer (10), the gate polysilicon electrode (9) and the second conductive type semiconductor well region (5), and the gate polysilicon electrode (9) and the heavily doped first conductive type semiconductor source region (7) are separated by a gate dielectric layer (12); the inter-gate-source dielectric layer (13) is positioned above the gate polysilicon electrode (9), and the inter-gate-source dielectric layer (13) covers a part of the heavily doped first conductive type semiconductor source region (7); the source metal (14) is positioned above the heavily doped second-conductivity-type semiconductor ohmic contact region (6) and covers the other part of the heavily doped first-conductivity-type semiconductor source region (7); the gate polysilicon electrode (9) is connected with the gate potential, the drain metal (1) is connected with the drain potential, and the shielding gate polysilicon electrode (8) is in short circuit with the source metal (14) and is connected with the source potential.
2. A shielded gate VDMOS for radiation-hardened total dose as claimed in claim 1, wherein: the depth of the heavily doped second conductivity type semiconductor ohmic contact region (6) is deeper than the heavily doped first conductivity type semiconductor source region (7) and not deeper than the second conductivity type semiconductor well region (5).
3. A shielded gate VDMOS for radiation-hardened total dose as claimed in claim 1, wherein: the source metal (14) protrudes into the semiconductor material and is still in contact with the heavily doped second conductivity type semiconductor ohmic contact region (6) and the heavily doped first conductivity type semiconductor source region (7).
4. A shielded gate VDMOS for radiation-hardened total dose as claimed in claim 1, wherein: the dielectric layer material is silicon dioxide or a high-K material with dielectric constant higher than that of silicon dioxide.
5. A shielded gate VDMOS for radiation-hardened total dose as claimed in claim 1, wherein: the semiconductor material is silicon or silicon carbide.
6. A shielded gate VDMOS for radiation-hardened total dose as claimed in claim 1, wherein: the first conductive type semiconductor is an N-type semiconductor, and the second conductive type semiconductor is a P-type semiconductor; or the first conductive type semiconductor is a P-type semiconductor and the second conductive type semiconductor is an N-type semiconductor.
7. A shielded gate VDMOS for radiation protection as claimed in any one of claims 1 to 6, wherein: the doping concentration of heavy doping is more than 1e19cm -3 。
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